Setting log file to 'G:/fpga/MXO2/system/impl1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file D:/diamond/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
(VERI-1482) Analyzing Verilog file G:/fpga/MXO2/system/system_top.v
(VERI-1482) Analyzing Verilog file G:/fpga/MXO2/system/DS18B20Z.v
(VERI-1482) Analyzing Verilog file G:/fpga/MXO2/system/OLED12832.v
(VERI-1482) Analyzing Verilog file G:/fpga/MXO2/system/time_generator.v
(VERI-1482) Analyzing Verilog file G:/fpga/MXO2/system/baud_generator.v
(VERI-1482) Analyzing Verilog file G:/fpga/MXO2/system/beeper_control.v
(VERI-1482) Analyzing Verilog file G:/fpga/MXO2/system/uart_rx.v
(VERI-1482) Analyzing Verilog file G:/fpga/MXO2/system/uart_top.v
(VERI-1482) Analyzing Verilog file G:/fpga/MXO2/system/uart_tx.v
(VERI-1482) Analyzing Verilog file G:/fpga/MXO2/system/beeper.v
INFO - G:/fpga/MXO2/system/system_top.v(1,8-1,18) (VERI-1018) compiling module system_top
INFO - G:/fpga/MXO2/system/system_top.v(1,1-116,10) (VERI-9000) elaborating module 'system_top'
INFO - G:/fpga/MXO2/system/time_generator.v(1,1-91,10) (VERI-9000) elaborating module 'time_generator_uniq_1'
INFO - G:/fpga/MXO2/system/DS18B20Z.v(1,1-204,10) (VERI-9000) elaborating module 'DS18B20Z_uniq_1'
INFO - G:/fpga/MXO2/system/OLED12832.v(1,1-366,10) (VERI-9000) elaborating module 'OLED12832_uniq_1'
INFO - G:/fpga/MXO2/system/uart_top.v(1,1-161,10) (VERI-9000) elaborating module 'uart_top_uniq_1'
INFO - G:/fpga/MXO2/system/beeper_control.v(1,1-59,10) (VERI-9000) elaborating module 'beeper_control_uniq_1'
INFO - G:/fpga/MXO2/system/baud_generator.v(1,1-34,10) (VERI-9000) elaborating module 'baud_generator_uniq_1'
INFO - G:/fpga/MXO2/system/baud_generator.v(1,1-34,10) (VERI-9000) elaborating module 'baud_generator_uniq_2'
INFO - G:/fpga/MXO2/system/uart_rx.v(1,1-69,10) (VERI-9000) elaborating module 'uart_rx_uniq_1'
INFO - G:/fpga/MXO2/system/uart_tx.v(1,1-41,10) (VERI-9000) elaborating module 'uart_tx_uniq_1'
INFO - G:/fpga/MXO2/system/beeper.v(1,1-64,10) (VERI-9000) elaborating module 'Beeper_uniq_1'
Done: design load finished with (0) errors, and (0) warnings