module bcd( clk , rst_n , din , din_vld , dout , dout_vld ); //参数定义 parameter DATA_W = 8 ; //输入信号定义 input clk ; input rst_n ; input [DATA_W-1:0] din ; input din_vld ; //输出信号定义 output reg [11:0] dout ; output reg dout_vld ; //中间信号定义 reg [19:0] din_temp ; reg [19:0] din_temp_ff0 ; reg [19:0] din_temp_ff1 ; reg [19:0] din_temp_ff2 ; reg [19:0] din_temp_ff3 ; reg din_vld_temp ; reg din_vld_temp_ff0 ; reg din_vld_temp_ff1 ; reg din_vld_temp_ff2 ; reg din_vld_temp_ff3 ; wire[DATA_W-1:0] din_a_temp ; wire[DATA_W-1:0] din_a_temp_ff0 ; wire[DATA_W-1:0] din_a_temp_ff1 ; wire[DATA_W-1:0] din_a_temp_ff2 ; wire[DATA_W-1:0] din_a_temp_ff3 ; wire[3:0] din_b_temp ; wire[3:0] din_b_temp_ff0 ; wire[3:0] din_b_temp_ff1 ; wire[3:0] din_b_temp_ff2 ; wire[3:0] din_b_temp_ff3 ; wire[3:0] din_c_temp ; wire[3:0] din_c_temp_ff0 ; wire[3:0] din_c_temp_ff1 ; wire[3:0] din_c_temp_ff2 ; wire[3:0] din_c_temp_ff3 ; wire[3:0] din_d_temp ; wire[3:0] din_d_temp_ff0 ; wire[3:0] din_d_temp_ff1 ; wire[3:0] din_d_temp_ff2 ; wire[3:0] din_d_temp_ff3 ; wire[DATA_W-1:0] din_add_a_temp ; wire[DATA_W-1:0] din_add_a_temp_ff0 ; wire[DATA_W-1:0] din_add_a_temp_ff1 ; wire[DATA_W-1:0] din_add_a_temp_ff2 ; wire[DATA_W-1:0] din_add_a_temp_ff3 ; wire[3:0] din_add_b_temp ; wire[3:0] din_add_b_temp_ff0 ; wire[3:0] din_add_b_temp_ff1 ; wire[3:0] din_add_b_temp_ff2 ; wire[3:0] din_add_b_temp_ff3 ; wire[3:0] din_add_c_temp ; wire[3:0] din_add_c_temp_ff0 ; wire[3:0] din_add_c_temp_ff1 ; wire[3:0] din_add_c_temp_ff2 ; wire[3:0] din_add_c_temp_ff3 ; wire[3:0] din_add_d_temp ; wire[3:0] din_add_d_temp_ff0 ; wire[3:0] din_add_d_temp_ff1 ; wire[3:0] din_add_d_temp_ff2 ; wire[3:0] din_add_d_temp_ff3 ; wire[20:0] din_shift_temp ; wire[20:0] din_shift_temp_ff0 ; wire[20:0] din_shift_temp_ff1 ; wire[20:0] din_shift_temp_ff2 ; wire[20:0] din_shift_temp_ff3 ; always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin din_temp <= 0; end else if(din_vld)begin din_temp <= {9'b0,din,3'b0}; end end always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin din_vld_temp <= 1'b0; end else if(din_vld)begin din_vld_temp <= din_vld; end else begin din_vld_temp <= 1'b0; end end assign din_a_temp = din_temp[7:0]; assign din_b_temp = din_temp[11:8]; assign din_c_temp = din_temp[15:12]; assign din_d_temp = din_temp[19:16]; assign din_add_a_temp = din_a_temp; assign din_add_b_temp = din_b_temp + (din_b_temp>=5?4'd3:4'd0); assign din_add_c_temp = din_c_temp + (din_c_temp>=5?4'd3:4'd0); assign din_add_d_temp = din_d_temp + (din_d_temp>=5?4'd3:4'd0); assign din_shift_temp = {din_add_d_temp,din_add_c_temp,din_add_b_temp,din_add_a_temp,1'b0}; always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin din_temp_ff0 <= 0; end else if(din_vld_temp)begin din_temp_ff0 <= din_shift_temp[19:0]; end end always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin din_vld_temp_ff0 <= 1'b0; end else if(din_vld_temp)begin din_vld_temp_ff0 <= 1'b1; end else begin din_vld_temp_ff0 <= 1'b0; end end assign din_a_temp_ff0 = din_temp_ff0[7:0]; assign din_b_temp_ff0 = din_temp_ff0[11:8]; assign din_c_temp_ff0 = din_temp_ff0[15:12]; assign din_d_temp_ff0 = din_temp_ff0[19:16]; assign din_add_a_temp_ff0 = din_a_temp_ff0; assign din_add_b_temp_ff0 = din_b_temp_ff0 + (din_b_temp_ff0>=5?4'd3:4'd0); assign din_add_c_temp_ff0 = din_c_temp_ff0 + (din_c_temp_ff0>=5?4'd3:4'd0); assign din_add_d_temp_ff0 = din_d_temp_ff0 + (din_d_temp_ff0>=5?4'd3:4'd0); assign din_shift_temp_ff0 = {din_add_d_temp_ff0,din_add_c_temp_ff0,din_add_b_temp_ff0,din_add_a_temp_ff0,1'b0}; always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin din_temp_ff1 <= 0; end else if(din_vld_temp_ff0)begin din_temp_ff1 <= din_shift_temp_ff0[19:0]; end end always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin din_vld_temp_ff1 <= 1'b0; end else if(din_vld_temp_ff0)begin din_vld_temp_ff1 <= 1'b1; end else begin din_vld_temp_ff1 <= 1'b0; end end assign din_a_temp_ff1 = din_temp_ff1[7:0]; assign din_b_temp_ff1 = din_temp_ff1[11:8]; assign din_c_temp_ff1 = din_temp_ff1[15:12]; assign din_d_temp_ff1 = din_temp_ff1[19:16]; assign din_add_a_temp_ff1 = din_a_temp_ff1; assign din_add_b_temp_ff1 = din_b_temp_ff1 + (din_b_temp_ff1>=5?4'd3:4'd0); assign din_add_c_temp_ff1 = din_c_temp_ff1 + (din_c_temp_ff1>=5?4'd3:4'd0); assign din_add_d_temp_ff1 = din_d_temp_ff1 + (din_d_temp_ff1>=5?4'd3:4'd0); assign din_shift_temp_ff1 = {din_add_d_temp_ff1,din_add_c_temp_ff1,din_add_b_temp_ff1,din_add_a_temp_ff1,1'b0}; always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin din_temp_ff2 <= 0; end else if(din_vld_temp_ff1)begin din_temp_ff2 <= din_shift_temp_ff1[19:0]; end end always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin din_vld_temp_ff2 <= 1'b0; end else if(din_vld_temp_ff1)begin din_vld_temp_ff2 <= 1'b1; end else begin din_vld_temp_ff2 <= 1'b0; end end assign din_a_temp_ff2 = din_temp_ff2[7:0]; assign din_b_temp_ff2 = din_temp_ff2[11:8]; assign din_c_temp_ff2 = din_temp_ff2[15:12]; assign din_d_temp_ff2 = din_temp_ff2[19:16]; assign din_add_a_temp_ff2 = din_a_temp_ff2; assign din_add_b_temp_ff2 = din_b_temp_ff2 + (din_b_temp_ff2>=5?4'd3:4'd0); assign din_add_c_temp_ff2 = din_c_temp_ff2 + (din_c_temp_ff2>=5?4'd3:4'd0); assign din_add_d_temp_ff2 = din_d_temp_ff2 + (din_d_temp_ff2>=5?4'd3:4'd0); assign din_shift_temp_ff2 = {din_add_d_temp_ff2,din_add_c_temp_ff2,din_add_b_temp_ff2,din_add_a_temp_ff2,1'b0}; always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin din_temp_ff3 <= 0; end else if(din_vld_temp_ff2)begin din_temp_ff3 <= din_shift_temp_ff2[19:0]; end end always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin din_vld_temp_ff3 <= 1'b0; end else if(din_vld_temp_ff2)begin din_vld_temp_ff3 <= 1'b1; end else begin din_vld_temp_ff3 <= 1'b0; end end assign din_a_temp_ff3 = din_temp_ff3[7:0]; assign din_b_temp_ff3 = din_temp_ff3[11:8]; assign din_c_temp_ff3 = din_temp_ff3[15:12]; assign din_d_temp_ff3 = din_temp_ff3[19:16]; assign din_add_a_temp_ff3 = din_a_temp_ff3; assign din_add_b_temp_ff3 = din_b_temp_ff3 + (din_b_temp_ff3>=5?4'd3:4'd0); assign din_add_c_temp_ff3 = din_c_temp_ff3 + (din_c_temp_ff3>=5?4'd3:4'd0); assign din_add_d_temp_ff3 = din_d_temp_ff3 + (din_d_temp_ff3>=5?4'd3:4'd0); assign din_shift_temp_ff3 = {din_add_d_temp_ff3,din_add_c_temp_ff3,din_add_b_temp_ff3,din_add_a_temp_ff3,1'b0}; always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin dout <= 0; end else if(din_vld_temp_ff3)begin dout <= din_shift_temp_ff3[19:8]; end end always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin dout_vld <= 1'b0; end else if(din_vld_temp_ff3)begin dout_vld <= 1'b1; end else begin dout_vld <= 1'b0; end end endmodule