I/O Timing Report 28 potential circuit loops found in timing analysis. Loading design for application iotiming from file step_project01_impl1.ncd. Design name: step_project01 NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-4000HC Package: CSBGA132 Performance: 5 Package Status: Final Version 1.44. Performance Hardware Data Status: Final Version 34.4. Loading design for application iotiming from file step_project01_impl1.ncd. Design name: step_project01 NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-4000HC Package: CSBGA132 Performance: 6 Package Status: Final Version 1.44. Performance Hardware Data Status: Final Version 34.4. Loading design for application iotiming from file step_project01_impl1.ncd. Design name: step_project01 NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-4000HC Package: CSBGA132 Performance: M Package Status: Final Version 1.44. Performance Hardware Data Status: Final Version 34.4. // Design: step_project01 // Package: CSBGA132 // ncd File: step_project01_impl1.ncd // Version: Diamond (64-bit) 3.11.0.396.4 // Written on Thu Feb 18 17:28:28 2021 // M: Minimum Performance Grade // iotiming step_project01_impl1.ncd step_project01_impl1.prf -gui -msgset C:/Users/CROFY/Documents/Diamond/Project/step_project01/promote.xml I/O Timing Report (All units are in ns) Worst Case Results across Performance Grades (M, 6, 5, 4): // Input Setup and Hold Times Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- fpga_rx clk R 1.476 4 0.058 M key[0] clk R 1.013 4 1.077 4 key[1] clk R 1.209 4 0.523 4 key[2] clk R 0.782 4 1.214 4 one_wire clk R 3.867 4 1.631 4 rst_n clk R 11.365 4 0.518 6 // Clock to Output Delay Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ beeper clk R 10.658 4 3.381 M fpga_tx clk R 9.763 4 3.123 M oled_clk clk R 10.275 4 3.233 M oled_csn clk R 9.848 4 3.128 M oled_dat clk R 10.151 4 3.209 M oled_dcn clk R 10.151 4 3.209 M oled_rst clk R 10.273 4 3.275 M // Internal_Clock to Input Port Internal_Clock -------------------------------------------------------- one_wire DS18B20Z_uut/clk_1mhz rst_n clk_c_generated_8 rst_n clk_c_generated_2 rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl rst_n control_module_uut/cl // Internal_Clock to Output Port Internal_Clock -------------------------------------------------------- one_wire DS18B20Z_uut/clk_1mhz WARNING: you must also run trce with hold speed: 4 WARNING: you must also run trce with hold speed: 6