Lattice Synthesis Timing Report -------------------------------------------------------------------------------- Lattice Synthesis Timing Report, Version Thu Feb 18 17:27:00 2021 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design: step_project01 Constraint file: Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 5.000000 -name clk1 [get_nets clk_1mhz] 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 5.000000 -name clk0 [get_nets clk_c] 4096 items scored, 4096 timing errors detected. -------------------------------------------------------------------------------- Error: The following path violates requirements by 74.521ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3AX CK \DS18B20Z_uut/data_out_i0_i15 (from clk_c +) Destination: FD1P3AX D \control_module_uut/tx_data_out_i0_i6 (to clk_c +) Delay: 79.361ns (30.7% logic, 69.3% route), 52 logic levels. Constraint Details: 79.361ns data_path \DS18B20Z_uut/data_out_i0_i15 to \control_module_uut/tx_data_out_i0_i6 violates 5.000ns delay constraint less 0.160ns L_S requirement (totaling 4.840ns) by 74.521ns Path Details: \DS18B20Z_uut/data_out_i0_i15 to \control_module_uut/tx_data_out_i0_i6 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \DS18B20Z_uut/data_out_i0_i15 (from clk_c) Route 1 e 0.941 data_out[15] LUT4 --- 0.493 B to Z i2_3_lut_adj_878 Route 7 e 1.502 n8 LUT4 --- 0.493 C to Z i2_3_lut Route 38 e 2.049 temperature_flag_N_23 LUT4 --- 0.493 C to Z temperature_code_10__I_0_10_i5_3_lut Route 2 e 1.141 temperature_code[4] A1_TO_FCO --- 0.827 A[2] to COUT add_6777_1 Route 1 e 0.020 n54690 FCI_TO_FCO --- 0.157 CIN to COUT add_6777_3 Route 1 e 0.020 n54691 FCI_TO_FCO --- 0.157 CIN to COUT add_6777_5 Route 1 e 0.020 n54692 FCI_TO_F --- 0.598 CIN to S[2] add_6777_7 Route 1 e 0.020 n12045 A1_TO_FCO --- 0.827 A[2] to COUT add_6799_5 Route 1 e 0.020 n54712 FCI_TO_FCO --- 0.157 CIN to COUT add_6799_7 Route 1 e 0.020 n54713 FCI_TO_FCO --- 0.157 CIN to COUT add_6799_9 Route 1 e 0.020 n54714 FCI_TO_F --- 0.598 CIN to S[2] add_6799_11 Route 1 e 0.020 n12097 A1_TO_FCO --- 0.827 A[2] to COUT add_6798_7 Route 1 e 0.020 n54707 FCI_TO_FCO --- 0.157 CIN to COUT add_6798_9 Route 1 e 0.020 n54708 FCI_TO_FCO --- 0.157 CIN to COUT add_6798_11 Route 1 e 0.020 n54709 FCI_TO_F --- 0.598 CIN to S[2] add_6798_cout Route 14 e 2.153 bin_code[20] LUT4 --- 0.493 B to Z \bin_to_bcd_uut/bin_code[17]_bdd_3_lut_2_lut_2_lut Route 1 e 0.020 \bin_to_bcd_uut/n59906 MUXL5 --- 0.233 BLUT to Z \bin_to_bcd_uut/i47415 Route 10 e 1.604 n8116 LUT4 --- 0.493 C to Z i2_4_lut Route 8 e 1.540 bcd_code_24__N_344 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4093_3_lut_4_lut Route 6 e 1.457 \bin_to_bcd_uut/n8120 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4724_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_362 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4766_3_lut_rep_622_4_lut_3_lut_4_lut Route 6 e 1.457 n60837 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i1_2_lut_rep_618_3_lut_4_lut_4_lut Route 1 e 0.941 \bin_to_bcd_uut/n60833 LUT4 --- 0.493 A to Z \bin_to_bcd_uut/bcd_code_24__N_328[3]_bdd_4_lut_47529 Route 1 e 0.020 \bin_to_bcd_uut/n59873 MUXL5 --- 0.233 ALUT to Z \bin_to_bcd_uut/i47400 Route 4 e 1.340 n26_adj_3237 LUT4 --- 0.493 A to Z i2_4_lut_adj_879 Route 7 e 1.502 bcd_code_24__N_371 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4079_3_lut_4_lut Route 7 e 1.502 \bin_to_bcd_uut/n8128 LUT4 --- 0.493 B to Z \bin_to_bcd_uut/i4836_3_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_398 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4004_3_lut_rep_596_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60811 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i4892_3_lut_4_lut Route 9 e 1.574 \bin_to_bcd_uut/bcd_code_24__N_425 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4036_3_lut_rep_585_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60800 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i4992_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_463 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4039_3_lut_rep_573_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60788 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5048_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_499 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4042_3_lut_rep_557_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60772 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5132_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_541 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4189_2_lut_rep_521_4_lut_4_lut Route 4 e 1.340 \bin_to_bcd_uut/n60736 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5342_3_lut_4_lut_3_lut_4_lut Route 5 e 1.405 \bin_to_bcd_uut/bcd_code_24__N_527 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i5473_2_lut_rep_497_3_lut Route 5 e 1.405 \bin_to_bcd_uut/n60712 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i4055_3_lut_rep_489_4_lut Route 2 e 1.141 \bin_to_bcd_uut/n60704 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5468_3_lut_4_lut Route 9 e 1.574 \bin_to_bcd_uut/bcd_code_24__N_572 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4059_3_lut_rep_470_4_lut Route 2 e 1.141 \bin_to_bcd_uut/n60685 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5580_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_623 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4064_3_lut_rep_453_4_lut Route 2 e 1.141 \bin_to_bcd_uut/n60668 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5692_3_lut_4_lut Route 9 e 1.574 \bin_to_bcd_uut/bcd_code_24__N_674 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4068_3_lut_rep_438_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60653 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5804_3_lut_4_lut Route 8 e 1.540 \bin_to_bcd_uut/bcd_code_24__N_725 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4072_3_lut_rep_425_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60640 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5909_3_lut_4_lut Route 6 e 1.457 \bin_to_bcd_uut/bcd_code_24__N_767 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4074_3_lut_rep_413_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60628 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5965_3_lut_rep_407_4_lut Route 1 e 0.941 n60622 LUT4 --- 0.493 B to Z \control_module_uut/mux_263_i7_4_lut Route 1 e 0.941 \control_module_uut/tx_data_out_7__N_2749[6] -------- 79.361 (30.7% logic, 69.3% route), 52 logic levels. Error: The following path violates requirements by 74.521ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3AX CK \DS18B20Z_uut/data_out_i0_i15 (from clk_c +) Destination: FD1P3AX D \control_module_uut/tx_data_out_i0_i6 (to clk_c +) Delay: 79.361ns (30.7% logic, 69.3% route), 52 logic levels. Constraint Details: 79.361ns data_path \DS18B20Z_uut/data_out_i0_i15 to \control_module_uut/tx_data_out_i0_i6 violates 5.000ns delay constraint less 0.160ns L_S requirement (totaling 4.840ns) by 74.521ns Path Details: \DS18B20Z_uut/data_out_i0_i15 to \control_module_uut/tx_data_out_i0_i6 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \DS18B20Z_uut/data_out_i0_i15 (from clk_c) Route 1 e 0.941 data_out[15] LUT4 --- 0.493 B to Z i2_3_lut_adj_878 Route 7 e 1.502 n8 LUT4 --- 0.493 C to Z i2_3_lut Route 38 e 2.049 temperature_flag_N_23 LUT4 --- 0.493 C to Z temperature_code_10__I_0_10_i5_3_lut Route 2 e 1.141 temperature_code[4] A1_TO_FCO --- 0.827 A[2] to COUT add_6777_1 Route 1 e 0.020 n54690 FCI_TO_FCO --- 0.157 CIN to COUT add_6777_3 Route 1 e 0.020 n54691 FCI_TO_F --- 0.598 CIN to S[2] add_6777_5 Route 1 e 0.020 n12047 A1_TO_FCO --- 0.827 A[2] to COUT add_6799_3 Route 1 e 0.020 n54711 FCI_TO_FCO --- 0.157 CIN to COUT add_6799_5 Route 1 e 0.020 n54712 FCI_TO_FCO --- 0.157 CIN to COUT add_6799_7 Route 1 e 0.020 n54713 FCI_TO_FCO --- 0.157 CIN to COUT add_6799_9 Route 1 e 0.020 n54714 FCI_TO_F --- 0.598 CIN to S[2] add_6799_11 Route 1 e 0.020 n12098 A1_TO_FCO --- 0.827 A[2] to COUT add_6798_7 Route 1 e 0.020 n54707 FCI_TO_FCO --- 0.157 CIN to COUT add_6798_9 Route 1 e 0.020 n54708 FCI_TO_FCO --- 0.157 CIN to COUT add_6798_11 Route 1 e 0.020 n54709 FCI_TO_F --- 0.598 CIN to S[2] add_6798_cout Route 14 e 2.153 bin_code[20] LUT4 --- 0.493 D to Z \bin_to_bcd_uut/bin_code[17]_bdd_3_lut_47414_4_lut_4_lut Route 1 e 0.020 \bin_to_bcd_uut/n59905 MUXL5 --- 0.233 ALUT to Z \bin_to_bcd_uut/i47415 Route 10 e 1.604 n8116 LUT4 --- 0.493 C to Z i2_4_lut Route 8 e 1.540 bcd_code_24__N_344 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4093_3_lut_4_lut Route 6 e 1.457 \bin_to_bcd_uut/n8120 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4724_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_362 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4766_3_lut_rep_622_4_lut_3_lut_4_lut Route 6 e 1.457 n60837 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i1_2_lut_rep_618_3_lut_4_lut_4_lut Route 1 e 0.941 \bin_to_bcd_uut/n60833 LUT4 --- 0.493 A to Z \bin_to_bcd_uut/bcd_code_24__N_328[3]_bdd_4_lut_47529 Route 1 e 0.020 \bin_to_bcd_uut/n59873 MUXL5 --- 0.233 ALUT to Z \bin_to_bcd_uut/i47400 Route 4 e 1.340 n26_adj_3237 LUT4 --- 0.493 A to Z i2_4_lut_adj_879 Route 7 e 1.502 bcd_code_24__N_371 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4079_3_lut_4_lut Route 7 e 1.502 \bin_to_bcd_uut/n8128 LUT4 --- 0.493 B to Z \bin_to_bcd_uut/i4836_3_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_398 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4004_3_lut_rep_596_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60811 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i4892_3_lut_4_lut Route 9 e 1.574 \bin_to_bcd_uut/bcd_code_24__N_425 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4036_3_lut_rep_585_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60800 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i4992_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_463 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4039_3_lut_rep_573_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60788 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5048_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_499 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4042_3_lut_rep_557_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60772 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5132_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_541 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4189_2_lut_rep_521_4_lut_4_lut Route 4 e 1.340 \bin_to_bcd_uut/n60736 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5342_3_lut_4_lut_3_lut_4_lut Route 5 e 1.405 \bin_to_bcd_uut/bcd_code_24__N_527 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i5473_2_lut_rep_497_3_lut Route 5 e 1.405 \bin_to_bcd_uut/n60712 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i4055_3_lut_rep_489_4_lut Route 2 e 1.141 \bin_to_bcd_uut/n60704 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5468_3_lut_4_lut Route 9 e 1.574 \bin_to_bcd_uut/bcd_code_24__N_572 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4059_3_lut_rep_470_4_lut Route 2 e 1.141 \bin_to_bcd_uut/n60685 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5580_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_623 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4064_3_lut_rep_453_4_lut Route 2 e 1.141 \bin_to_bcd_uut/n60668 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5692_3_lut_4_lut Route 9 e 1.574 \bin_to_bcd_uut/bcd_code_24__N_674 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4068_3_lut_rep_438_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60653 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5804_3_lut_4_lut Route 8 e 1.540 \bin_to_bcd_uut/bcd_code_24__N_725 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4072_3_lut_rep_425_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60640 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5909_3_lut_4_lut Route 6 e 1.457 \bin_to_bcd_uut/bcd_code_24__N_767 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4074_3_lut_rep_413_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60628 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5965_3_lut_rep_407_4_lut Route 1 e 0.941 n60622 LUT4 --- 0.493 B to Z \control_module_uut/mux_263_i7_4_lut Route 1 e 0.941 \control_module_uut/tx_data_out_7__N_2749[6] -------- 79.361 (30.7% logic, 69.3% route), 52 logic levels. Error: The following path violates requirements by 74.521ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3AX CK \DS18B20Z_uut/data_out_i0_i15 (from clk_c +) Destination: FD1P3AX D \control_module_uut/tx_data_out_i0_i6 (to clk_c +) Delay: 79.361ns (30.7% logic, 69.3% route), 52 logic levels. Constraint Details: 79.361ns data_path \DS18B20Z_uut/data_out_i0_i15 to \control_module_uut/tx_data_out_i0_i6 violates 5.000ns delay constraint less 0.160ns L_S requirement (totaling 4.840ns) by 74.521ns Path Details: \DS18B20Z_uut/data_out_i0_i15 to \control_module_uut/tx_data_out_i0_i6 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \DS18B20Z_uut/data_out_i0_i15 (from clk_c) Route 1 e 0.941 data_out[15] LUT4 --- 0.493 B to Z i2_3_lut_adj_878 Route 7 e 1.502 n8 LUT4 --- 0.493 C to Z i2_3_lut Route 38 e 2.049 temperature_flag_N_23 LUT4 --- 0.493 C to Z temperature_code_10__I_0_10_i5_3_lut Route 2 e 1.141 temperature_code[4] A1_TO_FCO --- 0.827 A[2] to COUT add_6777_1 Route 1 e 0.020 n54690 FCI_TO_FCO --- 0.157 CIN to COUT add_6777_3 Route 1 e 0.020 n54691 FCI_TO_FCO --- 0.157 CIN to COUT add_6777_5 Route 1 e 0.020 n54692 FCI_TO_F --- 0.598 CIN to S[2] add_6777_7 Route 1 e 0.020 n12045 A1_TO_FCO --- 0.827 A[2] to COUT add_6799_5 Route 1 e 0.020 n54712 FCI_TO_FCO --- 0.157 CIN to COUT add_6799_7 Route 1 e 0.020 n54713 FCI_TO_FCO --- 0.157 CIN to COUT add_6799_9 Route 1 e 0.020 n54714 FCI_TO_FCO --- 0.157 CIN to COUT add_6799_11 Route 1 e 0.020 n54715 FCI_TO_F --- 0.598 CIN to S[2] add_6799_13 Route 1 e 0.020 n12096 A1_TO_FCO --- 0.827 A[2] to COUT add_6798_9 Route 1 e 0.020 n54708 FCI_TO_FCO --- 0.157 CIN to COUT add_6798_11 Route 1 e 0.020 n54709 FCI_TO_F --- 0.598 CIN to S[2] add_6798_cout Route 14 e 2.153 bin_code[20] LUT4 --- 0.493 D to Z \bin_to_bcd_uut/bin_code[17]_bdd_3_lut_47414_4_lut_4_lut Route 1 e 0.020 \bin_to_bcd_uut/n59905 MUXL5 --- 0.233 ALUT to Z \bin_to_bcd_uut/i47415 Route 10 e 1.604 n8116 LUT4 --- 0.493 C to Z i2_4_lut Route 8 e 1.540 bcd_code_24__N_344 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4093_3_lut_4_lut Route 6 e 1.457 \bin_to_bcd_uut/n8120 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4724_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_362 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4766_3_lut_rep_622_4_lut_3_lut_4_lut Route 6 e 1.457 n60837 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i1_2_lut_rep_618_3_lut_4_lut_4_lut Route 1 e 0.941 \bin_to_bcd_uut/n60833 LUT4 --- 0.493 A to Z \bin_to_bcd_uut/bcd_code_24__N_328[3]_bdd_4_lut_47529 Route 1 e 0.020 \bin_to_bcd_uut/n59873 MUXL5 --- 0.233 ALUT to Z \bin_to_bcd_uut/i47400 Route 4 e 1.340 n26_adj_3237 LUT4 --- 0.493 A to Z i2_4_lut_adj_879 Route 7 e 1.502 bcd_code_24__N_371 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4079_3_lut_4_lut Route 7 e 1.502 \bin_to_bcd_uut/n8128 LUT4 --- 0.493 B to Z \bin_to_bcd_uut/i4836_3_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_398 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4004_3_lut_rep_596_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60811 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i4892_3_lut_4_lut Route 9 e 1.574 \bin_to_bcd_uut/bcd_code_24__N_425 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4036_3_lut_rep_585_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60800 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i4992_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_463 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4039_3_lut_rep_573_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60788 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5048_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_499 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4042_3_lut_rep_557_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60772 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5132_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_541 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4189_2_lut_rep_521_4_lut_4_lut Route 4 e 1.340 \bin_to_bcd_uut/n60736 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5342_3_lut_4_lut_3_lut_4_lut Route 5 e 1.405 \bin_to_bcd_uut/bcd_code_24__N_527 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i5473_2_lut_rep_497_3_lut Route 5 e 1.405 \bin_to_bcd_uut/n60712 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i4055_3_lut_rep_489_4_lut Route 2 e 1.141 \bin_to_bcd_uut/n60704 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5468_3_lut_4_lut Route 9 e 1.574 \bin_to_bcd_uut/bcd_code_24__N_572 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4059_3_lut_rep_470_4_lut Route 2 e 1.141 \bin_to_bcd_uut/n60685 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5580_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_623 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4064_3_lut_rep_453_4_lut Route 2 e 1.141 \bin_to_bcd_uut/n60668 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5692_3_lut_4_lut Route 9 e 1.574 \bin_to_bcd_uut/bcd_code_24__N_674 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4068_3_lut_rep_438_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60653 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5804_3_lut_4_lut Route 8 e 1.540 \bin_to_bcd_uut/bcd_code_24__N_725 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4072_3_lut_rep_425_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60640 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5909_3_lut_4_lut Route 6 e 1.457 \bin_to_bcd_uut/bcd_code_24__N_767 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4074_3_lut_rep_413_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n60628 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5965_3_lut_rep_407_4_lut Route 1 e 0.941 n60622 LUT4 --- 0.493 B to Z \control_module_uut/mux_263_i7_4_lut Route 1 e 0.941 \control_module_uut/tx_data_out_7__N_2749[6] -------- 79.361 (30.7% logic, 69.3% route), 52 logic levels. Warning: 79.521 ns is the maximum delay for this constraint. Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk1 [get_nets clk_1mhz] | -| -| 0 | | | create_clock -period 5.000000 -name | | | clk0 [get_nets clk_c] | 5.000 ns| 79.521 ns| 52 * | | | -------------------------------------------------------------------------------- 1 constraints not met. -------------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total -------------------------------------------------------------------------------- \bin_to_bcd_uut/bcd_code_24__N_362 | 10| 4096| 99.00% | | | \bin_to_bcd_uut/bcd_code_24__N_674 | 9| 4096| 99.00% | | | \bin_to_bcd_uut/bcd_code_24__N_725 | 8| 4096| 99.00% | | | \bin_to_bcd_uut/n8120 | 6| 4096| 99.00% | | | \bin_to_bcd_uut/n60628 | 3| 4096| 99.00% | | | \bin_to_bcd_uut/n60640 | 3| 4096| 99.00% | | | \bin_to_bcd_uut/n60653 | 3| 4096| 99.00% | | | \bin_to_bcd_uut/n60668 | 2| 4096| 99.00% | | | \control_module_uut/tx_data_out_7__N_274| | | 9[6] | 1| 4096| 99.00% | | | bcd_code_24__N_344 | 8| 4096| 99.00% | | | bin_code[20] | 14| 4096| 99.00% | | | n8 | 7| 4096| 99.00% | | | n8116 | 10| 4096| 99.00% | | | n54709 | 1| 4096| 99.00% | | | n60622 | 1| 4096| 99.00% | | | temperature_flag_N_23 | 38| 4096| 99.00% | | | \bin_to_bcd_uut/bcd_code_24__N_527 | 5| 3832| 93.55% | | | \bin_to_bcd_uut/bcd_code_24__N_541 | 10| 3832| 93.55% | | | \bin_to_bcd_uut/bcd_code_24__N_572 | 9| 3832| 93.55% | | | \bin_to_bcd_uut/bcd_code_24__N_623 | 10| 3832| 93.55% | | | \bin_to_bcd_uut/n60685 | 2| 3832| 93.55% | | | \bin_to_bcd_uut/n60704 | 2| 3832| 93.55% | | | \bin_to_bcd_uut/n60712 | 5| 3832| 93.55% | | | \bin_to_bcd_uut/n60772 | 3| 3832| 93.55% | | | n54690 | 1| 3688| 90.04% | | | temperature_code[4] | 2| 3688| 90.04% | | | \bin_to_bcd_uut/bcd_code_24__N_499 | 10| 3568| 87.11% | | | \bin_to_bcd_uut/n60736 | 4| 3568| 87.11% | | | \bin_to_bcd_uut/n60788 | 3| 3568| 87.11% | | | n54708 | 1| 3512| 85.74% | | | n54691 | 1| 3245| 79.22% | | | \bin_to_bcd_uut/bcd_code_24__N_463 | 10| 3040| 74.22% | | | \bin_to_bcd_uut/n60800 | 3| 3040| 74.22% | | | \bin_to_bcd_uut/bcd_code_24__N_425 | 9| 2724| 66.50% | | | \bin_to_bcd_uut/bcd_code_24__N_767 | 6| 2724| 66.50% | | | \bin_to_bcd_uut/n60811 | 3| 2724| 66.50% | | | n54713 | 1| 2590| 63.23% | | | n54712 | 1| 2455| 59.94% | | | n54707 | 1| 2386| 58.25% | | | n54714 | 1| 2340| 57.13% | | | n54692 | 1| 2282| 55.71% | | | \bin_to_bcd_uut/bcd_code_24__N_398 | 10| 2196| 53.61% | | | \bin_to_bcd_uut/n8128 | 7| 2196| 53.61% | | | \bin_to_bcd_uut/n59873 | 1| 2196| 53.61% | | | \bin_to_bcd_uut/n60833 | 1| 2196| 53.61% | | | n26_adj_3237 | 4| 2196| 53.61% | | | n60837 | 6| 2196| 53.61% | | | \bin_to_bcd_uut/n59905 | 1| 2065| 50.42% | | | \bin_to_bcd_uut/n59906 | 1| 2031| 49.58% | | | \bin_to_bcd_uut/bcd_code_24__N_380 | 11| 1900| 46.39% | | | \bin_to_bcd_uut/bcd_code_24__N_407 | 9| 1900| 46.39% | | | \bin_to_bcd_uut/n60834 | 3| 1900| 46.39% | | | \bin_to_bcd_uut/n60844 | 3| 1900| 46.39% | | | n54711 | 1| 1760| 42.97% | | | n54715 | 1| 1710| 41.75% | | | bcd_code_24__N_371 | 7| 1668| 40.72% | | | n54706 | 1| 1457| 35.57% | | | n54693 | 1| 1422| 34.72% | | | data_out[15] | 1| 1382| 33.74% | | | \bin_to_bcd_uut/bcd_code_24__N_434 | 9| 1372| 33.50% | | | \bin_to_bcd_uut/n60633 | 5| 1372| 33.50% | | | \bin_to_bcd_uut/n60827 | 3| 1372| 33.50% | | | data_out[13] | 1| 1358| 33.15% | | | data_out[11] | 1| 1356| 33.11% | | | \bin_to_bcd_uut/bcd_code_24__N_472 | 9| 1056| 25.78% | | | \bin_to_bcd_uut/n60821 | 3| 1056| 25.78% | | | n12047 | 1| 909| 22.19% | | | n12045 | 1| 818| 19.97% | | | n12049 | 1| 791| 19.31% | | | n54710 | 1| 791| 19.31% | | | n54694 | 1| 755| 18.43% | | | n54705 | 1| 721| 17.60% | | | n12043 | 1| 637| 15.55% | | | n12113 | 1| 584| 14.26% | | | n54716 | 1| 584| 14.26% | | | n12096 | 1| 567| 13.84% | | | n12095 | 1| 559| 13.65% | | | \bin_to_bcd_uut/bcd_code_24__N_373 | 5| 528| 12.89% | | | \bin_to_bcd_uut/bcd_code_24__N_402 | 5| 528| 12.89% | | | \bin_to_bcd_uut/bcd_code_24__N_467 | 5| 528| 12.89% | | | \bin_to_bcd_uut/bcd_code_24__N_503 | 5| 528| 12.89% | | | \bin_to_bcd_uut/bcd_code_24__N_508 | 9| 528| 12.89% | | | \bin_to_bcd_uut/n60780 | 5| 528| 12.89% | | | \bin_to_bcd_uut/n60794 | 5| 528| 12.89% | | | \bin_to_bcd_uut/n60810 | 3| 528| 12.89% | | | \bin_to_bcd_uut/n60816 | 5| 528| 12.89% | | | n12098 | 1| 467| 11.40% | | | n12097 | 1| 462| 11.28% | | | n12041 | 1| 456| 11.13% | | | -------------------------------------------------------------------------------- Timing summary: --------------- Timing errors: 4096 Score: 304726236 Constraints cover >4294967295 paths, 3772 nets, and 11877 connections (98.2% coverage) Peak memory: 197627904 bytes, TRCE: 5550080 bytes, DLYMAN: 0 bytes CPU_TIME_REPORT: 0 secs