Setting log file to 'C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/hdla_gen_hierarchy.html'. Starting: parse design source files (VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v (VERI-1482) Analyzing Verilog file C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/OLED12832.v (VERI-1482) Analyzing Verilog file C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/DS18B20Z.v (VERI-1482) Analyzing Verilog file C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/bin_to_bcd.v (VERI-1482) Analyzing Verilog file C:/Users/CROFY/Documents/Diamond/Project/step_project01/control_module.v (VERI-1482) Analyzing Verilog file C:/Users/CROFY/Documents/Diamond/Project/step_project01/step_project01.v (VERI-1482) Analyzing Verilog file C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/Uart_Tx.v (VERI-1482) Analyzing Verilog file C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/Uart_Rx.v (VERI-1482) Analyzing Verilog file C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/Baud.v (VERI-1482) Analyzing Verilog file C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/Uart_Bus.v (VERI-1482) Analyzing Verilog file C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/PWM.v (VERI-1482) Analyzing Verilog file C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/key_debounce.v INFO - C:/Users/CROFY/Documents/Diamond/Project/step_project01/step_project01.v(1,8-1,22) (VERI-1018) compiling module step_project01 INFO - C:/Users/CROFY/Documents/Diamond/Project/step_project01/step_project01.v(1,1-143,10) (VERI-9000) elaborating module 'step_project01' INFO - C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/DS18B20Z.v(18,1-266,10) (VERI-9000) elaborating module 'DS18B20Z_uniq_1' INFO - C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/bin_to_bcd.v(18,1-47,10) (VERI-9000) elaborating module 'bin_to_bcd_uniq_1' INFO - C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/OLED12832.v(18,1-304,10) (VERI-9000) elaborating module 'OLED12832_uniq_1' INFO - C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/Uart_Bus.v(18,1-96,10) (VERI-9000) elaborating module 'Uart_Bus_uniq_1' INFO - C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/PWM.v(18,1-43,10) (VERI-9000) elaborating module 'PWM_uniq_1' INFO - C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/key_debounce.v(1,1-60,10) (VERI-9000) elaborating module 'key_debounce_uniq_1' INFO - C:/Users/CROFY/Documents/Diamond/Project/step_project01/control_module.v(1,1-428,10) (VERI-9000) elaborating module 'control_module_uniq_1' INFO - C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/Baud.v(18,1-50,10) (VERI-9000) elaborating module 'Baud_uniq_1' INFO - C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/Baud.v(18,1-50,10) (VERI-9000) elaborating module 'Baud_uniq_2' INFO - C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/Uart_Rx.v(18,1-85,10) (VERI-9000) elaborating module 'Uart_Rx_uniq_1' INFO - C:/Users/CROFY/Documents/Diamond/Project/step_project01/impl1/source/Uart_Tx.v(18,1-61,10) (VERI-9000) elaborating module 'Uart_Tx_uniq_1' Done: design load finished with (0) errors, and (0) warnings