Lattice Synthesis Timing Report -------------------------------------------------------------------------------- Lattice Synthesis Timing Report, Version Sun Feb 14 14:55:28 2021 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design: OLED12832 Constraint file: Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 5.000000 -name clk0 [get_nets clk_c] 3973 items scored, 3973 timing errors detected. -------------------------------------------------------------------------------- Error: The following path violates requirements by 13.841ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3AX CK num_2017__i0 (from clk_c +) Destination: FD1S3AX D char_reg_i7 (to clk_c +) Delay: 18.681ns (31.3% logic, 68.7% route), 13 logic levels. Constraint Details: 18.681ns data_path num_2017__i0 to char_reg_i7 violates 5.000ns delay constraint less 0.160ns L_S requirement (totaling 4.840ns) by 13.841ns Path Details: num_2017__i0 to char_reg_i7 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q num_2017__i0 (from clk_c) Route 20 e 1.885 num[0] LUT4 --- 0.493 C to Z char[114]_bdd_3_lut_11319 Route 1 e 0.020 n16378 MUXL5 --- 0.233 BLUT to Z i11084 Route 1 e 0.941 n16379 LUT4 --- 0.493 A to Z n16379_bdd_4_lut Route 4 e 1.340 n16966 LUT4 --- 0.493 B to Z i1_2_lut_rep_246 Route 37 e 2.048 n16986 LUT4 --- 0.493 A to Z n644_bdd_4_lut Route 1 e 0.941 n16770 LUT4 --- 0.493 D to Z n3443_bdd_2_lut_11316_3_lut_4_lut Route 1 e 0.941 n16771 LUT4 --- 0.493 A to Z i1_4_lut_adj_10 Route 1 e 0.941 n15808 LUT4 --- 0.493 C to Z i1_4_lut_4_lut_adj_220 Route 1 e 0.941 n61 LUT4 --- 0.493 C to Z i1_4_lut_adj_9 Route 1 e 0.941 n64 LUT4 --- 0.493 C to Z i1_4_lut_4_lut_adj_207 Route 1 e 0.020 n12_adj_150 MUXL5 --- 0.233 ALUT to Z i47 Route 1 e 0.941 n24_adj_148 LUT4 --- 0.493 A to Z i1_4_lut_adj_63 Route 1 e 0.941 char_reg_7__N_203[7] -------- 18.681 (31.3% logic, 68.7% route), 13 logic levels. Error: The following path violates requirements by 13.841ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3AX CK num_2017__i0 (from clk_c +) Destination: FD1S3AX D char_reg_i7 (to clk_c +) Delay: 18.681ns (31.3% logic, 68.7% route), 13 logic levels. Constraint Details: 18.681ns data_path num_2017__i0 to char_reg_i7 violates 5.000ns delay constraint less 0.160ns L_S requirement (totaling 4.840ns) by 13.841ns Path Details: num_2017__i0 to char_reg_i7 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q num_2017__i0 (from clk_c) Route 20 e 1.885 num[0] LUT4 --- 0.493 B to Z char[114]_bdd_3_lut_11083 Route 1 e 0.020 n16377 MUXL5 --- 0.233 ALUT to Z i11084 Route 1 e 0.941 n16379 LUT4 --- 0.493 A to Z n16379_bdd_4_lut Route 4 e 1.340 n16966 LUT4 --- 0.493 B to Z i1_2_lut_rep_246 Route 37 e 2.048 n16986 LUT4 --- 0.493 A to Z n644_bdd_4_lut Route 1 e 0.941 n16770 LUT4 --- 0.493 D to Z n3443_bdd_2_lut_11316_3_lut_4_lut Route 1 e 0.941 n16771 LUT4 --- 0.493 A to Z i1_4_lut_adj_10 Route 1 e 0.941 n15808 LUT4 --- 0.493 C to Z i1_4_lut_4_lut_adj_220 Route 1 e 0.941 n61 LUT4 --- 0.493 C to Z i1_4_lut_adj_9 Route 1 e 0.941 n64 LUT4 --- 0.493 C to Z i1_4_lut_4_lut_adj_207 Route 1 e 0.020 n12_adj_150 MUXL5 --- 0.233 ALUT to Z i47 Route 1 e 0.941 n24_adj_148 LUT4 --- 0.493 A to Z i1_4_lut_adj_63 Route 1 e 0.941 char_reg_7__N_203[7] -------- 18.681 (31.3% logic, 68.7% route), 13 logic levels. Error: The following path violates requirements by 13.588ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3AX CK num_2017__i0 (from clk_c +) Destination: FD1S3AX D char_reg_i7 (to clk_c +) Delay: 18.428ns (30.4% logic, 69.6% route), 12 logic levels. Constraint Details: 18.428ns data_path num_2017__i0 to char_reg_i7 violates 5.000ns delay constraint less 0.160ns L_S requirement (totaling 4.840ns) by 13.588ns Path Details: num_2017__i0 to char_reg_i7 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q num_2017__i0 (from clk_c) Route 20 e 1.885 num[0] LUT4 --- 0.493 B to Z i3_3_lut_3_lut_4_lut Route 1 e 0.941 n4_adj_153 LUT4 --- 0.493 C to Z n16379_bdd_4_lut Route 4 e 1.340 n16966 LUT4 --- 0.493 B to Z i1_2_lut_rep_246 Route 37 e 2.048 n16986 LUT4 --- 0.493 A to Z n644_bdd_4_lut Route 1 e 0.941 n16770 LUT4 --- 0.493 D to Z n3443_bdd_2_lut_11316_3_lut_4_lut Route 1 e 0.941 n16771 LUT4 --- 0.493 A to Z i1_4_lut_adj_10 Route 1 e 0.941 n15808 LUT4 --- 0.493 C to Z i1_4_lut_4_lut_adj_220 Route 1 e 0.941 n61 LUT4 --- 0.493 C to Z i1_4_lut_adj_9 Route 1 e 0.941 n64 LUT4 --- 0.493 C to Z i1_4_lut_4_lut_adj_207 Route 1 e 0.020 n12_adj_150 MUXL5 --- 0.233 ALUT to Z i47 Route 1 e 0.941 n24_adj_148 LUT4 --- 0.493 A to Z i1_4_lut_adj_63 Route 1 e 0.941 char_reg_7__N_203[7] -------- 18.428 (30.4% logic, 69.6% route), 12 logic levels. Warning: 18.841 ns is the maximum delay for this constraint. Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk0 [get_nets clk_c] | 5.000 ns| 18.841 ns| 13 * | | | -------------------------------------------------------------------------------- 1 constraints not met. -------------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total -------------------------------------------------------------------------------- n16039 | 4| 1205| 30.33% | | | n641 | 36| 1143| 28.77% | | | num[0] | 20| 705| 17.74% | | | n16037 | 1| 584| 14.70% | | | n16038 | 1| 584| 14.70% | | | n16966 | 4| 557| 14.02% | | | char_reg_7__N_203[7] | 1| 550| 13.84% | | | n24_adj_148 | 1| 550| 13.84% | | | n12_adj_150 | 1| 542| 13.64% | | | n64 | 1| 542| 13.64% | | | num[3] | 12| 536| 13.49% | | | n16986 | 37| 524| 13.19% | | | num[2] | 12| 524| 13.19% | | | char_reg_7__N_203[1] | 1| 508| 12.79% | | | n642 | 39| 508| 12.79% | | | n16838 | 1| 508| 12.79% | | | char_reg_7__N_203[2] | 1| 507| 12.76% | | | n24_adj_135 | 1| 507| 12.76% | | | char_reg_7__N_203[0] | 1| 503| 12.66% | | | n24_adj_132 | 1| 503| 12.66% | | | char_reg_7__N_203[4] | 1| 500| 12.58% | | | n16824 | 1| 500| 12.58% | | | n16825 | 1| 500| 12.58% | | | n16826 | 1| 500| 12.58% | | | n16827 | 1| 500| 12.58% | | | n16835 | 1| 500| 12.58% | | | n16836 | 1| 500| 12.58% | | | n16837 | 1| 500| 12.58% | | | num[1] | 15| 500| 12.58% | | | n12 | 1| 499| 12.56% | | | n12_adj_137 | 1| 499| 12.56% | | | n64_adj_60 | 1| 499| 12.56% | | | n16746 | 1| 499| 12.56% | | | n16747 | 1| 499| 12.56% | | | n17640 | 1| 499| 12.56% | | | n9801 | 4| 486| 12.23% | | | char_reg_7__N_203[3] | 1| 484| 12.18% | | | n24_adj_138 | 1| 484| 12.18% | | | n12_adj_140 | 1| 480| 12.08% | | | n64_adj_62 | 1| 480| 12.08% | | | n16426 | 1| 480| 12.08% | | | char_reg_7__N_203[6] | 1| 475| 11.96% | | | n24_adj_145 | 1| 475| 11.96% | | | n12_adj_147 | 1| 467| 11.75% | | | n17428 | 1| 467| 11.75% | | | n17429 | 1| 467| 11.75% | | | n61 | 1| 463| 11.65% | | | n640 | 39| 449| 11.30% | | | n17641 | 39| 442| 11.13% | | | n16967 | 2| 430| 10.82% | | | n646 | 40| 414| 10.42% | | | char_reg_7__N_203[5] | 1| 400| 10.07% | | | n12_adj_144 | 1| 400| 10.07% | | | n24_adj_142 | 1| 400| 10.07% | | | n64_adj_58 | 1| 400| 10.07% | | | n16382 | 1| 400| 10.07% | | | n16423 | 1| 400| 10.07% | | | n16424 | 1| 400| 10.07% | | | n16558 | 1| 400| 10.07% | | | n16743 | 1| 400| 10.07% | | | n16744 | 1| 400| 10.07% | | | n16822 | 1| 400| 10.07% | | | n16833 | 1| 400| 10.07% | | | n17636 | 1| 400| 10.07% | | | n17637 | 1| 400| 10.07% | | | -------------------------------------------------------------------------------- Timing summary: --------------- Timing errors: 3973 Score: 44231970 Constraints cover 11794 paths, 921 nets, and 3165 connections (99.8% coverage) Peak memory: 99176448 bytes, TRCE: 5357568 bytes, DLYMAN: 0 bytes CPU_TIME_REPORT: 0 secs