Project Settings
Project Name proj_1 Device Name impl1: Lattice MachXO2 : LCMXO2_4000HC
Implementation Name impl1 Top Module step_project01
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 1000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 121 217 0 - 00m:04s - 2021/2/15
12:42:43
(premap)Complete 9 16 0 0m:00s 0m:00s 145MB 2021/2/15
12:42:45
(fpga_mapper)Complete 38 37 0 04m:59s 04m:59s 245MB 2021/2/15
12:47:45
Multi-srs Generator Complete2021/2/15
12:42:44

Area Summary
Register bits 349 I/O cells 10
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
ORCA LUTs (total_luts) 1321

Timing Summary
Clock NameReq FreqEst FreqSlack
DS18B20Z|clk_1mhz_derived_clock200.0 MHz19.7 MHz-45.818
step_project01|clk200.0 MHz19.7 MHz-7.920
System200.0 MHzNANA