Place & Route TRACE Report

Loading design for application trce from file step_project01_impl1.ncd.
Design name: step_project01
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-4000HC
Package:     CSBGA132
Performance: 4
Loading device for application trce from file 'xo2c4000.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.11.0.396.4
Thu Feb 18 17:28:22 2021

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o step_project01_impl1.twr -gui -msgset C:/Users/CROFY/Documents/Diamond/Project/step_project01/promote.xml step_project01_impl1.ncd step_project01_impl1.prf 
Design file:     step_project01_impl1.ncd
Preference file: step_project01_impl1.prf
Device,speed:    LCMXO2-4000HC,4
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY NET "clk_c" 23.368000 MHz (4096 errors)
  • 4096 items scored, 4096 timing errors detected. Warning: 0.468MHz is the maximum frequency for this preference.
  • FREQUENCY NET "clk_c_generated_8" 399.840000 MHz (1 errors)
  • 4 items scored, 1 timing error detected. Warning: 215.564MHz is the maximum frequency for this preference. 28 potential circuit loops found in timing analysis. Report Type: based on TRACE automatically generated preferences BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "clk_c" 23.368000 MHz ; 4096 items scored, 4096 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 13.564ns (weighted slack = -2095.516ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/i23195 (from clk_c_generated_8 +) Destination: FF Data in OLED12832_uut/char_i8 (to clk_c +) Delay: 6.050ns (48.4% logic, 51.6% route), 6 logic levels. Constraint Details: 6.050ns physical path delay control_module_uut/SLICE_608 to OLED12832_uut/SLICE_275 exceeds (delay constraint based on source clock period of 2.501ns and destination clock period of 42.794ns) 0.277ns delay constraint less 7.625ns skew and 0.166ns DIN_SET requirement (totaling -7.514ns) by 13.564ns Physical Path Details: Data path control_module_uut/SLICE_608 to OLED12832_uut/SLICE_275: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R14C16B.CLK to R14C16B.Q0 control_module_uut/SLICE_608 (from clk_c_generated_8) ROUTE 2 0.630 R14C16B.Q0 to R14C15D.D1 n35352 CTOF_DEL --- 0.495 R14C15D.D1 to R14C15D.F1 OLED12832_uut/SLICE_1184 ROUTE 2 0.445 R14C15D.F1 to R14C15D.C0 n61061 CTOF_DEL --- 0.495 R14C15D.C0 to R14C15D.F0 OLED12832_uut/SLICE_1184 ROUTE 1 0.645 R14C15D.F0 to R14C16D.D1 OLED12832_uut/n1_adj_3158 CTOF_DEL --- 0.495 R14C16D.D1 to R14C16D.F1 OLED12832_uut/SLICE_1011 ROUTE 1 0.436 R14C16D.F1 to R14C16D.C0 OLED12832_uut/char_167_N_1235_8 CTOF_DEL --- 0.495 R14C16D.C0 to R14C16D.F0 OLED12832_uut/SLICE_1011 ROUTE 1 0.967 R14C16D.F0 to R14C16A.A1 OLED12832_uut/n16_adj_3157 CTOF_DEL --- 0.495 R14C16A.A1 to R14C16A.F1 OLED12832_uut/SLICE_275 ROUTE 1 0.000 R14C16A.F1 to R14C16A.DI1 OLED12832_uut/char_167_N_904_8 (to clk_c) -------- 6.050 (48.4% logic, 51.6% route), 6 logic levels. Clock Skew Details: Source Clock Path clk to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 531 3.044 C1.PADDI to R14C15C.CLK clk_c REG_DEL --- 0.452 R14C15C.CLK to R14C15C.Q0 SLICE_1207 ROUTE 68 5.643 R14C15C.Q0 to R15C16C.A0 n62436 CTOF_DEL --- 0.495 R15C16C.A0 to R15C16C.F0 SLICE_1525 ROUTE 2 1.035 R15C16C.F0 to R14C16B.CLK clk_c_generated_8 -------- 11.801 (17.6% logic, 82.4% route), 3 logic levels. Destination Clock Path clk to OLED12832_uut/SLICE_275: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 531 3.044 C1.PADDI to R14C16A.CLK clk_c -------- 4.176 (27.1% logic, 72.9% route), 1 logic levels. Error: The following path exceeds requirements by 11.571ns (weighted slack = -1787.615ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/i23195 (from clk_c_generated_8 +) Destination: FF Data in control_module_uut/temp_out_i8_23196_23197_reset (to clk_c +) Delay: 3.490ns (41.3% logic, 58.7% route), 3 logic levels. Constraint Details: 3.490ns physical path delay control_module_uut/SLICE_608 to SLICE_1506 exceeds (delay constraint based on source clock period of 2.501ns and destination clock period of 42.794ns) 0.277ns delay constraint less 7.625ns skew and 0.733ns LSRREC_SET requirement (totaling -8.081ns) by 11.571ns Physical Path Details: Data path control_module_uut/SLICE_608 to SLICE_1506: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R14C16B.CLK to R14C16B.Q0 control_module_uut/SLICE_608 (from clk_c_generated_8) ROUTE 2 0.630 R14C16B.Q0 to R14C15D.D1 n35352 CTOF_DEL --- 0.495 R14C15D.D1 to R14C15D.F1 OLED12832_uut/SLICE_1184 ROUTE 2 0.756 R14C15D.F1 to R14C15A.C1 n61061 CTOF_DEL --- 0.495 R14C15A.C1 to R14C15A.F1 control_module_uut/SLICE_1488 ROUTE 2 0.662 R14C15A.F1 to R14C15B.LSR control_module_uut/temp_out_31__N_1883 (to clk_c) -------- 3.490 (41.3% logic, 58.7% route), 3 logic levels. Clock Skew Details: Source Clock Path clk to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 531 3.044 C1.PADDI to R14C15C.CLK clk_c REG_DEL --- 0.452 R14C15C.CLK to R14C15C.Q0 SLICE_1207 ROUTE 68 5.643 R14C15C.Q0 to R15C16C.A0 n62436 CTOF_DEL --- 0.495 R15C16C.A0 to R15C16C.F0 SLICE_1525 ROUTE 2 1.035 R15C16C.F0 to R14C16B.CLK clk_c_generated_8 -------- 11.801 (17.6% logic, 82.4% route), 3 logic levels. Destination Clock Path clk to SLICE_1506: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 531 3.044 C1.PADDI to R14C15B.CLK clk_c -------- 4.176 (27.1% logic, 72.9% route), 1 logic levels. Error: The following path exceeds requirements by 10.320ns (weighted slack = -1594.347ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/i23195 (from clk_c_generated_8 +) Destination: FF Data in control_module_uut/temp_out_i8_23196_23197_set (to clk_c +) Delay: 2.239ns (42.3% logic, 57.7% route), 2 logic levels. Constraint Details: 2.239ns physical path delay control_module_uut/SLICE_608 to SLICE_609 exceeds (delay constraint based on source clock period of 2.501ns and destination clock period of 42.794ns) 0.277ns delay constraint less 7.625ns skew and 0.733ns LSRREC_SET requirement (totaling -8.081ns) by 10.320ns Physical Path Details: Data path control_module_uut/SLICE_608 to SLICE_609: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R14C16B.CLK to R14C16B.Q0 control_module_uut/SLICE_608 (from clk_c_generated_8) ROUTE 2 0.630 R14C16B.Q0 to R15C16C.D0 n35352 CTOF_DEL --- 0.495 R15C16C.D0 to R15C16C.F0 SLICE_1525 ROUTE 2 0.662 R15C16C.F0 to R15C16B.LSR clk_c_generated_8 (to clk_c) -------- 2.239 (42.3% logic, 57.7% route), 2 logic levels. Clock Skew Details: Source Clock Path clk to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 531 3.044 C1.PADDI to R14C15C.CLK clk_c REG_DEL --- 0.452 R14C15C.CLK to R14C15C.Q0 SLICE_1207 ROUTE 68 5.643 R14C15C.Q0 to R15C16C.A0 n62436 CTOF_DEL --- 0.495 R15C16C.A0 to R15C16C.F0 SLICE_1525 ROUTE 2 1.035 R15C16C.F0 to R14C16B.CLK clk_c_generated_8 -------- 11.801 (17.6% logic, 82.4% route), 3 logic levels. Destination Clock Path clk to SLICE_609: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 531 3.044 C1.PADDI to R15C16B.CLK clk_c -------- 4.176 (27.1% logic, 72.9% route), 1 logic levels. Error: The following path exceeds requirements by 37.200ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DS18B20Z_uut/data_out_i0_i0 (from clk_c +) Destination: FF Data in control_module_uut/temp_out_i18_23232_23233_reset (to clk_c +) Delay: 79.646ns (30.9% logic, 69.1% route), 50 logic levels. Constraint Details: 79.646ns physical path delay DS18B20Z_uut/SLICE_1537 to SLICE_1541 exceeds 42.794ns delay constraint less 0.000ns skew and 0.348ns M_SET requirement (totaling 42.446ns) by 37.200ns Physical Path Details: Data path DS18B20Z_uut/SLICE_1537 to SLICE_1541: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R12C25D.CLK to R12C25D.Q0 DS18B20Z_uut/SLICE_1537 (from clk_c) ROUTE 5 1.043 R12C25D.Q0 to R14C25A.B1 data_out_0 C1TOFCO_DE --- 0.889 R14C25A.B1 to R14C25A.FCO SLICE_178 ROUTE 1 0.000 R14C25A.FCO to R14C25B.FCI n54604 FCITOFCO_D --- 0.162 R14C25B.FCI to R14C25B.FCO SLICE_177 ROUTE 1 0.000 R14C25B.FCO to R14C25C.FCI n54605 FCITOFCO_D --- 0.162 R14C25C.FCI to R14C25C.FCO SLICE_0 ROUTE 1 0.000 R14C25C.FCO to R14C25D.FCI n54606 FCITOF0_DE --- 0.585 R14C25D.FCI to R14C25D.F0 SLICE_175 ROUTE 4 3.250 R14C25D.F0 to R13C26D.C1 temperature_code_10_N_1_5 CTOF_DEL --- 0.495 R13C26D.C1 to R13C26D.F1 SLICE_1510 ROUTE 2 1.804 R13C26D.F1 to R12C26B.A0 temperature_code_5 C0TOFCO_DE --- 1.023 R12C26B.A0 to R12C26B.FCO SLICE_28 ROUTE 1 0.000 R12C26B.FCO to R12C26C.FCI n54691 FCITOF0_DE --- 0.585 R12C26C.FCI to R12C26C.F0 SLICE_27 ROUTE 1 2.224 R12C26C.F0 to R10C26B.B1 n12047 C1TOFCO_DE --- 0.889 R10C26B.B1 to R10C26B.FCO SLICE_14 ROUTE 1 0.000 R10C26B.FCO to R10C26C.FCI n54711 FCITOFCO_D --- 0.162 R10C26C.FCI to R10C26C.FCO SLICE_13 ROUTE 1 0.000 R10C26C.FCO to R10C26D.FCI n54712 FCITOF0_DE --- 0.585 R10C26D.FCI to R10C26D.F0 SLICE_12 ROUTE 1 1.420 R10C26D.F0 to R10C28B.B0 n12102 C0TOFCO_DE --- 1.023 R10C28B.B0 to R10C28B.FCO SLICE_21 ROUTE 1 0.000 R10C28B.FCO to R10C28C.FCI n54705 FCITOFCO_D --- 0.162 R10C28C.FCI to R10C28C.FCO SLICE_20 ROUTE 1 0.000 R10C28C.FCO to R10C28D.FCI n54706 FCITOFCO_D --- 0.162 R10C28D.FCI to R10C28D.FCO SLICE_19 ROUTE 1 0.000 R10C28D.FCO to R10C29A.FCI n54707 FCITOFCO_D --- 0.162 R10C29A.FCI to R10C29A.FCO SLICE_18 ROUTE 1 0.000 R10C29A.FCO to R10C29B.FCI n54708 FCITOFCO_D --- 0.162 R10C29B.FCI to R10C29B.FCO SLICE_17 ROUTE 1 0.000 R10C29B.FCO to R10C29C.FCI n54709 FCITOF0_DE --- 0.585 R10C29C.FCI to R10C29C.F0 SLICE_16 ROUTE 15 0.726 R10C29C.F0 to R10C29D.B0 bin_code_20 CTOF_DEL --- 0.495 R10C29D.B0 to R10C29D.F0 bin_to_bcd_uut/SLICE_963 ROUTE 2 0.445 R10C29D.F0 to R10C29D.C1 bin_to_bcd_uut/n59905 CTOF_DEL --- 0.495 R10C29D.C1 to R10C29D.F1 bin_to_bcd_uut/SLICE_963 ROUTE 9 2.048 R10C29D.F1 to R16C27A.C0 n8116 CTOF_DEL --- 0.495 R16C27A.C0 to R16C27A.F0 SLICE_1064 ROUTE 9 1.332 R16C27A.F0 to R8C27B.C1 bcd_code_24__N_344 CTOF_DEL --- 0.495 R8C27B.C1 to R8C27B.F1 bin_to_bcd_uut/SLICE_1088 ROUTE 4 0.461 R8C27B.F1 to R8C27B.C0 bin_to_bcd_uut/n8120 CTOF_DEL --- 0.495 R8C27B.C0 to R8C27B.F0 bin_to_bcd_uut/SLICE_1088 ROUTE 4 2.339 R8C27B.F0 to R8C26C.D1 bin_to_bcd_uut/n60848 CTOF_DEL --- 0.495 R8C26C.D1 to R8C26C.F1 bin_to_bcd_uut/SLICE_1393 ROUTE 3 0.782 R8C26C.F1 to R9C26C.C1 bin_to_bcd_uut/n60844 CTOF_DEL --- 0.495 R9C26C.C1 to R9C26C.F1 bin_to_bcd_uut/SLICE_1385 ROUTE 11 1.082 R9C26C.F1 to R9C27C.B0 bin_to_bcd_uut/bcd_code_24__N_380 CTOF_DEL --- 0.495 R9C27C.B0 to R9C27C.F0 bin_to_bcd_uut/SLICE_1120 ROUTE 3 1.180 R9C27C.F0 to R9C26A.C1 bin_to_bcd_uut/n60834 CTOF_DEL --- 0.495 R9C26A.C1 to R9C26A.F1 bin_to_bcd_uut/SLICE_1386 ROUTE 9 1.433 R9C26A.F1 to R8C26D.A1 bin_to_bcd_uut/bcd_code_24__N_407 CTOF_DEL --- 0.495 R8C26D.A1 to R8C26D.F1 bin_to_bcd_uut/SLICE_1118 ROUTE 4 2.290 R8C26D.F1 to R7C26C.B1 bin_to_bcd_uut/n60825 CTOF_DEL --- 0.495 R7C26C.B1 to R7C26C.F1 bin_to_bcd_uut/SLICE_1380 ROUTE 3 1.002 R7C26C.F1 to R8C26A.A1 bin_to_bcd_uut/n60821 CTOF_DEL --- 0.495 R8C26A.A1 to R8C26A.F1 bin_to_bcd_uut/SLICE_1368 ROUTE 9 0.469 R8C26A.F1 to R8C26B.C0 bin_to_bcd_uut/bcd_code_24__N_472 CTOF_DEL --- 0.495 R8C26B.C0 to R8C26B.F0 bin_to_bcd_uut/SLICE_1115 ROUTE 5 2.050 R8C26B.F0 to R8C28A.B0 bin_to_bcd_uut/bcd_code_24__N_467 CTOF_DEL --- 0.495 R8C28A.B0 to R8C28A.F0 bin_to_bcd_uut/SLICE_1366 ROUTE 5 2.746 R8C28A.F0 to R17C28B.B1 bin_to_bcd_uut/n60794 CTOF_DEL --- 0.495 R17C28B.B1 to R17C28B.F1 bin_to_bcd_uut/SLICE_1349 ROUTE 5 1.040 R17C28B.F1 to R17C27C.B0 bin_to_bcd_uut/n60771 CTOF_DEL --- 0.495 R17C27C.B0 to R17C27C.F0 bin_to_bcd_uut/SLICE_1100 ROUTE 2 0.993 R17C27C.F0 to R17C29A.A0 bin_to_bcd_uut/n60765 CTOF_DEL --- 0.495 R17C29A.A0 to R17C29A.F0 bin_to_bcd_uut/SLICE_1103 ROUTE 9 1.574 R17C29A.F0 to R15C29D.C0 bin_to_bcd_uut/bcd_code_24__N_490 CTOF_DEL --- 0.495 R15C29D.C0 to R15C29D.F0 bin_to_bcd_uut/SLICE_1340 ROUTE 2 1.522 R15C29D.F0 to R9C30C.A0 bin_to_bcd_uut/n60743 CTOF_DEL --- 0.495 R9C30C.A0 to R9C30C.F0 bin_to_bcd_uut/SLICE_1341 ROUTE 4 2.389 R9C30C.F0 to R16C27C.A0 bin_to_bcd_uut/n60736 CTOF_DEL --- 0.495 R16C27C.A0 to R16C27C.F0 bin_to_bcd_uut/SLICE_1318 ROUTE 5 0.445 R16C27C.F0 to R16C27C.C1 bin_to_bcd_uut/bcd_code_24__N_527 CTOF_DEL --- 0.495 R16C27C.C1 to R16C27C.F1 bin_to_bcd_uut/SLICE_1318 ROUTE 5 1.476 R16C27C.F1 to R14C26D.B1 bin_to_bcd_uut/n60712 CTOF_DEL --- 0.495 R14C26D.B1 to R14C26D.F1 bin_to_bcd_uut/SLICE_1313 ROUTE 2 0.995 R14C26D.F1 to R15C26B.A1 bin_to_bcd_uut/n60704 CTOF_DEL --- 0.495 R15C26B.A1 to R15C26B.F1 bin_to_bcd_uut/SLICE_1089 ROUTE 9 0.477 R15C26B.F1 to R15C26C.C0 bin_to_bcd_uut/bcd_code_24__N_572 CTOF_DEL --- 0.495 R15C26C.C0 to R15C26C.F0 bin_to_bcd_uut/SLICE_1123 ROUTE 2 1.015 R15C26C.F0 to R14C26D.B0 bin_to_bcd_uut/n60685 CTOF_DEL --- 0.495 R14C26D.B0 to R14C26D.F0 bin_to_bcd_uut/SLICE_1313 ROUTE 10 2.416 R14C26D.F0 to R6C26A.A0 bin_to_bcd_uut/bcd_code_24__N_623 CTOF_DEL --- 0.495 R6C26A.A0 to R6C26A.F0 bin_to_bcd_uut/SLICE_1121 ROUTE 2 0.976 R6C26A.F0 to R6C26C.A1 bin_to_bcd_uut/n60668 CTOF_DEL --- 0.495 R6C26C.A1 to R6C26C.F1 bin_to_bcd_uut/SLICE_1352 ROUTE 9 4.056 R6C26C.F1 to R14C24B.A0 bin_to_bcd_uut/bcd_code_24__N_674 CTOF_DEL --- 0.495 R14C24B.A0 to R14C24B.F0 bin_to_bcd_uut/SLICE_1371 ROUTE 5 1.011 R14C24B.F0 to R15C24D.A0 bin_to_bcd_uut/bcd_code_24__N_669 CTOF_DEL --- 0.495 R15C24D.A0 to R15C24D.F0 bin_to_bcd_uut/SLICE_1320 ROUTE 4 0.718 R15C24D.F0 to R15C24B.B1 bin_to_bcd_uut/n60639 CTOF_DEL --- 0.495 R15C24B.B1 to R15C24B.F1 SLICE_417 ROUTE 3 0.987 R15C24B.F1 to R15C23D.A1 bin_to_bcd_uut/n60635 CTOF_DEL --- 0.495 R15C23D.A1 to R15C23D.F1 SLICE_414 ROUTE 6 0.787 R15C23D.F1 to R15C23B.C1 bin_to_bcd_uut/bcd_code_24__N_716 CTOF_DEL --- 0.495 R15C23B.C1 to R15C23B.F1 SLICE_401 ROUTE 3 1.040 R15C23B.F1 to R15C25C.B0 bin_to_bcd_uut/n60623 CTOF_DEL --- 0.495 R15C25C.B0 to R15C25C.F0 SLICE_404 ROUTE 2 1.023 R15C25C.F0 to R13C27C.M0 bcd_code_18 (to clk_c) -------- 79.646 (30.9% logic, 69.1% route), 50 logic levels. Clock Skew Details: Source Clock Path clk to DS18B20Z_uut/SLICE_1537: Name Fanout Delay (ns) Site Resource ROUTE 531 3.044 C1.PADDI to R12C25D.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_1541: Name Fanout Delay (ns) Site Resource ROUTE 531 3.044 C1.PADDI to R13C27C.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 37.200ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DS18B20Z_uut/data_out_i0_i0 (from clk_c +) Destination: FF Data in control_module_uut/temp_out_i18_23232_23233_reset (to clk_c +) Delay: 79.646ns (30.5% logic, 69.5% route), 48 logic levels. Constraint Details: 79.646ns physical path delay DS18B20Z_uut/SLICE_1537 to SLICE_1541 exceeds 42.794ns delay constraint less 0.000ns skew and 0.348ns M_SET requirement (totaling 42.446ns) by 37.200ns Physical Path Details: Data path DS18B20Z_uut/SLICE_1537 to SLICE_1541: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R12C25D.CLK to R12C25D.Q0 DS18B20Z_uut/SLICE_1537 (from clk_c) ROUTE 5 1.043 R12C25D.Q0 to R14C25A.B1 data_out_0 C1TOFCO_DE --- 0.889 R14C25A.B1 to R14C25A.FCO SLICE_178 ROUTE 1 0.000 R14C25A.FCO to R14C25B.FCI n54604 FCITOFCO_D --- 0.162 R14C25B.FCI to R14C25B.FCO SLICE_177 ROUTE 1 0.000 R14C25B.FCO to R14C25C.FCI n54605 FCITOFCO_D --- 0.162 R14C25C.FCI to R14C25C.FCO SLICE_0 ROUTE 1 0.000 R14C25C.FCO to R14C25D.FCI n54606 FCITOF0_DE --- 0.585 R14C25D.FCI to R14C25D.F0 SLICE_175 ROUTE 4 3.250 R14C25D.F0 to R13C26D.C1 temperature_code_10_N_1_5 CTOF_DEL --- 0.495 R13C26D.C1 to R13C26D.F1 SLICE_1510 ROUTE 2 1.804 R13C26D.F1 to R12C26B.A0 temperature_code_5 C0TOFCO_DE --- 1.023 R12C26B.A0 to R12C26B.FCO SLICE_28 ROUTE 1 0.000 R12C26B.FCO to R12C26C.FCI n54691 FCITOF0_DE --- 0.585 R12C26C.FCI to R12C26C.F0 SLICE_27 ROUTE 1 2.224 R12C26C.F0 to R10C26B.B1 n12047 C1TOFCO_DE --- 0.889 R10C26B.B1 to R10C26B.FCO SLICE_14 ROUTE 1 0.000 R10C26B.FCO to R10C26C.FCI n54711 FCITOFCO_D --- 0.162 R10C26C.FCI to R10C26C.FCO SLICE_13 ROUTE 1 0.000 R10C26C.FCO to R10C26D.FCI n54712 FCITOF0_DE --- 0.585 R10C26D.FCI to R10C26D.F0 SLICE_12 ROUTE 1 1.420 R10C26D.F0 to R10C28B.B0 n12102 C0TOFCO_DE --- 1.023 R10C28B.B0 to R10C28B.FCO SLICE_21 ROUTE 1 0.000 R10C28B.FCO to R10C28C.FCI n54705 FCITOFCO_D --- 0.162 R10C28C.FCI to R10C28C.FCO SLICE_20 ROUTE 1 0.000 R10C28C.FCO to R10C28D.FCI n54706 FCITOFCO_D --- 0.162 R10C28D.FCI to R10C28D.FCO SLICE_19 ROUTE 1 0.000 R10C28D.FCO to R10C29A.FCI n54707 FCITOF1_DE --- 0.643 R10C29A.FCI to R10C29A.F1 SLICE_18 ROUTE 12 0.992 R10C29A.F1 to R10C29D.A0 bin_code_17 CTOF_DEL --- 0.495 R10C29D.A0 to R10C29D.F0 bin_to_bcd_uut/SLICE_963 ROUTE 2 0.445 R10C29D.F0 to R10C29D.C1 bin_to_bcd_uut/n59905 CTOF_DEL --- 0.495 R10C29D.C1 to R10C29D.F1 bin_to_bcd_uut/SLICE_963 ROUTE 9 2.048 R10C29D.F1 to R16C27A.C0 n8116 CTOF_DEL --- 0.495 R16C27A.C0 to R16C27A.F0 SLICE_1064 ROUTE 9 1.332 R16C27A.F0 to R8C27B.C1 bcd_code_24__N_344 CTOF_DEL --- 0.495 R8C27B.C1 to R8C27B.F1 bin_to_bcd_uut/SLICE_1088 ROUTE 4 0.461 R8C27B.F1 to R8C27B.C0 bin_to_bcd_uut/n8120 CTOF_DEL --- 0.495 R8C27B.C0 to R8C27B.F0 bin_to_bcd_uut/SLICE_1088 ROUTE 4 2.339 R8C27B.F0 to R8C26C.D1 bin_to_bcd_uut/n60848 CTOF_DEL --- 0.495 R8C26C.D1 to R8C26C.F1 bin_to_bcd_uut/SLICE_1393 ROUTE 3 0.782 R8C26C.F1 to R9C26C.C1 bin_to_bcd_uut/n60844 CTOF_DEL --- 0.495 R9C26C.C1 to R9C26C.F1 bin_to_bcd_uut/SLICE_1385 ROUTE 11 1.082 R9C26C.F1 to R9C27C.B0 bin_to_bcd_uut/bcd_code_24__N_380 CTOF_DEL --- 0.495 R9C27C.B0 to R9C27C.F0 bin_to_bcd_uut/SLICE_1120 ROUTE 3 1.180 R9C27C.F0 to R9C26A.C1 bin_to_bcd_uut/n60834 CTOF_DEL --- 0.495 R9C26A.C1 to R9C26A.F1 bin_to_bcd_uut/SLICE_1386 ROUTE 9 1.433 R9C26A.F1 to R8C26D.A1 bin_to_bcd_uut/bcd_code_24__N_407 CTOF_DEL --- 0.495 R8C26D.A1 to R8C26D.F1 bin_to_bcd_uut/SLICE_1118 ROUTE 4 2.290 R8C26D.F1 to R7C26C.B1 bin_to_bcd_uut/n60825 CTOF_DEL --- 0.495 R7C26C.B1 to R7C26C.F1 bin_to_bcd_uut/SLICE_1380 ROUTE 3 1.002 R7C26C.F1 to R8C26A.A1 bin_to_bcd_uut/n60821 CTOF_DEL --- 0.495 R8C26A.A1 to R8C26A.F1 bin_to_bcd_uut/SLICE_1368 ROUTE 9 0.469 R8C26A.F1 to R8C26B.C0 bin_to_bcd_uut/bcd_code_24__N_472 CTOF_DEL --- 0.495 R8C26B.C0 to R8C26B.F0 bin_to_bcd_uut/SLICE_1115 ROUTE 5 2.050 R8C26B.F0 to R8C28A.B0 bin_to_bcd_uut/bcd_code_24__N_467 CTOF_DEL --- 0.495 R8C28A.B0 to R8C28A.F0 bin_to_bcd_uut/SLICE_1366 ROUTE 5 2.746 R8C28A.F0 to R17C28B.B1 bin_to_bcd_uut/n60794 CTOF_DEL --- 0.495 R17C28B.B1 to R17C28B.F1 bin_to_bcd_uut/SLICE_1349 ROUTE 5 1.040 R17C28B.F1 to R17C27C.B0 bin_to_bcd_uut/n60771 CTOF_DEL --- 0.495 R17C27C.B0 to R17C27C.F0 bin_to_bcd_uut/SLICE_1100 ROUTE 2 0.993 R17C27C.F0 to R17C29A.A0 bin_to_bcd_uut/n60765 CTOF_DEL --- 0.495 R17C29A.A0 to R17C29A.F0 bin_to_bcd_uut/SLICE_1103 ROUTE 9 1.574 R17C29A.F0 to R15C29D.C0 bin_to_bcd_uut/bcd_code_24__N_490 CTOF_DEL --- 0.495 R15C29D.C0 to R15C29D.F0 bin_to_bcd_uut/SLICE_1340 ROUTE 2 1.522 R15C29D.F0 to R9C30C.A0 bin_to_bcd_uut/n60743 CTOF_DEL --- 0.495 R9C30C.A0 to R9C30C.F0 bin_to_bcd_uut/SLICE_1341 ROUTE 4 2.389 R9C30C.F0 to R16C27C.A0 bin_to_bcd_uut/n60736 CTOF_DEL --- 0.495 R16C27C.A0 to R16C27C.F0 bin_to_bcd_uut/SLICE_1318 ROUTE 5 0.445 R16C27C.F0 to R16C27C.C1 bin_to_bcd_uut/bcd_code_24__N_527 CTOF_DEL --- 0.495 R16C27C.C1 to R16C27C.F1 bin_to_bcd_uut/SLICE_1318 ROUTE 5 1.476 R16C27C.F1 to R14C26D.B1 bin_to_bcd_uut/n60712 CTOF_DEL --- 0.495 R14C26D.B1 to R14C26D.F1 bin_to_bcd_uut/SLICE_1313 ROUTE 2 0.995 R14C26D.F1 to R15C26B.A1 bin_to_bcd_uut/n60704 CTOF_DEL --- 0.495 R15C26B.A1 to R15C26B.F1 bin_to_bcd_uut/SLICE_1089 ROUTE 9 0.477 R15C26B.F1 to R15C26C.C0 bin_to_bcd_uut/bcd_code_24__N_572 CTOF_DEL --- 0.495 R15C26C.C0 to R15C26C.F0 bin_to_bcd_uut/SLICE_1123 ROUTE 2 1.015 R15C26C.F0 to R14C26D.B0 bin_to_bcd_uut/n60685 CTOF_DEL --- 0.495 R14C26D.B0 to R14C26D.F0 bin_to_bcd_uut/SLICE_1313 ROUTE 10 2.416 R14C26D.F0 to R6C26A.A0 bin_to_bcd_uut/bcd_code_24__N_623 CTOF_DEL --- 0.495 R6C26A.A0 to R6C26A.F0 bin_to_bcd_uut/SLICE_1121 ROUTE 2 0.976 R6C26A.F0 to R6C26C.A1 bin_to_bcd_uut/n60668 CTOF_DEL --- 0.495 R6C26C.A1 to R6C26C.F1 bin_to_bcd_uut/SLICE_1352 ROUTE 9 4.056 R6C26C.F1 to R14C24B.A0 bin_to_bcd_uut/bcd_code_24__N_674 CTOF_DEL --- 0.495 R14C24B.A0 to R14C24B.F0 bin_to_bcd_uut/SLICE_1371 ROUTE 5 1.011 R14C24B.F0 to R15C24D.A0 bin_to_bcd_uut/bcd_code_24__N_669 CTOF_DEL --- 0.495 R15C24D.A0 to R15C24D.F0 bin_to_bcd_uut/SLICE_1320 ROUTE 4 0.718 R15C24D.F0 to R15C24B.B1 bin_to_bcd_uut/n60639 CTOF_DEL --- 0.495 R15C24B.B1 to R15C24B.F1 SLICE_417 ROUTE 3 0.987 R15C24B.F1 to R15C23D.A1 bin_to_bcd_uut/n60635 CTOF_DEL --- 0.495 R15C23D.A1 to R15C23D.F1 SLICE_414 ROUTE 6 0.787 R15C23D.F1 to R15C23B.C1 bin_to_bcd_uut/bcd_code_24__N_716 CTOF_DEL --- 0.495 R15C23B.C1 to R15C23B.F1 SLICE_401 ROUTE 3 1.040 R15C23B.F1 to R15C25C.B0 bin_to_bcd_uut/n60623 CTOF_DEL --- 0.495 R15C25C.B0 to R15C25C.F0 SLICE_404 ROUTE 2 1.023 R15C25C.F0 to R13C27C.M0 bcd_code_18 (to clk_c) -------- 79.646 (30.5% logic, 69.5% route), 48 logic levels. Clock Skew Details: Source Clock Path clk to DS18B20Z_uut/SLICE_1537: Name Fanout Delay (ns) Site Resource ROUTE 531 3.044 C1.PADDI to R12C25D.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_1541: Name Fanout Delay (ns) Site Resource ROUTE 531 3.044 C1.PADDI to R13C27C.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 37.200ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DS18B20Z_uut/data_out_i0_i0 (from clk_c +) Destination: FF Data in control_module_uut/temp_out_i18_23232_23233_reset (to clk_c +) Delay: 79.646ns (30.9% logic, 69.1% route), 50 logic levels. Constraint Details: 79.646ns physical path delay DS18B20Z_uut/SLICE_1537 to SLICE_1541 exceeds 42.794ns delay constraint less 0.000ns skew and 0.348ns M_SET requirement (totaling 42.446ns) by 37.200ns Physical Path Details: Data path DS18B20Z_uut/SLICE_1537 to SLICE_1541: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R12C25D.CLK to R12C25D.Q0 DS18B20Z_uut/SLICE_1537 (from clk_c) ROUTE 5 1.043 R12C25D.Q0 to R14C25A.B1 data_out_0 C1TOFCO_DE --- 0.889 R14C25A.B1 to R14C25A.FCO SLICE_178 ROUTE 1 0.000 R14C25A.FCO to R14C25B.FCI n54604 FCITOFCO_D --- 0.162 R14C25B.FCI to R14C25B.FCO SLICE_177 ROUTE 1 0.000 R14C25B.FCO to R14C25C.FCI n54605 FCITOFCO_D --- 0.162 R14C25C.FCI to R14C25C.FCO SLICE_0 ROUTE 1 0.000 R14C25C.FCO to R14C25D.FCI n54606 FCITOF0_DE --- 0.585 R14C25D.FCI to R14C25D.F0 SLICE_175 ROUTE 4 3.250 R14C25D.F0 to R13C26D.C1 temperature_code_10_N_1_5 CTOF_DEL --- 0.495 R13C26D.C1 to R13C26D.F1 SLICE_1510 ROUTE 2 1.804 R13C26D.F1 to R12C26B.A0 temperature_code_5 C0TOFCO_DE --- 1.023 R12C26B.A0 to R12C26B.FCO SLICE_28 ROUTE 1 0.000 R12C26B.FCO to R12C26C.FCI n54691 FCITOF0_DE --- 0.585 R12C26C.FCI to R12C26C.F0 SLICE_27 ROUTE 1 2.224 R12C26C.F0 to R10C26B.B1 n12047 C1TOFCO_DE --- 0.889 R10C26B.B1 to R10C26B.FCO SLICE_14 ROUTE 1 0.000 R10C26B.FCO to R10C26C.FCI n54711 FCITOFCO_D --- 0.162 R10C26C.FCI to R10C26C.FCO SLICE_13 ROUTE 1 0.000 R10C26C.FCO to R10C26D.FCI n54712 FCITOFCO_D --- 0.162 R10C26D.FCI to R10C26D.FCO SLICE_12 ROUTE 1 0.000 R10C26D.FCO to R10C27A.FCI n54713 FCITOFCO_D --- 0.162 R10C27A.FCI to R10C27A.FCO SLICE_11 ROUTE 1 0.000 R10C27A.FCO to R10C27B.FCI n54714 FCITOFCO_D --- 0.162 R10C27B.FCI to R10C27B.FCO SLICE_10 ROUTE 1 0.000 R10C27B.FCO to R10C27C.FCI n54715 FCITOFCO_D --- 0.162 R10C27C.FCI to R10C27C.FCO SLICE_9 ROUTE 1 0.000 R10C27C.FCO to R10C27D.FCI n54716 FCITOF0_DE --- 0.585 R10C27D.FCI to R10C27D.F0 SLICE_8 ROUTE 1 1.420 R10C27D.F0 to R10C29B.B0 n12113 C0TOFCO_DE --- 1.023 R10C29B.B0 to R10C29B.FCO SLICE_17 ROUTE 1 0.000 R10C29B.FCO to R10C29C.FCI n54709 FCITOF0_DE --- 0.585 R10C29C.FCI to R10C29C.F0 SLICE_16 ROUTE 15 0.726 R10C29C.F0 to R10C29D.B0 bin_code_20 CTOF_DEL --- 0.495 R10C29D.B0 to R10C29D.F0 bin_to_bcd_uut/SLICE_963 ROUTE 2 0.445 R10C29D.F0 to R10C29D.C1 bin_to_bcd_uut/n59905 CTOF_DEL --- 0.495 R10C29D.C1 to R10C29D.F1 bin_to_bcd_uut/SLICE_963 ROUTE 9 2.048 R10C29D.F1 to R16C27A.C0 n8116 CTOF_DEL --- 0.495 R16C27A.C0 to R16C27A.F0 SLICE_1064 ROUTE 9 1.332 R16C27A.F0 to R8C27B.C1 bcd_code_24__N_344 CTOF_DEL --- 0.495 R8C27B.C1 to R8C27B.F1 bin_to_bcd_uut/SLICE_1088 ROUTE 4 0.461 R8C27B.F1 to R8C27B.C0 bin_to_bcd_uut/n8120 CTOF_DEL --- 0.495 R8C27B.C0 to R8C27B.F0 bin_to_bcd_uut/SLICE_1088 ROUTE 4 2.339 R8C27B.F0 to R8C26C.D1 bin_to_bcd_uut/n60848 CTOF_DEL --- 0.495 R8C26C.D1 to R8C26C.F1 bin_to_bcd_uut/SLICE_1393 ROUTE 3 0.782 R8C26C.F1 to R9C26C.C1 bin_to_bcd_uut/n60844 CTOF_DEL --- 0.495 R9C26C.C1 to R9C26C.F1 bin_to_bcd_uut/SLICE_1385 ROUTE 11 1.082 R9C26C.F1 to R9C27C.B0 bin_to_bcd_uut/bcd_code_24__N_380 CTOF_DEL --- 0.495 R9C27C.B0 to R9C27C.F0 bin_to_bcd_uut/SLICE_1120 ROUTE 3 1.180 R9C27C.F0 to R9C26A.C1 bin_to_bcd_uut/n60834 CTOF_DEL --- 0.495 R9C26A.C1 to R9C26A.F1 bin_to_bcd_uut/SLICE_1386 ROUTE 9 1.433 R9C26A.F1 to R8C26D.A1 bin_to_bcd_uut/bcd_code_24__N_407 CTOF_DEL --- 0.495 R8C26D.A1 to R8C26D.F1 bin_to_bcd_uut/SLICE_1118 ROUTE 4 2.290 R8C26D.F1 to R7C26C.B1 bin_to_bcd_uut/n60825 CTOF_DEL --- 0.495 R7C26C.B1 to R7C26C.F1 bin_to_bcd_uut/SLICE_1380 ROUTE 3 1.002 R7C26C.F1 to R8C26A.A1 bin_to_bcd_uut/n60821 CTOF_DEL --- 0.495 R8C26A.A1 to R8C26A.F1 bin_to_bcd_uut/SLICE_1368 ROUTE 9 0.469 R8C26A.F1 to R8C26B.C0 bin_to_bcd_uut/bcd_code_24__N_472 CTOF_DEL --- 0.495 R8C26B.C0 to R8C26B.F0 bin_to_bcd_uut/SLICE_1115 ROUTE 5 2.050 R8C26B.F0 to R8C28A.B0 bin_to_bcd_uut/bcd_code_24__N_467 CTOF_DEL --- 0.495 R8C28A.B0 to R8C28A.F0 bin_to_bcd_uut/SLICE_1366 ROUTE 5 2.746 R8C28A.F0 to R17C28B.B1 bin_to_bcd_uut/n60794 CTOF_DEL --- 0.495 R17C28B.B1 to R17C28B.F1 bin_to_bcd_uut/SLICE_1349 ROUTE 5 1.040 R17C28B.F1 to R17C27C.B0 bin_to_bcd_uut/n60771 CTOF_DEL --- 0.495 R17C27C.B0 to R17C27C.F0 bin_to_bcd_uut/SLICE_1100 ROUTE 2 0.993 R17C27C.F0 to R17C29A.A0 bin_to_bcd_uut/n60765 CTOF_DEL --- 0.495 R17C29A.A0 to R17C29A.F0 bin_to_bcd_uut/SLICE_1103 ROUTE 9 1.574 R17C29A.F0 to R15C29D.C0 bin_to_bcd_uut/bcd_code_24__N_490 CTOF_DEL --- 0.495 R15C29D.C0 to R15C29D.F0 bin_to_bcd_uut/SLICE_1340 ROUTE 2 1.522 R15C29D.F0 to R9C30C.A0 bin_to_bcd_uut/n60743 CTOF_DEL --- 0.495 R9C30C.A0 to R9C30C.F0 bin_to_bcd_uut/SLICE_1341 ROUTE 4 2.389 R9C30C.F0 to R16C27C.A0 bin_to_bcd_uut/n60736 CTOF_DEL --- 0.495 R16C27C.A0 to R16C27C.F0 bin_to_bcd_uut/SLICE_1318 ROUTE 5 0.445 R16C27C.F0 to R16C27C.C1 bin_to_bcd_uut/bcd_code_24__N_527 CTOF_DEL --- 0.495 R16C27C.C1 to R16C27C.F1 bin_to_bcd_uut/SLICE_1318 ROUTE 5 1.476 R16C27C.F1 to R14C26D.B1 bin_to_bcd_uut/n60712 CTOF_DEL --- 0.495 R14C26D.B1 to R14C26D.F1 bin_to_bcd_uut/SLICE_1313 ROUTE 2 0.995 R14C26D.F1 to R15C26B.A1 bin_to_bcd_uut/n60704 CTOF_DEL --- 0.495 R15C26B.A1 to R15C26B.F1 bin_to_bcd_uut/SLICE_1089 ROUTE 9 0.477 R15C26B.F1 to R15C26C.C0 bin_to_bcd_uut/bcd_code_24__N_572 CTOF_DEL --- 0.495 R15C26C.C0 to R15C26C.F0 bin_to_bcd_uut/SLICE_1123 ROUTE 2 1.015 R15C26C.F0 to R14C26D.B0 bin_to_bcd_uut/n60685 CTOF_DEL --- 0.495 R14C26D.B0 to R14C26D.F0 bin_to_bcd_uut/SLICE_1313 ROUTE 10 2.416 R14C26D.F0 to R6C26A.A0 bin_to_bcd_uut/bcd_code_24__N_623 CTOF_DEL --- 0.495 R6C26A.A0 to R6C26A.F0 bin_to_bcd_uut/SLICE_1121 ROUTE 2 0.976 R6C26A.F0 to R6C26C.A1 bin_to_bcd_uut/n60668 CTOF_DEL --- 0.495 R6C26C.A1 to R6C26C.F1 bin_to_bcd_uut/SLICE_1352 ROUTE 9 4.056 R6C26C.F1 to R14C24B.A0 bin_to_bcd_uut/bcd_code_24__N_674 CTOF_DEL --- 0.495 R14C24B.A0 to R14C24B.F0 bin_to_bcd_uut/SLICE_1371 ROUTE 5 1.011 R14C24B.F0 to R15C24D.A0 bin_to_bcd_uut/bcd_code_24__N_669 CTOF_DEL --- 0.495 R15C24D.A0 to R15C24D.F0 bin_to_bcd_uut/SLICE_1320 ROUTE 4 0.718 R15C24D.F0 to R15C24B.B1 bin_to_bcd_uut/n60639 CTOF_DEL --- 0.495 R15C24B.B1 to R15C24B.F1 SLICE_417 ROUTE 3 0.987 R15C24B.F1 to R15C23D.A1 bin_to_bcd_uut/n60635 CTOF_DEL --- 0.495 R15C23D.A1 to R15C23D.F1 SLICE_414 ROUTE 6 0.787 R15C23D.F1 to R15C23B.C1 bin_to_bcd_uut/bcd_code_24__N_716 CTOF_DEL --- 0.495 R15C23B.C1 to R15C23B.F1 SLICE_401 ROUTE 3 1.040 R15C23B.F1 to R15C25C.B0 bin_to_bcd_uut/n60623 CTOF_DEL --- 0.495 R15C25C.B0 to R15C25C.F0 SLICE_404 ROUTE 2 1.023 R15C25C.F0 to R13C27C.M0 bcd_code_18 (to clk_c) -------- 79.646 (30.9% logic, 69.1% route), 50 logic levels. Clock Skew Details: Source Clock Path clk to DS18B20Z_uut/SLICE_1537: Name Fanout Delay (ns) Site Resource ROUTE 531 3.044 C1.PADDI to R12C25D.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_1541: Name Fanout Delay (ns) Site Resource ROUTE 531 3.044 C1.PADDI to R13C27C.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 37.128ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DS18B20Z_uut/data_out_i0_i1 (from clk_c +) Destination: FF Data in control_module_uut/temp_out_i18_23232_23233_reset (to clk_c +) Delay: 79.574ns (30.9% logic, 69.1% route), 49 logic levels. Constraint Details: 79.574ns physical path delay DS18B20Z_uut/SLICE_1537 to SLICE_1541 exceeds 42.794ns delay constraint less 0.000ns skew and 0.348ns M_SET requirement (totaling 42.446ns) by 37.128ns Physical Path Details: Data path DS18B20Z_uut/SLICE_1537 to SLICE_1541: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R12C25D.CLK to R12C25D.Q1 DS18B20Z_uut/SLICE_1537 (from clk_c) ROUTE 5 0.999 R12C25D.Q1 to R14C25B.A0 data_out_1 C0TOFCO_DE --- 1.023 R14C25B.A0 to R14C25B.FCO SLICE_177 ROUTE 1 0.000 R14C25B.FCO to R14C25C.FCI n54605 FCITOFCO_D --- 0.162 R14C25C.FCI to R14C25C.FCO SLICE_0 ROUTE 1 0.000 R14C25C.FCO to R14C25D.FCI n54606 FCITOF0_DE --- 0.585 R14C25D.FCI to R14C25D.F0 SLICE_175 ROUTE 4 3.250 R14C25D.F0 to R13C26D.C1 temperature_code_10_N_1_5 CTOF_DEL --- 0.495 R13C26D.C1 to R13C26D.F1 SLICE_1510 ROUTE 2 1.804 R13C26D.F1 to R12C26B.A0 temperature_code_5 C0TOFCO_DE --- 1.023 R12C26B.A0 to R12C26B.FCO SLICE_28 ROUTE 1 0.000 R12C26B.FCO to R12C26C.FCI n54691 FCITOF0_DE --- 0.585 R12C26C.FCI to R12C26C.F0 SLICE_27 ROUTE 1 2.224 R12C26C.F0 to R10C26B.B1 n12047 C1TOFCO_DE --- 0.889 R10C26B.B1 to R10C26B.FCO SLICE_14 ROUTE 1 0.000 R10C26B.FCO to R10C26C.FCI n54711 FCITOFCO_D --- 0.162 R10C26C.FCI to R10C26C.FCO SLICE_13 ROUTE 1 0.000 R10C26C.FCO to R10C26D.FCI n54712 FCITOF0_DE --- 0.585 R10C26D.FCI to R10C26D.F0 SLICE_12 ROUTE 1 1.420 R10C26D.F0 to R10C28B.B0 n12102 C0TOFCO_DE --- 1.023 R10C28B.B0 to R10C28B.FCO SLICE_21 ROUTE 1 0.000 R10C28B.FCO to R10C28C.FCI n54705 FCITOFCO_D --- 0.162 R10C28C.FCI to R10C28C.FCO SLICE_20 ROUTE 1 0.000 R10C28C.FCO to R10C28D.FCI n54706 FCITOFCO_D --- 0.162 R10C28D.FCI to R10C28D.FCO SLICE_19 ROUTE 1 0.000 R10C28D.FCO to R10C29A.FCI n54707 FCITOFCO_D --- 0.162 R10C29A.FCI to R10C29A.FCO SLICE_18 ROUTE 1 0.000 R10C29A.FCO to R10C29B.FCI n54708 FCITOFCO_D --- 0.162 R10C29B.FCI to R10C29B.FCO SLICE_17 ROUTE 1 0.000 R10C29B.FCO to R10C29C.FCI n54709 FCITOF0_DE --- 0.585 R10C29C.FCI to R10C29C.F0 SLICE_16 ROUTE 15 0.726 R10C29C.F0 to R10C29D.B0 bin_code_20 CTOF_DEL --- 0.495 R10C29D.B0 to R10C29D.F0 bin_to_bcd_uut/SLICE_963 ROUTE 2 0.445 R10C29D.F0 to R10C29D.C1 bin_to_bcd_uut/n59905 CTOF_DEL --- 0.495 R10C29D.C1 to R10C29D.F1 bin_to_bcd_uut/SLICE_963 ROUTE 9 2.048 R10C29D.F1 to R16C27A.C0 n8116 CTOF_DEL --- 0.495 R16C27A.C0 to R16C27A.F0 SLICE_1064 ROUTE 9 1.332 R16C27A.F0 to R8C27B.C1 bcd_code_24__N_344 CTOF_DEL --- 0.495 R8C27B.C1 to R8C27B.F1 bin_to_bcd_uut/SLICE_1088 ROUTE 4 0.461 R8C27B.F1 to R8C27B.C0 bin_to_bcd_uut/n8120 CTOF_DEL --- 0.495 R8C27B.C0 to R8C27B.F0 bin_to_bcd_uut/SLICE_1088 ROUTE 4 2.339 R8C27B.F0 to R8C26C.D1 bin_to_bcd_uut/n60848 CTOF_DEL --- 0.495 R8C26C.D1 to R8C26C.F1 bin_to_bcd_uut/SLICE_1393 ROUTE 3 0.782 R8C26C.F1 to R9C26C.C1 bin_to_bcd_uut/n60844 CTOF_DEL --- 0.495 R9C26C.C1 to R9C26C.F1 bin_to_bcd_uut/SLICE_1385 ROUTE 11 1.082 R9C26C.F1 to R9C27C.B0 bin_to_bcd_uut/bcd_code_24__N_380 CTOF_DEL --- 0.495 R9C27C.B0 to R9C27C.F0 bin_to_bcd_uut/SLICE_1120 ROUTE 3 1.180 R9C27C.F0 to R9C26A.C1 bin_to_bcd_uut/n60834 CTOF_DEL --- 0.495 R9C26A.C1 to R9C26A.F1 bin_to_bcd_uut/SLICE_1386 ROUTE 9 1.433 R9C26A.F1 to R8C26D.A1 bin_to_bcd_uut/bcd_code_24__N_407 CTOF_DEL --- 0.495 R8C26D.A1 to R8C26D.F1 bin_to_bcd_uut/SLICE_1118 ROUTE 4 2.290 R8C26D.F1 to R7C26C.B1 bin_to_bcd_uut/n60825 CTOF_DEL --- 0.495 R7C26C.B1 to R7C26C.F1 bin_to_bcd_uut/SLICE_1380 ROUTE 3 1.002 R7C26C.F1 to R8C26A.A1 bin_to_bcd_uut/n60821 CTOF_DEL --- 0.495 R8C26A.A1 to R8C26A.F1 bin_to_bcd_uut/SLICE_1368 ROUTE 9 0.469 R8C26A.F1 to R8C26B.C0 bin_to_bcd_uut/bcd_code_24__N_472 CTOF_DEL --- 0.495 R8C26B.C0 to R8C26B.F0 bin_to_bcd_uut/SLICE_1115 ROUTE 5 2.050 R8C26B.F0 to R8C28A.B0 bin_to_bcd_uut/bcd_code_24__N_467 CTOF_DEL --- 0.495 R8C28A.B0 to R8C28A.F0 bin_to_bcd_uut/SLICE_1366 ROUTE 5 2.746 R8C28A.F0 to R17C28B.B1 bin_to_bcd_uut/n60794 CTOF_DEL --- 0.495 R17C28B.B1 to R17C28B.F1 bin_to_bcd_uut/SLICE_1349 ROUTE 5 1.040 R17C28B.F1 to R17C27C.B0 bin_to_bcd_uut/n60771 CTOF_DEL --- 0.495 R17C27C.B0 to R17C27C.F0 bin_to_bcd_uut/SLICE_1100 ROUTE 2 0.993 R17C27C.F0 to R17C29A.A0 bin_to_bcd_uut/n60765 CTOF_DEL --- 0.495 R17C29A.A0 to R17C29A.F0 bin_to_bcd_uut/SLICE_1103 ROUTE 9 1.574 R17C29A.F0 to R15C29D.C0 bin_to_bcd_uut/bcd_code_24__N_490 CTOF_DEL --- 0.495 R15C29D.C0 to R15C29D.F0 bin_to_bcd_uut/SLICE_1340 ROUTE 2 1.522 R15C29D.F0 to R9C30C.A0 bin_to_bcd_uut/n60743 CTOF_DEL --- 0.495 R9C30C.A0 to R9C30C.F0 bin_to_bcd_uut/SLICE_1341 ROUTE 4 2.389 R9C30C.F0 to R16C27C.A0 bin_to_bcd_uut/n60736 CTOF_DEL --- 0.495 R16C27C.A0 to R16C27C.F0 bin_to_bcd_uut/SLICE_1318 ROUTE 5 0.445 R16C27C.F0 to R16C27C.C1 bin_to_bcd_uut/bcd_code_24__N_527 CTOF_DEL --- 0.495 R16C27C.C1 to R16C27C.F1 bin_to_bcd_uut/SLICE_1318 ROUTE 5 1.476 R16C27C.F1 to R14C26D.B1 bin_to_bcd_uut/n60712 CTOF_DEL --- 0.495 R14C26D.B1 to R14C26D.F1 bin_to_bcd_uut/SLICE_1313 ROUTE 2 0.995 R14C26D.F1 to R15C26B.A1 bin_to_bcd_uut/n60704 CTOF_DEL --- 0.495 R15C26B.A1 to R15C26B.F1 bin_to_bcd_uut/SLICE_1089 ROUTE 9 0.477 R15C26B.F1 to R15C26C.C0 bin_to_bcd_uut/bcd_code_24__N_572 CTOF_DEL --- 0.495 R15C26C.C0 to R15C26C.F0 bin_to_bcd_uut/SLICE_1123 ROUTE 2 1.015 R15C26C.F0 to R14C26D.B0 bin_to_bcd_uut/n60685 CTOF_DEL --- 0.495 R14C26D.B0 to R14C26D.F0 bin_to_bcd_uut/SLICE_1313 ROUTE 10 2.416 R14C26D.F0 to R6C26A.A0 bin_to_bcd_uut/bcd_code_24__N_623 CTOF_DEL --- 0.495 R6C26A.A0 to R6C26A.F0 bin_to_bcd_uut/SLICE_1121 ROUTE 2 0.976 R6C26A.F0 to R6C26C.A1 bin_to_bcd_uut/n60668 CTOF_DEL --- 0.495 R6C26C.A1 to R6C26C.F1 bin_to_bcd_uut/SLICE_1352 ROUTE 9 4.056 R6C26C.F1 to R14C24B.A0 bin_to_bcd_uut/bcd_code_24__N_674 CTOF_DEL --- 0.495 R14C24B.A0 to R14C24B.F0 bin_to_bcd_uut/SLICE_1371 ROUTE 5 1.011 R14C24B.F0 to R15C24D.A0 bin_to_bcd_uut/bcd_code_24__N_669 CTOF_DEL --- 0.495 R15C24D.A0 to R15C24D.F0 bin_to_bcd_uut/SLICE_1320 ROUTE 4 0.718 R15C24D.F0 to R15C24B.B1 bin_to_bcd_uut/n60639 CTOF_DEL --- 0.495 R15C24B.B1 to R15C24B.F1 SLICE_417 ROUTE 3 0.987 R15C24B.F1 to R15C23D.A1 bin_to_bcd_uut/n60635 CTOF_DEL --- 0.495 R15C23D.A1 to R15C23D.F1 SLICE_414 ROUTE 6 0.787 R15C23D.F1 to R15C23B.C1 bin_to_bcd_uut/bcd_code_24__N_716 CTOF_DEL --- 0.495 R15C23B.C1 to R15C23B.F1 SLICE_401 ROUTE 3 1.040 R15C23B.F1 to R15C25C.B0 bin_to_bcd_uut/n60623 CTOF_DEL --- 0.495 R15C25C.B0 to R15C25C.F0 SLICE_404 ROUTE 2 1.023 R15C25C.F0 to R13C27C.M0 bcd_code_18 (to clk_c) -------- 79.574 (30.9% logic, 69.1% route), 49 logic levels. Clock Skew Details: Source Clock Path clk to DS18B20Z_uut/SLICE_1537: Name Fanout Delay (ns) Site Resource ROUTE 531 3.044 C1.PADDI to R12C25D.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_1541: Name Fanout Delay (ns) Site Resource ROUTE 531 3.044 C1.PADDI to R13C27C.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 37.128ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DS18B20Z_uut/data_out_i0_i1 (from clk_c +) Destination: FF Data in control_module_uut/temp_out_i18_23232_23233_reset (to clk_c +) Delay: 79.574ns (30.5% logic, 69.5% route), 47 logic levels. Constraint Details: 79.574ns physical path delay DS18B20Z_uut/SLICE_1537 to SLICE_1541 exceeds 42.794ns delay constraint less 0.000ns skew and 0.348ns M_SET requirement (totaling 42.446ns) by 37.128ns Physical Path Details: Data path DS18B20Z_uut/SLICE_1537 to SLICE_1541: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R12C25D.CLK to R12C25D.Q1 DS18B20Z_uut/SLICE_1537 (from clk_c) ROUTE 5 0.999 R12C25D.Q1 to R14C25B.A0 data_out_1 C0TOFCO_DE --- 1.023 R14C25B.A0 to R14C25B.FCO SLICE_177 ROUTE 1 0.000 R14C25B.FCO to R14C25C.FCI n54605 FCITOFCO_D --- 0.162 R14C25C.FCI to R14C25C.FCO SLICE_0 ROUTE 1 0.000 R14C25C.FCO to R14C25D.FCI n54606 FCITOF0_DE --- 0.585 R14C25D.FCI to R14C25D.F0 SLICE_175 ROUTE 4 3.250 R14C25D.F0 to R13C26D.C1 temperature_code_10_N_1_5 CTOF_DEL --- 0.495 R13C26D.C1 to R13C26D.F1 SLICE_1510 ROUTE 2 1.804 R13C26D.F1 to R12C26B.A0 temperature_code_5 C0TOFCO_DE --- 1.023 R12C26B.A0 to R12C26B.FCO SLICE_28 ROUTE 1 0.000 R12C26B.FCO to R12C26C.FCI n54691 FCITOF0_DE --- 0.585 R12C26C.FCI to R12C26C.F0 SLICE_27 ROUTE 1 2.224 R12C26C.F0 to R10C26B.B1 n12047 C1TOFCO_DE --- 0.889 R10C26B.B1 to R10C26B.FCO SLICE_14 ROUTE 1 0.000 R10C26B.FCO to R10C26C.FCI n54711 FCITOFCO_D --- 0.162 R10C26C.FCI to R10C26C.FCO SLICE_13 ROUTE 1 0.000 R10C26C.FCO to R10C26D.FCI n54712 FCITOF0_DE --- 0.585 R10C26D.FCI to R10C26D.F0 SLICE_12 ROUTE 1 1.420 R10C26D.F0 to R10C28B.B0 n12102 C0TOFCO_DE --- 1.023 R10C28B.B0 to R10C28B.FCO SLICE_21 ROUTE 1 0.000 R10C28B.FCO to R10C28C.FCI n54705 FCITOFCO_D --- 0.162 R10C28C.FCI to R10C28C.FCO SLICE_20 ROUTE 1 0.000 R10C28C.FCO to R10C28D.FCI n54706 FCITOFCO_D --- 0.162 R10C28D.FCI to R10C28D.FCO SLICE_19 ROUTE 1 0.000 R10C28D.FCO to R10C29A.FCI n54707 FCITOF1_DE --- 0.643 R10C29A.FCI to R10C29A.F1 SLICE_18 ROUTE 12 0.992 R10C29A.F1 to R10C29D.A0 bin_code_17 CTOF_DEL --- 0.495 R10C29D.A0 to R10C29D.F0 bin_to_bcd_uut/SLICE_963 ROUTE 2 0.445 R10C29D.F0 to R10C29D.C1 bin_to_bcd_uut/n59905 CTOF_DEL --- 0.495 R10C29D.C1 to R10C29D.F1 bin_to_bcd_uut/SLICE_963 ROUTE 9 2.048 R10C29D.F1 to R16C27A.C0 n8116 CTOF_DEL --- 0.495 R16C27A.C0 to R16C27A.F0 SLICE_1064 ROUTE 9 1.332 R16C27A.F0 to R8C27B.C1 bcd_code_24__N_344 CTOF_DEL --- 0.495 R8C27B.C1 to R8C27B.F1 bin_to_bcd_uut/SLICE_1088 ROUTE 4 0.461 R8C27B.F1 to R8C27B.C0 bin_to_bcd_uut/n8120 CTOF_DEL --- 0.495 R8C27B.C0 to R8C27B.F0 bin_to_bcd_uut/SLICE_1088 ROUTE 4 2.339 R8C27B.F0 to R8C26C.D1 bin_to_bcd_uut/n60848 CTOF_DEL --- 0.495 R8C26C.D1 to R8C26C.F1 bin_to_bcd_uut/SLICE_1393 ROUTE 3 0.782 R8C26C.F1 to R9C26C.C1 bin_to_bcd_uut/n60844 CTOF_DEL --- 0.495 R9C26C.C1 to R9C26C.F1 bin_to_bcd_uut/SLICE_1385 ROUTE 11 1.082 R9C26C.F1 to R9C27C.B0 bin_to_bcd_uut/bcd_code_24__N_380 CTOF_DEL --- 0.495 R9C27C.B0 to R9C27C.F0 bin_to_bcd_uut/SLICE_1120 ROUTE 3 1.180 R9C27C.F0 to R9C26A.C1 bin_to_bcd_uut/n60834 CTOF_DEL --- 0.495 R9C26A.C1 to R9C26A.F1 bin_to_bcd_uut/SLICE_1386 ROUTE 9 1.433 R9C26A.F1 to R8C26D.A1 bin_to_bcd_uut/bcd_code_24__N_407 CTOF_DEL --- 0.495 R8C26D.A1 to R8C26D.F1 bin_to_bcd_uut/SLICE_1118 ROUTE 4 2.290 R8C26D.F1 to R7C26C.B1 bin_to_bcd_uut/n60825 CTOF_DEL --- 0.495 R7C26C.B1 to R7C26C.F1 bin_to_bcd_uut/SLICE_1380 ROUTE 3 1.002 R7C26C.F1 to R8C26A.A1 bin_to_bcd_uut/n60821 CTOF_DEL --- 0.495 R8C26A.A1 to R8C26A.F1 bin_to_bcd_uut/SLICE_1368 ROUTE 9 0.469 R8C26A.F1 to R8C26B.C0 bin_to_bcd_uut/bcd_code_24__N_472 CTOF_DEL --- 0.495 R8C26B.C0 to R8C26B.F0 bin_to_bcd_uut/SLICE_1115 ROUTE 5 2.050 R8C26B.F0 to R8C28A.B0 bin_to_bcd_uut/bcd_code_24__N_467 CTOF_DEL --- 0.495 R8C28A.B0 to R8C28A.F0 bin_to_bcd_uut/SLICE_1366 ROUTE 5 2.746 R8C28A.F0 to R17C28B.B1 bin_to_bcd_uut/n60794 CTOF_DEL --- 0.495 R17C28B.B1 to R17C28B.F1 bin_to_bcd_uut/SLICE_1349 ROUTE 5 1.040 R17C28B.F1 to R17C27C.B0 bin_to_bcd_uut/n60771 CTOF_DEL --- 0.495 R17C27C.B0 to R17C27C.F0 bin_to_bcd_uut/SLICE_1100 ROUTE 2 0.993 R17C27C.F0 to R17C29A.A0 bin_to_bcd_uut/n60765 CTOF_DEL --- 0.495 R17C29A.A0 to R17C29A.F0 bin_to_bcd_uut/SLICE_1103 ROUTE 9 1.574 R17C29A.F0 to R15C29D.C0 bin_to_bcd_uut/bcd_code_24__N_490 CTOF_DEL --- 0.495 R15C29D.C0 to R15C29D.F0 bin_to_bcd_uut/SLICE_1340 ROUTE 2 1.522 R15C29D.F0 to R9C30C.A0 bin_to_bcd_uut/n60743 CTOF_DEL --- 0.495 R9C30C.A0 to R9C30C.F0 bin_to_bcd_uut/SLICE_1341 ROUTE 4 2.389 R9C30C.F0 to R16C27C.A0 bin_to_bcd_uut/n60736 CTOF_DEL --- 0.495 R16C27C.A0 to R16C27C.F0 bin_to_bcd_uut/SLICE_1318 ROUTE 5 0.445 R16C27C.F0 to R16C27C.C1 bin_to_bcd_uut/bcd_code_24__N_527 CTOF_DEL --- 0.495 R16C27C.C1 to R16C27C.F1 bin_to_bcd_uut/SLICE_1318 ROUTE 5 1.476 R16C27C.F1 to R14C26D.B1 bin_to_bcd_uut/n60712 CTOF_DEL --- 0.495 R14C26D.B1 to R14C26D.F1 bin_to_bcd_uut/SLICE_1313 ROUTE 2 0.995 R14C26D.F1 to R15C26B.A1 bin_to_bcd_uut/n60704 CTOF_DEL --- 0.495 R15C26B.A1 to R15C26B.F1 bin_to_bcd_uut/SLICE_1089 ROUTE 9 0.477 R15C26B.F1 to R15C26C.C0 bin_to_bcd_uut/bcd_code_24__N_572 CTOF_DEL --- 0.495 R15C26C.C0 to R15C26C.F0 bin_to_bcd_uut/SLICE_1123 ROUTE 2 1.015 R15C26C.F0 to R14C26D.B0 bin_to_bcd_uut/n60685 CTOF_DEL --- 0.495 R14C26D.B0 to R14C26D.F0 bin_to_bcd_uut/SLICE_1313 ROUTE 10 2.416 R14C26D.F0 to R6C26A.A0 bin_to_bcd_uut/bcd_code_24__N_623 CTOF_DEL --- 0.495 R6C26A.A0 to R6C26A.F0 bin_to_bcd_uut/SLICE_1121 ROUTE 2 0.976 R6C26A.F0 to R6C26C.A1 bin_to_bcd_uut/n60668 CTOF_DEL --- 0.495 R6C26C.A1 to R6C26C.F1 bin_to_bcd_uut/SLICE_1352 ROUTE 9 4.056 R6C26C.F1 to R14C24B.A0 bin_to_bcd_uut/bcd_code_24__N_674 CTOF_DEL --- 0.495 R14C24B.A0 to R14C24B.F0 bin_to_bcd_uut/SLICE_1371 ROUTE 5 1.011 R14C24B.F0 to R15C24D.A0 bin_to_bcd_uut/bcd_code_24__N_669 CTOF_DEL --- 0.495 R15C24D.A0 to R15C24D.F0 bin_to_bcd_uut/SLICE_1320 ROUTE 4 0.718 R15C24D.F0 to R15C24B.B1 bin_to_bcd_uut/n60639 CTOF_DEL --- 0.495 R15C24B.B1 to R15C24B.F1 SLICE_417 ROUTE 3 0.987 R15C24B.F1 to R15C23D.A1 bin_to_bcd_uut/n60635 CTOF_DEL --- 0.495 R15C23D.A1 to R15C23D.F1 SLICE_414 ROUTE 6 0.787 R15C23D.F1 to R15C23B.C1 bin_to_bcd_uut/bcd_code_24__N_716 CTOF_DEL --- 0.495 R15C23B.C1 to R15C23B.F1 SLICE_401 ROUTE 3 1.040 R15C23B.F1 to R15C25C.B0 bin_to_bcd_uut/n60623 CTOF_DEL --- 0.495 R15C25C.B0 to R15C25C.F0 SLICE_404 ROUTE 2 1.023 R15C25C.F0 to R13C27C.M0 bcd_code_18 (to clk_c) -------- 79.574 (30.5% logic, 69.5% route), 47 logic levels. Clock Skew Details: Source Clock Path clk to DS18B20Z_uut/SLICE_1537: Name Fanout Delay (ns) Site Resource ROUTE 531 3.044 C1.PADDI to R12C25D.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_1541: Name Fanout Delay (ns) Site Resource ROUTE 531 3.044 C1.PADDI to R13C27C.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 37.128ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DS18B20Z_uut/data_out_i0_i1 (from clk_c +) Destination: FF Data in control_module_uut/temp_out_i18_23232_23233_reset (to clk_c +) Delay: 79.574ns (30.9% logic, 69.1% route), 49 logic levels. Constraint Details: 79.574ns physical path delay DS18B20Z_uut/SLICE_1537 to SLICE_1541 exceeds 42.794ns delay constraint less 0.000ns skew and 0.348ns M_SET requirement (totaling 42.446ns) by 37.128ns Physical Path Details: Data path DS18B20Z_uut/SLICE_1537 to SLICE_1541: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R12C25D.CLK to R12C25D.Q1 DS18B20Z_uut/SLICE_1537 (from clk_c) ROUTE 5 0.999 R12C25D.Q1 to R14C25B.A0 data_out_1 C0TOFCO_DE --- 1.023 R14C25B.A0 to R14C25B.FCO SLICE_177 ROUTE 1 0.000 R14C25B.FCO to R14C25C.FCI n54605 FCITOFCO_D --- 0.162 R14C25C.FCI to R14C25C.FCO SLICE_0 ROUTE 1 0.000 R14C25C.FCO to R14C25D.FCI n54606 FCITOF0_DE --- 0.585 R14C25D.FCI to R14C25D.F0 SLICE_175 ROUTE 4 3.250 R14C25D.F0 to R13C26D.C1 temperature_code_10_N_1_5 CTOF_DEL --- 0.495 R13C26D.C1 to R13C26D.F1 SLICE_1510 ROUTE 2 1.804 R13C26D.F1 to R12C26B.A0 temperature_code_5 C0TOFCO_DE --- 1.023 R12C26B.A0 to R12C26B.FCO SLICE_28 ROUTE 1 0.000 R12C26B.FCO to R12C26C.FCI n54691 FCITOF0_DE --- 0.585 R12C26C.FCI to R12C26C.F0 SLICE_27 ROUTE 1 2.224 R12C26C.F0 to R10C26B.B1 n12047 C1TOFCO_DE --- 0.889 R10C26B.B1 to R10C26B.FCO SLICE_14 ROUTE 1 0.000 R10C26B.FCO to R10C26C.FCI n54711 FCITOFCO_D --- 0.162 R10C26C.FCI to R10C26C.FCO SLICE_13 ROUTE 1 0.000 R10C26C.FCO to R10C26D.FCI n54712 FCITOFCO_D --- 0.162 R10C26D.FCI to R10C26D.FCO SLICE_12 ROUTE 1 0.000 R10C26D.FCO to R10C27A.FCI n54713 FCITOFCO_D --- 0.162 R10C27A.FCI to R10C27A.FCO SLICE_11 ROUTE 1 0.000 R10C27A.FCO to R10C27B.FCI n54714 FCITOFCO_D --- 0.162 R10C27B.FCI to R10C27B.FCO SLICE_10 ROUTE 1 0.000 R10C27B.FCO to R10C27C.FCI n54715 FCITOFCO_D --- 0.162 R10C27C.FCI to R10C27C.FCO SLICE_9 ROUTE 1 0.000 R10C27C.FCO to R10C27D.FCI n54716 FCITOF0_DE --- 0.585 R10C27D.FCI to R10C27D.F0 SLICE_8 ROUTE 1 1.420 R10C27D.F0 to R10C29B.B0 n12113 C0TOFCO_DE --- 1.023 R10C29B.B0 to R10C29B.FCO SLICE_17 ROUTE 1 0.000 R10C29B.FCO to R10C29C.FCI n54709 FCITOF0_DE --- 0.585 R10C29C.FCI to R10C29C.F0 SLICE_16 ROUTE 15 0.726 R10C29C.F0 to R10C29D.B0 bin_code_20 CTOF_DEL --- 0.495 R10C29D.B0 to R10C29D.F0 bin_to_bcd_uut/SLICE_963 ROUTE 2 0.445 R10C29D.F0 to R10C29D.C1 bin_to_bcd_uut/n59905 CTOF_DEL --- 0.495 R10C29D.C1 to R10C29D.F1 bin_to_bcd_uut/SLICE_963 ROUTE 9 2.048 R10C29D.F1 to R16C27A.C0 n8116 CTOF_DEL --- 0.495 R16C27A.C0 to R16C27A.F0 SLICE_1064 ROUTE 9 1.332 R16C27A.F0 to R8C27B.C1 bcd_code_24__N_344 CTOF_DEL --- 0.495 R8C27B.C1 to R8C27B.F1 bin_to_bcd_uut/SLICE_1088 ROUTE 4 0.461 R8C27B.F1 to R8C27B.C0 bin_to_bcd_uut/n8120 CTOF_DEL --- 0.495 R8C27B.C0 to R8C27B.F0 bin_to_bcd_uut/SLICE_1088 ROUTE 4 2.339 R8C27B.F0 to R8C26C.D1 bin_to_bcd_uut/n60848 CTOF_DEL --- 0.495 R8C26C.D1 to R8C26C.F1 bin_to_bcd_uut/SLICE_1393 ROUTE 3 0.782 R8C26C.F1 to R9C26C.C1 bin_to_bcd_uut/n60844 CTOF_DEL --- 0.495 R9C26C.C1 to R9C26C.F1 bin_to_bcd_uut/SLICE_1385 ROUTE 11 1.082 R9C26C.F1 to R9C27C.B0 bin_to_bcd_uut/bcd_code_24__N_380 CTOF_DEL --- 0.495 R9C27C.B0 to R9C27C.F0 bin_to_bcd_uut/SLICE_1120 ROUTE 3 1.180 R9C27C.F0 to R9C26A.C1 bin_to_bcd_uut/n60834 CTOF_DEL --- 0.495 R9C26A.C1 to R9C26A.F1 bin_to_bcd_uut/SLICE_1386 ROUTE 9 1.433 R9C26A.F1 to R8C26D.A1 bin_to_bcd_uut/bcd_code_24__N_407 CTOF_DEL --- 0.495 R8C26D.A1 to R8C26D.F1 bin_to_bcd_uut/SLICE_1118 ROUTE 4 2.290 R8C26D.F1 to R7C26C.B1 bin_to_bcd_uut/n60825 CTOF_DEL --- 0.495 R7C26C.B1 to R7C26C.F1 bin_to_bcd_uut/SLICE_1380 ROUTE 3 1.002 R7C26C.F1 to R8C26A.A1 bin_to_bcd_uut/n60821 CTOF_DEL --- 0.495 R8C26A.A1 to R8C26A.F1 bin_to_bcd_uut/SLICE_1368 ROUTE 9 0.469 R8C26A.F1 to R8C26B.C0 bin_to_bcd_uut/bcd_code_24__N_472 CTOF_DEL --- 0.495 R8C26B.C0 to R8C26B.F0 bin_to_bcd_uut/SLICE_1115 ROUTE 5 2.050 R8C26B.F0 to R8C28A.B0 bin_to_bcd_uut/bcd_code_24__N_467 CTOF_DEL --- 0.495 R8C28A.B0 to R8C28A.F0 bin_to_bcd_uut/SLICE_1366 ROUTE 5 2.746 R8C28A.F0 to R17C28B.B1 bin_to_bcd_uut/n60794 CTOF_DEL --- 0.495 R17C28B.B1 to R17C28B.F1 bin_to_bcd_uut/SLICE_1349 ROUTE 5 1.040 R17C28B.F1 to R17C27C.B0 bin_to_bcd_uut/n60771 CTOF_DEL --- 0.495 R17C27C.B0 to R17C27C.F0 bin_to_bcd_uut/SLICE_1100 ROUTE 2 0.993 R17C27C.F0 to R17C29A.A0 bin_to_bcd_uut/n60765 CTOF_DEL --- 0.495 R17C29A.A0 to R17C29A.F0 bin_to_bcd_uut/SLICE_1103 ROUTE 9 1.574 R17C29A.F0 to R15C29D.C0 bin_to_bcd_uut/bcd_code_24__N_490 CTOF_DEL --- 0.495 R15C29D.C0 to R15C29D.F0 bin_to_bcd_uut/SLICE_1340 ROUTE 2 1.522 R15C29D.F0 to R9C30C.A0 bin_to_bcd_uut/n60743 CTOF_DEL --- 0.495 R9C30C.A0 to R9C30C.F0 bin_to_bcd_uut/SLICE_1341 ROUTE 4 2.389 R9C30C.F0 to R16C27C.A0 bin_to_bcd_uut/n60736 CTOF_DEL --- 0.495 R16C27C.A0 to R16C27C.F0 bin_to_bcd_uut/SLICE_1318 ROUTE 5 0.445 R16C27C.F0 to R16C27C.C1 bin_to_bcd_uut/bcd_code_24__N_527 CTOF_DEL --- 0.495 R16C27C.C1 to R16C27C.F1 bin_to_bcd_uut/SLICE_1318 ROUTE 5 1.476 R16C27C.F1 to R14C26D.B1 bin_to_bcd_uut/n60712 CTOF_DEL --- 0.495 R14C26D.B1 to R14C26D.F1 bin_to_bcd_uut/SLICE_1313 ROUTE 2 0.995 R14C26D.F1 to R15C26B.A1 bin_to_bcd_uut/n60704 CTOF_DEL --- 0.495 R15C26B.A1 to R15C26B.F1 bin_to_bcd_uut/SLICE_1089 ROUTE 9 0.477 R15C26B.F1 to R15C26C.C0 bin_to_bcd_uut/bcd_code_24__N_572 CTOF_DEL --- 0.495 R15C26C.C0 to R15C26C.F0 bin_to_bcd_uut/SLICE_1123 ROUTE 2 1.015 R15C26C.F0 to R14C26D.B0 bin_to_bcd_uut/n60685 CTOF_DEL --- 0.495 R14C26D.B0 to R14C26D.F0 bin_to_bcd_uut/SLICE_1313 ROUTE 10 2.416 R14C26D.F0 to R6C26A.A0 bin_to_bcd_uut/bcd_code_24__N_623 CTOF_DEL --- 0.495 R6C26A.A0 to R6C26A.F0 bin_to_bcd_uut/SLICE_1121 ROUTE 2 0.976 R6C26A.F0 to R6C26C.A1 bin_to_bcd_uut/n60668 CTOF_DEL --- 0.495 R6C26C.A1 to R6C26C.F1 bin_to_bcd_uut/SLICE_1352 ROUTE 9 4.056 R6C26C.F1 to R14C24B.A0 bin_to_bcd_uut/bcd_code_24__N_674 CTOF_DEL --- 0.495 R14C24B.A0 to R14C24B.F0 bin_to_bcd_uut/SLICE_1371 ROUTE 5 1.011 R14C24B.F0 to R15C24D.A0 bin_to_bcd_uut/bcd_code_24__N_669 CTOF_DEL --- 0.495 R15C24D.A0 to R15C24D.F0 bin_to_bcd_uut/SLICE_1320 ROUTE 4 0.718 R15C24D.F0 to R15C24B.B1 bin_to_bcd_uut/n60639 CTOF_DEL --- 0.495 R15C24B.B1 to R15C24B.F1 SLICE_417 ROUTE 3 0.987 R15C24B.F1 to R15C23D.A1 bin_to_bcd_uut/n60635 CTOF_DEL --- 0.495 R15C23D.A1 to R15C23D.F1 SLICE_414 ROUTE 6 0.787 R15C23D.F1 to R15C23B.C1 bin_to_bcd_uut/bcd_code_24__N_716 CTOF_DEL --- 0.495 R15C23B.C1 to R15C23B.F1 SLICE_401 ROUTE 3 1.040 R15C23B.F1 to R15C25C.B0 bin_to_bcd_uut/n60623 CTOF_DEL --- 0.495 R15C25C.B0 to R15C25C.F0 SLICE_404 ROUTE 2 1.023 R15C25C.F0 to R13C27C.M0 bcd_code_18 (to clk_c) -------- 79.574 (30.9% logic, 69.1% route), 49 logic levels. Clock Skew Details: Source Clock Path clk to DS18B20Z_uut/SLICE_1537: Name Fanout Delay (ns) Site Resource ROUTE 531 3.044 C1.PADDI to R12C25D.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_1541: Name Fanout Delay (ns) Site Resource ROUTE 531 3.044 C1.PADDI to R13C27C.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 37.124ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DS18B20Z_uut/data_out_i0_i0 (from clk_c +) Destination: FF Data in control_module_uut/temp_out_i18_23232_23233_reset (to clk_c +) Delay: 79.570ns (30.8% logic, 69.2% route), 50 logic levels. Constraint Details: 79.570ns physical path delay DS18B20Z_uut/SLICE_1537 to SLICE_1541 exceeds 42.794ns delay constraint less 0.000ns skew and 0.348ns M_SET requirement (totaling 42.446ns) by 37.124ns Physical Path Details: Data path DS18B20Z_uut/SLICE_1537 to SLICE_1541: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R12C25D.CLK to R12C25D.Q0 DS18B20Z_uut/SLICE_1537 (from clk_c) ROUTE 5 1.043 R12C25D.Q0 to R14C25A.B1 data_out_0 C1TOFCO_DE --- 0.889 R14C25A.B1 to R14C25A.FCO SLICE_178 ROUTE 1 0.000 R14C25A.FCO to R14C25B.FCI n54604 FCITOFCO_D --- 0.162 R14C25B.FCI to R14C25B.FCO SLICE_177 ROUTE 1 0.000 R14C25B.FCO to R14C25C.FCI n54605 FCITOFCO_D --- 0.162 R14C25C.FCI to R14C25C.FCO SLICE_0 ROUTE 1 0.000 R14C25C.FCO to R14C25D.FCI n54606 FCITOF0_DE --- 0.585 R14C25D.FCI to R14C25D.F0 SLICE_175 ROUTE 4 3.250 R14C25D.F0 to R13C26D.C1 temperature_code_10_N_1_5 CTOF_DEL --- 0.495 R13C26D.C1 to R13C26D.F1 SLICE_1510 ROUTE 2 1.804 R13C26D.F1 to R12C26B.A0 temperature_code_5 C0TOFCO_DE --- 1.023 R12C26B.A0 to R12C26B.FCO SLICE_28 ROUTE 1 0.000 R12C26B.FCO to R12C26C.FCI n54691 FCITOF0_DE --- 0.585 R12C26C.FCI to R12C26C.F0 SLICE_27 ROUTE 1 2.224 R12C26C.F0 to R10C26B.B1 n12047 C1TOFCO_DE --- 0.889 R10C26B.B1 to R10C26B.FCO SLICE_14 ROUTE 1 0.000 R10C26B.FCO to R10C26C.FCI n54711 FCITOFCO_D --- 0.162 R10C26C.FCI to R10C26C.FCO SLICE_13 ROUTE 1 0.000 R10C26C.FCO to R10C26D.FCI n54712 FCITOF1_DE --- 0.643 R10C26D.FCI to R10C26D.F1 SLICE_12 ROUTE 1 1.420 R10C26D.F1 to R10C28B.B1 n12101 C1TOFCO_DE --- 0.889 R10C28B.B1 to R10C28B.FCO SLICE_21 ROUTE 1 0.000 R10C28B.FCO to R10C28C.FCI n54705 FCITOFCO_D --- 0.162 R10C28C.FCI to R10C28C.FCO SLICE_20 ROUTE 1 0.000 R10C28C.FCO to R10C28D.FCI n54706 FCITOFCO_D --- 0.162 R10C28D.FCI to R10C28D.FCO SLICE_19 ROUTE 1 0.000 R10C28D.FCO to R10C29A.FCI n54707 FCITOFCO_D --- 0.162 R10C29A.FCI to R10C29A.FCO SLICE_18 ROUTE 1 0.000 R10C29A.FCO to R10C29B.FCI n54708 FCITOFCO_D --- 0.162 R10C29B.FCI to R10C29B.FCO SLICE_17 ROUTE 1 0.000 R10C29B.FCO to R10C29C.FCI n54709 FCITOF0_DE --- 0.585 R10C29C.FCI to R10C29C.F0 SLICE_16 ROUTE 15 0.726 R10C29C.F0 to R10C29D.B0 bin_code_20 CTOF_DEL --- 0.495 R10C29D.B0 to R10C29D.F0 bin_to_bcd_uut/SLICE_963 ROUTE 2 0.445 R10C29D.F0 to R10C29D.C1 bin_to_bcd_uut/n59905 CTOF_DEL --- 0.495 R10C29D.C1 to R10C29D.F1 bin_to_bcd_uut/SLICE_963 ROUTE 9 2.048 R10C29D.F1 to R16C27A.C0 n8116 CTOF_DEL --- 0.495 R16C27A.C0 to R16C27A.F0 SLICE_1064 ROUTE 9 1.332 R16C27A.F0 to R8C27B.C1 bcd_code_24__N_344 CTOF_DEL --- 0.495 R8C27B.C1 to R8C27B.F1 bin_to_bcd_uut/SLICE_1088 ROUTE 4 0.461 R8C27B.F1 to R8C27B.C0 bin_to_bcd_uut/n8120 CTOF_DEL --- 0.495 R8C27B.C0 to R8C27B.F0 bin_to_bcd_uut/SLICE_1088 ROUTE 4 2.339 R8C27B.F0 to R8C26C.D1 bin_to_bcd_uut/n60848 CTOF_DEL --- 0.495 R8C26C.D1 to R8C26C.F1 bin_to_bcd_uut/SLICE_1393 ROUTE 3 0.782 R8C26C.F1 to R9C26C.C1 bin_to_bcd_uut/n60844 CTOF_DEL --- 0.495 R9C26C.C1 to R9C26C.F1 bin_to_bcd_uut/SLICE_1385 ROUTE 11 1.082 R9C26C.F1 to R9C27C.B0 bin_to_bcd_uut/bcd_code_24__N_380 CTOF_DEL --- 0.495 R9C27C.B0 to R9C27C.F0 bin_to_bcd_uut/SLICE_1120 ROUTE 3 1.180 R9C27C.F0 to R9C26A.C1 bin_to_bcd_uut/n60834 CTOF_DEL --- 0.495 R9C26A.C1 to R9C26A.F1 bin_to_bcd_uut/SLICE_1386 ROUTE 9 1.433 R9C26A.F1 to R8C26D.A1 bin_to_bcd_uut/bcd_code_24__N_407 CTOF_DEL --- 0.495 R8C26D.A1 to R8C26D.F1 bin_to_bcd_uut/SLICE_1118 ROUTE 4 2.290 R8C26D.F1 to R7C26C.B1 bin_to_bcd_uut/n60825 CTOF_DEL --- 0.495 R7C26C.B1 to R7C26C.F1 bin_to_bcd_uut/SLICE_1380 ROUTE 3 1.002 R7C26C.F1 to R8C26A.A1 bin_to_bcd_uut/n60821 CTOF_DEL --- 0.495 R8C26A.A1 to R8C26A.F1 bin_to_bcd_uut/SLICE_1368 ROUTE 9 0.469 R8C26A.F1 to R8C26B.C0 bin_to_bcd_uut/bcd_code_24__N_472 CTOF_DEL --- 0.495 R8C26B.C0 to R8C26B.F0 bin_to_bcd_uut/SLICE_1115 ROUTE 5 2.050 R8C26B.F0 to R8C28A.B0 bin_to_bcd_uut/bcd_code_24__N_467 CTOF_DEL --- 0.495 R8C28A.B0 to R8C28A.F0 bin_to_bcd_uut/SLICE_1366 ROUTE 5 2.746 R8C28A.F0 to R17C28B.B1 bin_to_bcd_uut/n60794 CTOF_DEL --- 0.495 R17C28B.B1 to R17C28B.F1 bin_to_bcd_uut/SLICE_1349 ROUTE 5 1.040 R17C28B.F1 to R17C27C.B0 bin_to_bcd_uut/n60771 CTOF_DEL --- 0.495 R17C27C.B0 to R17C27C.F0 bin_to_bcd_uut/SLICE_1100 ROUTE 2 0.993 R17C27C.F0 to R17C29A.A0 bin_to_bcd_uut/n60765 CTOF_DEL --- 0.495 R17C29A.A0 to R17C29A.F0 bin_to_bcd_uut/SLICE_1103 ROUTE 9 1.574 R17C29A.F0 to R15C29D.C0 bin_to_bcd_uut/bcd_code_24__N_490 CTOF_DEL --- 0.495 R15C29D.C0 to R15C29D.F0 bin_to_bcd_uut/SLICE_1340 ROUTE 2 1.522 R15C29D.F0 to R9C30C.A0 bin_to_bcd_uut/n60743 CTOF_DEL --- 0.495 R9C30C.A0 to R9C30C.F0 bin_to_bcd_uut/SLICE_1341 ROUTE 4 2.389 R9C30C.F0 to R16C27C.A0 bin_to_bcd_uut/n60736 CTOF_DEL --- 0.495 R16C27C.A0 to R16C27C.F0 bin_to_bcd_uut/SLICE_1318 ROUTE 5 0.445 R16C27C.F0 to R16C27C.C1 bin_to_bcd_uut/bcd_code_24__N_527 CTOF_DEL --- 0.495 R16C27C.C1 to R16C27C.F1 bin_to_bcd_uut/SLICE_1318 ROUTE 5 1.476 R16C27C.F1 to R14C26D.B1 bin_to_bcd_uut/n60712 CTOF_DEL --- 0.495 R14C26D.B1 to R14C26D.F1 bin_to_bcd_uut/SLICE_1313 ROUTE 2 0.995 R14C26D.F1 to R15C26B.A1 bin_to_bcd_uut/n60704 CTOF_DEL --- 0.495 R15C26B.A1 to R15C26B.F1 bin_to_bcd_uut/SLICE_1089 ROUTE 9 0.477 R15C26B.F1 to R15C26C.C0 bin_to_bcd_uut/bcd_code_24__N_572 CTOF_DEL --- 0.495 R15C26C.C0 to R15C26C.F0 bin_to_bcd_uut/SLICE_1123 ROUTE 2 1.015 R15C26C.F0 to R14C26D.B0 bin_to_bcd_uut/n60685 CTOF_DEL --- 0.495 R14C26D.B0 to R14C26D.F0 bin_to_bcd_uut/SLICE_1313 ROUTE 10 2.416 R14C26D.F0 to R6C26A.A0 bin_to_bcd_uut/bcd_code_24__N_623 CTOF_DEL --- 0.495 R6C26A.A0 to R6C26A.F0 bin_to_bcd_uut/SLICE_1121 ROUTE 2 0.976 R6C26A.F0 to R6C26C.A1 bin_to_bcd_uut/n60668 CTOF_DEL --- 0.495 R6C26C.A1 to R6C26C.F1 bin_to_bcd_uut/SLICE_1352 ROUTE 9 4.056 R6C26C.F1 to R14C24B.A0 bin_to_bcd_uut/bcd_code_24__N_674 CTOF_DEL --- 0.495 R14C24B.A0 to R14C24B.F0 bin_to_bcd_uut/SLICE_1371 ROUTE 5 1.011 R14C24B.F0 to R15C24D.A0 bin_to_bcd_uut/bcd_code_24__N_669 CTOF_DEL --- 0.495 R15C24D.A0 to R15C24D.F0 bin_to_bcd_uut/SLICE_1320 ROUTE 4 0.718 R15C24D.F0 to R15C24B.B1 bin_to_bcd_uut/n60639 CTOF_DEL --- 0.495 R15C24B.B1 to R15C24B.F1 SLICE_417 ROUTE 3 0.987 R15C24B.F1 to R15C23D.A1 bin_to_bcd_uut/n60635 CTOF_DEL --- 0.495 R15C23D.A1 to R15C23D.F1 SLICE_414 ROUTE 6 0.787 R15C23D.F1 to R15C23B.C1 bin_to_bcd_uut/bcd_code_24__N_716 CTOF_DEL --- 0.495 R15C23B.C1 to R15C23B.F1 SLICE_401 ROUTE 3 1.040 R15C23B.F1 to R15C25C.B0 bin_to_bcd_uut/n60623 CTOF_DEL --- 0.495 R15C25C.B0 to R15C25C.F0 SLICE_404 ROUTE 2 1.023 R15C25C.F0 to R13C27C.M0 bcd_code_18 (to clk_c) -------- 79.570 (30.8% logic, 69.2% route), 50 logic levels. Clock Skew Details: Source Clock Path clk to DS18B20Z_uut/SLICE_1537: Name Fanout Delay (ns) Site Resource ROUTE 531 3.044 C1.PADDI to R12C25D.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_1541: Name Fanout Delay (ns) Site Resource ROUTE 531 3.044 C1.PADDI to R13C27C.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Warning: 0.468MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "clk_c_generated_8" 399.840000 MHz ; 4 items scored, 1 timing error detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 2.138ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/i23195 (from clk_c_generated_8 +) Destination: FF Data in control_module_uut/i23195 (to clk_c_generated_8 +) Delay: 3.906ns (36.9% logic, 63.1% route), 3 logic levels. Constraint Details: 3.906ns physical path delay control_module_uut/SLICE_608 to control_module_uut/SLICE_608 exceeds 2.501ns delay constraint less 0.000ns skew and 0.733ns LSRREC_SET requirement (totaling 1.768ns) by 2.138ns Physical Path Details: Data path control_module_uut/SLICE_608 to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R14C16B.CLK to R14C16B.Q0 control_module_uut/SLICE_608 (from clk_c_generated_8) ROUTE 2 0.630 R14C16B.Q0 to R14C15D.D1 n35352 CTOF_DEL --- 0.495 R14C15D.D1 to R14C15D.F1 OLED12832_uut/SLICE_1184 ROUTE 2 0.756 R14C15D.F1 to R14C15A.C1 n61061 CTOF_DEL --- 0.495 R14C15A.C1 to R14C15A.F1 control_module_uut/SLICE_1488 ROUTE 2 1.078 R14C15A.F1 to R14C16B.LSR control_module_uut/temp_out_31__N_1883 (to clk_c_generated_8) -------- 3.906 (36.9% logic, 63.1% route), 3 logic levels. Clock Skew Details: Source Clock Path SLICE_1525 to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource ROUTE 2 1.035 R15C16C.F0 to R14C16B.CLK clk_c_generated_8 -------- 1.035 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SLICE_1525 to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource ROUTE 2 1.035 R15C16C.F0 to R14C16B.CLK clk_c_generated_8 -------- 1.035 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.142ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/temp_out_i8_23196_23197_set (from clk_c +) Destination: FF Data in control_module_uut/i23195 (to clk_c_generated_8 +) Delay: 4.619ns (31.2% logic, 68.8% route), 3 logic levels. Constraint Details: 4.619ns physical path delay SLICE_609 to control_module_uut/SLICE_608 meets (delay constraint based on source clock period of 42.794ns and destination clock period of 2.501ns) 2.501ns delay constraint less -2.993ns skew and 0.733ns LSRREC_SET requirement (totaling 4.761ns) by 0.142ns Physical Path Details: Data path SLICE_609 to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R15C16B.CLK to R15C16B.Q0 SLICE_609 (from clk_c) ROUTE 2 1.343 R15C16B.Q0 to R14C15D.B1 n35353 CTOF_DEL --- 0.495 R14C15D.B1 to R14C15D.F1 OLED12832_uut/SLICE_1184 ROUTE 2 0.756 R14C15D.F1 to R14C15A.C1 n61061 CTOF_DEL --- 0.495 R14C15A.C1 to R14C15A.F1 control_module_uut/SLICE_1488 ROUTE 2 1.078 R14C15A.F1 to R14C16B.LSR control_module_uut/temp_out_31__N_1883 (to clk_c_generated_8) -------- 4.619 (31.2% logic, 68.8% route), 3 logic levels. Clock Skew Details: Source Clock Path clk to SLICE_609: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 531 3.044 C1.PADDI to R15C16B.CLK clk_c -------- 4.176 (27.1% logic, 72.9% route), 1 logic levels. Destination Clock Path clk to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 531 3.044 C1.PADDI to R15C16B.CLK clk_c REG_DEL --- 0.452 R15C16B.CLK to R15C16B.Q0 SLICE_609 ROUTE 2 1.011 R15C16B.Q0 to R15C16C.B0 n35353 CTOF_DEL --- 0.495 R15C16C.B0 to R15C16C.F0 SLICE_1525 ROUTE 2 1.035 R15C16C.F0 to R14C16B.CLK clk_c_generated_8 -------- 7.169 (29.0% logic, 71.0% route), 3 logic levels. Passed: The following path meets requirements by 0.511ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/temp_out_i8_23196_23197_reset (from clk_c +) Destination: FF Data in control_module_uut/i23195 (to clk_c_generated_8 +) Delay: 4.250ns (33.9% logic, 66.1% route), 3 logic levels. Constraint Details: 4.250ns physical path delay SLICE_1506 to control_module_uut/SLICE_608 meets (delay constraint based on source clock period of 42.794ns and destination clock period of 2.501ns) 2.501ns delay constraint less -2.993ns skew and 0.733ns LSRREC_SET requirement (totaling 4.761ns) by 0.511ns Physical Path Details: Data path SLICE_1506 to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R14C15B.CLK to R14C15B.Q0 SLICE_1506 (from clk_c) ROUTE 2 0.974 R14C15B.Q0 to R14C15D.A1 n35354 CTOF_DEL --- 0.495 R14C15D.A1 to R14C15D.F1 OLED12832_uut/SLICE_1184 ROUTE 2 0.756 R14C15D.F1 to R14C15A.C1 n61061 CTOF_DEL --- 0.495 R14C15A.C1 to R14C15A.F1 control_module_uut/SLICE_1488 ROUTE 2 1.078 R14C15A.F1 to R14C16B.LSR control_module_uut/temp_out_31__N_1883 (to clk_c_generated_8) -------- 4.250 (33.9% logic, 66.1% route), 3 logic levels. Clock Skew Details: Source Clock Path clk to SLICE_1506: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 531 3.044 C1.PADDI to R14C15B.CLK clk_c -------- 4.176 (27.1% logic, 72.9% route), 1 logic levels. Destination Clock Path clk to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 531 3.044 C1.PADDI to R15C16B.CLK clk_c REG_DEL --- 0.452 R15C16B.CLK to R15C16B.Q0 SLICE_609 ROUTE 2 1.011 R15C16B.Q0 to R15C16C.B0 n35353 CTOF_DEL --- 0.495 R15C16C.B0 to R15C16C.F0 SLICE_1525 ROUTE 2 1.035 R15C16C.F0 to R14C16B.CLK clk_c_generated_8 -------- 7.169 (29.0% logic, 71.0% route), 3 logic levels. Passed: The following path meets requirements by 1.692ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/tone_flag_330_rep_938 (from clk_c +) Destination: FF Data in control_module_uut/i23195 (to clk_c_generated_8 +) Delay: 3.069ns (30.9% logic, 69.1% route), 2 logic levels. Constraint Details: 3.069ns physical path delay SLICE_1207 to control_module_uut/SLICE_608 meets (delay constraint based on source clock period of 42.794ns and destination clock period of 2.501ns) 2.501ns delay constraint less -2.993ns skew and 0.733ns LSRREC_SET requirement (totaling 4.761ns) by 1.692ns Physical Path Details: Data path SLICE_1207 to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R14C15C.CLK to R14C15C.Q0 SLICE_1207 (from clk_c) ROUTE 68 1.044 R14C15C.Q0 to R14C15A.B1 n62436 CTOF_DEL --- 0.495 R14C15A.B1 to R14C15A.F1 control_module_uut/SLICE_1488 ROUTE 2 1.078 R14C15A.F1 to R14C16B.LSR control_module_uut/temp_out_31__N_1883 (to clk_c_generated_8) -------- 3.069 (30.9% logic, 69.1% route), 2 logic levels. Clock Skew Details: Source Clock Path clk to SLICE_1207: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 531 3.044 C1.PADDI to R14C15C.CLK clk_c -------- 4.176 (27.1% logic, 72.9% route), 1 logic levels. Destination Clock Path clk to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 531 3.044 C1.PADDI to R15C16B.CLK clk_c REG_DEL --- 0.452 R15C16B.CLK to R15C16B.Q0 SLICE_609 ROUTE 2 1.011 R15C16B.Q0 to R15C16C.B0 n35353 CTOF_DEL --- 0.495 R15C16C.B0 to R15C16C.F0 SLICE_1525 ROUTE 2 1.035 R15C16C.F0 to R14C16B.CLK clk_c_generated_8 -------- 7.169 (29.0% logic, 71.0% route), 3 logic levels. Warning: 215.564MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "clk_c" 23.368000 MHz ; | 23.368 MHz| 0.468 MHz| 6 * | | | FREQUENCY NET "clk_c_generated_8" | | | 399.840000 MHz ; | 399.840 MHz| 215.564 MHz| 3 * | | | ---------------------------------------------------------------------------- 2 preferences(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- bin_to_bcd_uut/n60668 | 2| 4093| 99.90% | | | bin_to_bcd_uut/n60771 | 5| 4093| 99.90% | | | bin_to_bcd_uut/n60765 | 2| 4093| 99.90% | | | bin_to_bcd_uut/bcd_code_24__N_674 | 9| 4093| 99.90% | | | bin_to_bcd_uut/n60639 | 4| 4093| 99.90% | | | bin_to_bcd_uut/bcd_code_24__N_669 | 5| 4093| 99.90% | | | bin_to_bcd_uut/n60743 | 2| 4093| 99.90% | | | bin_to_bcd_uut/n60736 | 4| 4093| 99.90% | | | bin_to_bcd_uut/bcd_code_24__N_490 | 9| 4093| 99.90% | | | bin_to_bcd_uut/n8120 | 4| 4093| 99.90% | | | bcd_code_24__N_344 | 9| 4093| 99.90% | | | n54691 | 1| 4093| 99.90% | | | temperature_code_5 | 2| 4093| 99.90% | | | temperature_code_10_N_1_5 | 4| 4093| 99.90% | | | n8116 | 9| 4092| 99.88% | | | bin_to_bcd_uut/n59905 | 2| 4050| 98.85% | | | bin_to_bcd_uut/n60712 | 5| 4024| 98.22% | | | bin_to_bcd_uut/bcd_code_24__N_572 | 9| 4024| 98.22% | | | bin_to_bcd_uut/n60704 | 2| 4024| 98.22% | | | bin_to_bcd_uut/bcd_code_24__N_527 | 5| 4024| 98.22% | | | n54606 | 1| 3947| 96.34% | | | n12047 | 1| 3771| 92.04% | | | n54711 | 1| 3771| 92.04% | | | n54712 | 1| 3735| 91.16% | | | bin_to_bcd_uut/bcd_code_24__N_623 | 10| 3586| 87.53% | | | bin_to_bcd_uut/n60685 | 2| 3586| 87.53% | | | bin_to_bcd_uut/n60794 | 5| 3483| 85.01% | | | bin_to_bcd_uut/n60623 | 3| 3344| 81.62% | | | bin_to_bcd_uut/n60635 | 3| 3344| 81.62% | | | n54707 | 1| 3287| 80.23% | | | bin_to_bcd_uut/bcd_code_24__N_716 | 6| 3284| 80.16% | | | n54605 | 1| 3214| 78.45% | | | bin_to_bcd_uut/n60848 | 4| 3196| 78.01% | | | bin_to_bcd_uut/n60844 | 3| 3138| 76.59% | | | n54706 | 1| 3045| 74.32% | | | bin_to_bcd_uut/n60834 | 3| 2736| 66.78% | | | bin_to_bcd_uut/bcd_code_24__N_407 | 9| 2736| 66.78% | | | bcd_code_18 | 2| 2378| 58.04% | | | bin_to_bcd_uut/n60805 | 4| 2341| 57.14% | | | bin_to_bcd_uut/n60800 | 3| 2341| 57.14% | | | n54709 | 1| 2332| 56.92% | | | bin_code_20 | 15| 2332| 56.92% | | | n54705 | 1| 2088| 50.96% | | | n54713 | 1| 1931| 47.13% | | | n54708 | 1| 1882| 45.94% | | | bin_to_bcd_uut/bcd_code_24__N_467 | 5| 1752| 42.76% | | | bin_to_bcd_uut/bcd_code_24__N_380 | 11| 1720| 41.98% | | | bin_to_bcd_uut/n60821 | 3| 1700| 41.49% | | | bin_code_17 | 12| 1509| 36.83% | | | n54604 | 1| 1503| 36.69% | | | data_out_0 | 5| 1503| 36.69% | | | bin_to_bcd_uut/bcd_code_24__N_472 | 9| 1449| 35.37% | | | bin_to_bcd_uut/n60825 | 4| 1438| 35.10% | | | bin_to_bcd_uut/n60839 | 6| 1418| 34.61% | | | bin_to_bcd_uut/n8128 | 4| 1357| 33.12% | | | bin_to_bcd_uut/n60816 | 5| 1357| 33.12% | | | bin_to_bcd_uut/n60811 | 3| 1357| 33.12% | | | bin_to_bcd_uut/n60827 | 3| 1298| 31.68% | | | n12102 | 1| 1182| 28.85% | | | data_out_1 | 5| 1048| 25.58% | | | n54714 | 1| 1040| 25.38% | | | bin_to_bcd_uut/bcd_code_24__N_429 | 5| 984| 24.02% | | | bcd_code_17 | 2| 966| 23.58% | | | n60837 | 6| 955| 23.31% | | | n26_adj_3237 | 4| 955| 23.31% | | | bin_to_bcd_uut/n60833 | 1| 942| 22.99% | | | bin_to_bcd_uut/bcd_code_24__N_434 | 9| 925| 22.58% | | | bin_to_bcd_uut/bcd_code_24__N_362 | 10| 862| 21.04% | | | n12101 | 1| 836| 20.41% | | | n12099 | 1| 810| 19.77% | | | n54715 | 1| 806| 19.67% | | | bin_to_bcd_uut/bcd_code_24__N_660 | 4| 749| 18.28% | | | bcd_code_23 | 3| 749| 18.28% | | | n12113 | 1| 702| 17.13% | | | n54716 | 1| 702| 17.13% | | | data_out_2 | 5| 663| 16.18% | | | bin_to_bcd_uut/bcd_code_24__N_463 | 10| 610| 14.89% | | | bin_to_bcd_uut/n8185 | 3| 568| 13.86% | | | bcd_code_24__N_367 | 5| 530| 12.94% | | | bin_to_bcd_uut/n60680 | 2| 507| 12.37% | | | bin_to_bcd_uut/n60674 | 5| 507| 12.37% | | | data_out_3 | 5| 460| 11.23% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 30 clocks: Clock Domain: control_module_uut/clk_c_generated_9 Source: SLICE_1525.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_7 Source: control_module_uut/SLICE_1440.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_6 Source: control_module_uut/SLICE_1444.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_5 Source: control_module_uut/SLICE_1441.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_4 Source: control_module_uut/SLICE_1442.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_3 Source: control_module_uut/SLICE_1445.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_28 Source: control_module_uut/SLICE_1446.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_27 Source: control_module_uut/SLICE_1447.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_26 Source: control_module_uut/SLICE_1434.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_25 Source: control_module_uut/SLICE_1532.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_24 Source: control_module_uut/SLICE_1533.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_23 Source: control_module_uut/SLICE_1534.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_22 Source: control_module_uut/SLICE_1534.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_21 Source: control_module_uut/SLICE_1435.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_20 Source: control_module_uut/SLICE_1436.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_19 Source: control_module_uut/SLICE_1437.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_18 Source: control_module_uut/SLICE_1533.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_17 Source: control_module_uut/SLICE_1532.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_16 Source: control_module_uut/SLICE_1531.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_15 Source: control_module_uut/SLICE_1530.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_14 Source: control_module_uut/SLICE_1438.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_13 Source: control_module_uut/SLICE_1439.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_12 Source: control_module_uut/SLICE_1443.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_11 Source: control_module_uut/SLICE_1527.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_10 Source: control_module_uut/SLICE_1527.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_1 Source: control_module_uut/SLICE_1433.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: clk_c_generated_8 Source: SLICE_1525.F0 Loads: 2 Covered under: FREQUENCY NET "clk_c_generated_8" 399.840000 MHz ; Data transfers from: Clock Domain: clk_c Source: clk.PAD Covered under: FREQUENCY NET "clk_c_generated_8" 399.840000 MHz ; Transfers: 3 Clock Domain: clk_c_generated_2 Source: SLICE_1431.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: clk_c Source: clk.PAD Loads: 531 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Data transfers from: Clock Domain: control_module_uut/clk_c_generated_9 Source: SLICE_1525.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_7 Source: control_module_uut/SLICE_1440.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_6 Source: control_module_uut/SLICE_1444.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_5 Source: control_module_uut/SLICE_1441.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_4 Source: control_module_uut/SLICE_1442.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_3 Source: control_module_uut/SLICE_1445.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_28 Source: control_module_uut/SLICE_1446.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_27 Source: control_module_uut/SLICE_1447.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_26 Source: control_module_uut/SLICE_1434.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_25 Source: control_module_uut/SLICE_1532.F0 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_24 Source: control_module_uut/SLICE_1533.F0 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_23 Source: control_module_uut/SLICE_1534.F0 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_22 Source: control_module_uut/SLICE_1534.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_21 Source: control_module_uut/SLICE_1435.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_20 Source: control_module_uut/SLICE_1436.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_19 Source: control_module_uut/SLICE_1437.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_18 Source: control_module_uut/SLICE_1533.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_17 Source: control_module_uut/SLICE_1532.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_16 Source: control_module_uut/SLICE_1531.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_15 Source: control_module_uut/SLICE_1530.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_14 Source: control_module_uut/SLICE_1438.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_13 Source: control_module_uut/SLICE_1439.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_12 Source: control_module_uut/SLICE_1443.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_11 Source: control_module_uut/SLICE_1527.F0 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_10 Source: control_module_uut/SLICE_1527.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_1 Source: control_module_uut/SLICE_1433.F0 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: clk_c_generated_8 Source: SLICE_1525.F0 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: clk_c_generated_2 Source: SLICE_1431.F0 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: DS18B20Z_uut/clk_1mhz Source: DS18B20Z_uut/SLICE_228.Q0 Loads: 11 No transfer within this clock domain is found Timing summary (Setup): --------------- Timing errors: 4097 Score: 154691890 Cumulative negative slack: 154691890 Constraints cover 2147483647 paths, 2 nets, and 12035 connections (97.96% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.11.0.396.4 Thu Feb 18 17:28:23 2021 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o step_project01_impl1.twr -gui -msgset C:/Users/CROFY/Documents/Diamond/Project/step_project01/promote.xml step_project01_impl1.ncd step_project01_impl1.prf Design file: step_project01_impl1.ncd Preference file: step_project01_impl1.prf Device,speed: LCMXO2-4000HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "clk_c" 23.368000 MHz (0 errors)
  • 4096 items scored, 0 timing errors detected.
  • FREQUENCY NET "clk_c_generated_8" 399.840000 MHz (3 errors)
  • 4 items scored, 3 timing errors detected. 28 potential circuit loops found in timing analysis. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "clk_c" 23.368000 MHz ; 4096 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q u1/Uart_Rx_uut/uart_rx0_46 (from clk_c +) Destination: FF Data in u1/Uart_Rx_uut/uart_rx1_47 (to clk_c +) Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: 0.285ns physical path delay SLICE_656 to SLICE_656 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path SLICE_656 to SLICE_656: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R16C13C.CLK to R16C13C.Q0 SLICE_656 (from clk_c) ROUTE 1 0.152 R16C13C.Q0 to R16C13C.M1 u1/Uart_Rx_uut/uart_rx0 (to clk_c) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to SLICE_656: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R16C13C.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_656: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R16C13C.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DS18B20Z_uut/temperature_buffer_i0_i1 (from clk_c +) Destination: FF Data in DS18B20Z_uut/temperature_i0_i1 (to clk_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_48 to SLICE_49 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_48 to SLICE_49: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R13C14B.CLK to R13C14B.Q0 SLICE_48 (from clk_c) ROUTE 2 0.154 R13C14B.Q0 to R13C14A.M1 DS18B20Z_uut/temperature_buffer_1 (to clk_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to SLICE_48: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R13C14B.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_49: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R13C14A.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/cnt_rxn_FSM_i0_i0 (from clk_c +) Destination: FF Data in control_module_uut/cnt_rxn_FSM_i0_i1 (to clk_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay control_module_uut/SLICE_1227 to control_module_uut/SLICE_1227 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path control_module_uut/SLICE_1227 to control_module_uut/SLICE_1227: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R3C22D.CLK to R3C22D.Q0 control_module_uut/SLICE_1227 (from clk_c) ROUTE 14 0.154 R3C22D.Q0 to R3C22D.M1 control_module_uut/n1118 (to clk_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to control_module_uut/SLICE_1227: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R3C22D.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to control_module_uut/SLICE_1227: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R3C22D.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/cnt_rxn_FSM_i0_i10 (from clk_c +) Destination: FF Data in control_module_uut/cnt_rxn_FSM_i0_i11 (to clk_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay control_module_uut/SLICE_1255 to control_module_uut/SLICE_1255 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path control_module_uut/SLICE_1255 to control_module_uut/SLICE_1255: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R15C10A.CLK to R15C10A.Q0 control_module_uut/SLICE_1255 (from clk_c) ROUTE 12 0.154 R15C10A.Q0 to R15C10A.M1 control_module_uut/n1108 (to clk_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to control_module_uut/SLICE_1255: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R15C10A.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to control_module_uut/SLICE_1255: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R15C10A.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/cnt_rxn_FSM_i0_i8 (from clk_c +) Destination: FF Data in control_module_uut/cnt_rxn_FSM_i0_i9 (to clk_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay control_module_uut/SLICE_1548 to control_module_uut/SLICE_1548 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path control_module_uut/SLICE_1548 to control_module_uut/SLICE_1548: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R15C11A.CLK to R15C11A.Q0 control_module_uut/SLICE_1548 (from clk_c) ROUTE 12 0.154 R15C11A.Q0 to R15C11A.M1 control_module_uut/n1110 (to clk_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to control_module_uut/SLICE_1548: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R15C11A.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to control_module_uut/SLICE_1548: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R15C11A.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.307ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/cnt_rxn_FSM_i0_i4 (from clk_c +) Destination: FF Data in control_module_uut/cnt_rxn_FSM_i0_i5 (to clk_c +) Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels. Constraint Details: 0.288ns physical path delay control_module_uut/SLICE_1278 to control_module_uut/SLICE_1278 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.307ns Physical Path Details: Data path control_module_uut/SLICE_1278 to control_module_uut/SLICE_1278: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R14C11B.CLK to R14C11B.Q0 control_module_uut/SLICE_1278 (from clk_c) ROUTE 13 0.155 R14C11B.Q0 to R14C11B.M1 control_module_uut/n1114 (to clk_c) -------- 0.288 (46.2% logic, 53.8% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to control_module_uut/SLICE_1278: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R14C11B.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to control_module_uut/SLICE_1278: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R14C11B.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.307ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/cnt_rxn_FSM_i0_i6 (from clk_c +) Destination: FF Data in control_module_uut/cnt_rxn_FSM_i0_i7 (to clk_c +) Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels. Constraint Details: 0.288ns physical path delay control_module_uut/SLICE_1550 to control_module_uut/SLICE_1550 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.307ns Physical Path Details: Data path control_module_uut/SLICE_1550 to control_module_uut/SLICE_1550: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R14C10A.CLK to R14C10A.Q0 control_module_uut/SLICE_1550 (from clk_c) ROUTE 13 0.155 R14C10A.Q0 to R14C10A.M1 control_module_uut/n1112 (to clk_c) -------- 0.288 (46.2% logic, 53.8% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to control_module_uut/SLICE_1550: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R14C10A.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to control_module_uut/SLICE_1550: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R14C10A.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.307ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/cnt_rxn_FSM_i0_i16 (from clk_c +) Destination: FF Data in control_module_uut/cnt_rxn_FSM_i0_i17 (to clk_c +) Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels. Constraint Details: 0.288ns physical path delay control_module_uut/SLICE_1260 to control_module_uut/SLICE_1260 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.307ns Physical Path Details: Data path control_module_uut/SLICE_1260 to control_module_uut/SLICE_1260: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R15C11B.CLK to R15C11B.Q0 control_module_uut/SLICE_1260 (from clk_c) ROUTE 14 0.155 R15C11B.Q0 to R15C11B.M1 control_module_uut/n1102 (to clk_c) -------- 0.288 (46.2% logic, 53.8% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to control_module_uut/SLICE_1260: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R15C11B.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to control_module_uut/SLICE_1260: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R15C11B.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.307ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/cnt_rxn_FSM_i0_i27 (from clk_c +) Destination: FF Data in control_module_uut/cnt_rxn_FSM_i0_i28 (to clk_c +) Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels. Constraint Details: 0.288ns physical path delay control_module_uut/SLICE_1451 to control_module_uut/SLICE_1451 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.307ns Physical Path Details: Data path control_module_uut/SLICE_1451 to control_module_uut/SLICE_1451: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R15C9C.CLK to R15C9C.Q0 control_module_uut/SLICE_1451 (from clk_c) ROUTE 14 0.155 R15C9C.Q0 to R15C9C.M1 control_module_uut/n1091 (to clk_c) -------- 0.288 (46.2% logic, 53.8% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to control_module_uut/SLICE_1451: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R15C9C.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to control_module_uut/SLICE_1451: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R15C9C.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.307ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/cnt_rxn_FSM_i0_i30 (from clk_c +) Destination: FF Data in control_module_uut/cnt_rxn_FSM_i0_i31 (to clk_c +) Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels. Constraint Details: 0.288ns physical path delay control_module_uut/SLICE_1452 to control_module_uut/SLICE_1452 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.307ns Physical Path Details: Data path control_module_uut/SLICE_1452 to control_module_uut/SLICE_1452: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R14C9D.CLK to R14C9D.Q0 control_module_uut/SLICE_1452 (from clk_c) ROUTE 12 0.155 R14C9D.Q0 to R14C9D.M1 control_module_uut/n1088 (to clk_c) -------- 0.288 (46.2% logic, 53.8% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to control_module_uut/SLICE_1452: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R14C9D.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to control_module_uut/SLICE_1452: Name Fanout Delay (ns) Site Resource ROUTE 531 1.116 C1.PADDI to R14C9D.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. ================================================================================ Preference: FREQUENCY NET "clk_c_generated_8" 399.840000 MHz ; 4 items scored, 3 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 1.944ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/tone_flag_330_rep_938 (from clk_c +) Destination: FF Data in control_module_uut/i23195 (to clk_c_generated_8 +) Delay: 0.725ns (32.3% logic, 67.7% route), 2 logic levels. Constraint Details: 0.725ns physical path delay SLICE_1207 to control_module_uut/SLICE_608 exceeds (delay constraint based on source clock period of 42.794ns and destination clock period of 2.501ns) 0.000ns LSRREC_HLD and 0.000ns delay constraint less -2.669ns skew requirement (totaling 2.669ns) by 1.944ns Physical Path Details: Data path SLICE_1207 to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R14C15C.CLK to R14C15C.Q0 SLICE_1207 (from clk_c) ROUTE 68 0.232 R14C15C.Q0 to R14C15A.B1 n62436 CTOF_DEL --- 0.101 R14C15A.B1 to R14C15A.F1 control_module_uut/SLICE_1488 ROUTE 2 0.259 R14C15A.F1 to R14C16B.LSR control_module_uut/temp_out_31__N_1883 (to clk_c_generated_8) -------- 0.725 (32.3% logic, 67.7% route), 2 logic levels. Clock Skew Details: Source Clock Path clk to SLICE_1207: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.449 C1.PAD to C1.PADDI clk ROUTE 531 1.116 C1.PADDI to R14C15C.CLK clk_c -------- 1.565 (28.7% logic, 71.3% route), 1 logic levels. Destination Clock Path clk to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.449 C1.PAD to C1.PADDI clk ROUTE 531 1.116 C1.PADDI to R14C15C.CLK clk_c REG_DEL --- 0.154 R14C15C.CLK to R14C15C.Q0 SLICE_1207 ROUTE 68 1.980 R14C15C.Q0 to R15C16C.A0 n62436 CTOF_DEL --- 0.177 R15C16C.A0 to R15C16C.F0 SLICE_1525 ROUTE 2 0.358 R15C16C.F0 to R14C16B.CLK clk_c_generated_8 -------- 4.234 (18.4% logic, 81.6% route), 3 logic levels. Error: The following path exceeds requirements by 1.725ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/temp_out_i8_23196_23197_reset (from clk_c +) Destination: FF Data in control_module_uut/i23195 (to clk_c_generated_8 +) Delay: 0.944ns (35.5% logic, 64.5% route), 3 logic levels. Constraint Details: 0.944ns physical path delay SLICE_1506 to control_module_uut/SLICE_608 exceeds (delay constraint based on source clock period of 42.794ns and destination clock period of 2.501ns) 0.000ns LSRREC_HLD and 0.000ns delay constraint less -2.669ns skew requirement (totaling 2.669ns) by 1.725ns Physical Path Details: Data path SLICE_1506 to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R14C15B.CLK to R14C15B.Q0 SLICE_1506 (from clk_c) ROUTE 2 0.212 R14C15B.Q0 to R14C15D.A1 n35354 CTOF_DEL --- 0.101 R14C15D.A1 to R14C15D.F1 OLED12832_uut/SLICE_1184 ROUTE 2 0.138 R14C15D.F1 to R14C15A.C1 n61061 CTOF_DEL --- 0.101 R14C15A.C1 to R14C15A.F1 control_module_uut/SLICE_1488 ROUTE 2 0.259 R14C15A.F1 to R14C16B.LSR control_module_uut/temp_out_31__N_1883 (to clk_c_generated_8) -------- 0.944 (35.5% logic, 64.5% route), 3 logic levels. Clock Skew Details: Source Clock Path clk to SLICE_1506: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.449 C1.PAD to C1.PADDI clk ROUTE 531 1.116 C1.PADDI to R14C15B.CLK clk_c -------- 1.565 (28.7% logic, 71.3% route), 1 logic levels. Destination Clock Path clk to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.449 C1.PAD to C1.PADDI clk ROUTE 531 1.116 C1.PADDI to R14C15C.CLK clk_c REG_DEL --- 0.154 R14C15C.CLK to R14C15C.Q0 SLICE_1207 ROUTE 68 1.980 R14C15C.Q0 to R15C16C.A0 n62436 CTOF_DEL --- 0.177 R15C16C.A0 to R15C16C.F0 SLICE_1525 ROUTE 2 0.358 R15C16C.F0 to R14C16B.CLK clk_c_generated_8 -------- 4.234 (18.4% logic, 81.6% route), 3 logic levels. Error: The following path exceeds requirements by 1.628ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/temp_out_i8_23196_23197_set (from clk_c +) Destination: FF Data in control_module_uut/i23195 (to clk_c_generated_8 +) Delay: 1.041ns (32.2% logic, 67.8% route), 3 logic levels. Constraint Details: 1.041ns physical path delay SLICE_609 to control_module_uut/SLICE_608 exceeds (delay constraint based on source clock period of 42.794ns and destination clock period of 2.501ns) 0.000ns LSRREC_HLD and 0.000ns delay constraint less -2.669ns skew requirement (totaling 2.669ns) by 1.628ns Physical Path Details: Data path SLICE_609 to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R15C16B.CLK to R15C16B.Q0 SLICE_609 (from clk_c) ROUTE 2 0.309 R15C16B.Q0 to R14C15D.B1 n35353 CTOF_DEL --- 0.101 R14C15D.B1 to R14C15D.F1 OLED12832_uut/SLICE_1184 ROUTE 2 0.138 R14C15D.F1 to R14C15A.C1 n61061 CTOF_DEL --- 0.101 R14C15A.C1 to R14C15A.F1 control_module_uut/SLICE_1488 ROUTE 2 0.259 R14C15A.F1 to R14C16B.LSR control_module_uut/temp_out_31__N_1883 (to clk_c_generated_8) -------- 1.041 (32.2% logic, 67.8% route), 3 logic levels. Clock Skew Details: Source Clock Path clk to SLICE_609: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.449 C1.PAD to C1.PADDI clk ROUTE 531 1.116 C1.PADDI to R15C16B.CLK clk_c -------- 1.565 (28.7% logic, 71.3% route), 1 logic levels. Destination Clock Path clk to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.449 C1.PAD to C1.PADDI clk ROUTE 531 1.116 C1.PADDI to R14C15C.CLK clk_c REG_DEL --- 0.154 R14C15C.CLK to R14C15C.Q0 SLICE_1207 ROUTE 68 1.980 R14C15C.Q0 to R15C16C.A0 n62436 CTOF_DEL --- 0.177 R15C16C.A0 to R15C16C.F0 SLICE_1525 ROUTE 2 0.358 R15C16C.F0 to R14C16B.CLK clk_c_generated_8 -------- 4.234 (18.4% logic, 81.6% route), 3 logic levels. Passed: The following path meets requirements by 0.868ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_module_uut/i23195 (from clk_c_generated_8 +) Destination: FF Data in control_module_uut/i23195 (to clk_c_generated_8 +) Delay: 0.868ns (38.6% logic, 61.4% route), 3 logic levels. Constraint Details: 0.868ns physical path delay control_module_uut/SLICE_608 to control_module_uut/SLICE_608 meets 0.000ns LSRREC_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.000ns) by 0.868ns Physical Path Details: Data path control_module_uut/SLICE_608 to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R14C16B.CLK to R14C16B.Q0 control_module_uut/SLICE_608 (from clk_c_generated_8) ROUTE 2 0.136 R14C16B.Q0 to R14C15D.D1 n35352 CTOF_DEL --- 0.101 R14C15D.D1 to R14C15D.F1 OLED12832_uut/SLICE_1184 ROUTE 2 0.138 R14C15D.F1 to R14C15A.C1 n61061 CTOF_DEL --- 0.101 R14C15A.C1 to R14C15A.F1 control_module_uut/SLICE_1488 ROUTE 2 0.259 R14C15A.F1 to R14C16B.LSR control_module_uut/temp_out_31__N_1883 (to clk_c_generated_8) -------- 0.868 (38.6% logic, 61.4% route), 3 logic levels. Clock Skew Details: Source Clock Path SLICE_1525 to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource ROUTE 2 0.358 R15C16C.F0 to R14C16B.CLK clk_c_generated_8 -------- 0.358 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SLICE_1525 to control_module_uut/SLICE_608: Name Fanout Delay (ns) Site Resource ROUTE 2 0.358 R15C16C.F0 to R14C16B.CLK clk_c_generated_8 -------- 0.358 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "clk_c" 23.368000 MHz ; | 0.000 ns| 0.304 ns| 1 | | | FREQUENCY NET "clk_c_generated_8" | | | 399.840000 MHz ; | 0.000 ns| -1.944 ns| 2 * | | | ---------------------------------------------------------------------------- 1 preference(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- control_module_uut/temp_out_31__N_1883 | 2| 3| 100.00% | | | n61061 | 2| 2| 66.67% | | | n62436 | 68| 1| 33.33% | | | n35353 | 2| 1| 33.33% | | | n35354 | 2| 1| 33.33% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 30 clocks: Clock Domain: control_module_uut/clk_c_generated_9 Source: SLICE_1525.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_7 Source: control_module_uut/SLICE_1440.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_6 Source: control_module_uut/SLICE_1444.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_5 Source: control_module_uut/SLICE_1441.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_4 Source: control_module_uut/SLICE_1442.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_3 Source: control_module_uut/SLICE_1445.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_28 Source: control_module_uut/SLICE_1446.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_27 Source: control_module_uut/SLICE_1447.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_26 Source: control_module_uut/SLICE_1434.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_25 Source: control_module_uut/SLICE_1532.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_24 Source: control_module_uut/SLICE_1533.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_23 Source: control_module_uut/SLICE_1534.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_22 Source: control_module_uut/SLICE_1534.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_21 Source: control_module_uut/SLICE_1435.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_20 Source: control_module_uut/SLICE_1436.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_19 Source: control_module_uut/SLICE_1437.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_18 Source: control_module_uut/SLICE_1533.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_17 Source: control_module_uut/SLICE_1532.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_16 Source: control_module_uut/SLICE_1531.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_15 Source: control_module_uut/SLICE_1530.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_14 Source: control_module_uut/SLICE_1438.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_13 Source: control_module_uut/SLICE_1439.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_12 Source: control_module_uut/SLICE_1443.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_11 Source: control_module_uut/SLICE_1527.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_10 Source: control_module_uut/SLICE_1527.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_module_uut/clk_c_generated_1 Source: control_module_uut/SLICE_1433.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: clk_c_generated_8 Source: SLICE_1525.F0 Loads: 2 Covered under: FREQUENCY NET "clk_c_generated_8" 399.840000 MHz ; Data transfers from: Clock Domain: clk_c Source: clk.PAD Covered under: FREQUENCY NET "clk_c_generated_8" 399.840000 MHz ; Transfers: 3 Clock Domain: clk_c_generated_2 Source: SLICE_1431.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: clk_c Source: clk.PAD Loads: 531 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Data transfers from: Clock Domain: control_module_uut/clk_c_generated_9 Source: SLICE_1525.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_7 Source: control_module_uut/SLICE_1440.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_6 Source: control_module_uut/SLICE_1444.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_5 Source: control_module_uut/SLICE_1441.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_4 Source: control_module_uut/SLICE_1442.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_3 Source: control_module_uut/SLICE_1445.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_28 Source: control_module_uut/SLICE_1446.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_27 Source: control_module_uut/SLICE_1447.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_26 Source: control_module_uut/SLICE_1434.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_25 Source: control_module_uut/SLICE_1532.F0 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_24 Source: control_module_uut/SLICE_1533.F0 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_23 Source: control_module_uut/SLICE_1534.F0 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_22 Source: control_module_uut/SLICE_1534.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_21 Source: control_module_uut/SLICE_1435.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_20 Source: control_module_uut/SLICE_1436.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_19 Source: control_module_uut/SLICE_1437.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_18 Source: control_module_uut/SLICE_1533.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_17 Source: control_module_uut/SLICE_1532.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_16 Source: control_module_uut/SLICE_1531.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_15 Source: control_module_uut/SLICE_1530.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_14 Source: control_module_uut/SLICE_1438.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_13 Source: control_module_uut/SLICE_1439.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_12 Source: control_module_uut/SLICE_1443.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_11 Source: control_module_uut/SLICE_1527.F0 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_10 Source: control_module_uut/SLICE_1527.F1 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: control_module_uut/clk_c_generated_1 Source: control_module_uut/SLICE_1433.F0 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: clk_c_generated_8 Source: SLICE_1525.F0 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: clk_c_generated_2 Source: SLICE_1431.F0 Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1 Clock Domain: DS18B20Z_uut/clk_1mhz Source: DS18B20Z_uut/SLICE_228.Q0 Loads: 11 No transfer within this clock domain is found Timing summary (Hold): --------------- Timing errors: 3 Score: 5297 Cumulative negative slack: 5297 Constraints cover 2147483647 paths, 2 nets, and 12035 connections (97.96% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 4097 (setup), 3 (hold) Score: 154691890 (setup), 5297 (hold) Cumulative negative slack: 154697187 (154691890+5297) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------