#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr  1 2019
#install: C:\lscc\diamond\3.11_x64\synpbase
#OS: Windows 8 6.2
#Hostname: COMPUTERYT

# Mon Feb 15 12:42:39 2021

#Implementation: impl1


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2

Hostname: COMPUTERYT

Implementation : impl1
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43

@N: :  | Running in 64-bit mode 

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2

Hostname: COMPUTERYT

Implementation : impl1
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43

@N: :  | Running in 64-bit mode 
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Users\CROFY\Documents\Diamond\Project\step_project01\impl1\source\OLED12832.v" (library work)
@I::"C:\Users\CROFY\Documents\Diamond\Project\step_project01\impl1\source\DS18B20Z.v" (library work)
@I::"C:\Users\CROFY\Documents\Diamond\Project\step_project01\impl1\source\bin_to_bcd.v" (library work)
@I::"C:\Users\CROFY\Documents\Diamond\Project\step_project01\control_module.v" (library work)
@I::"C:\Users\CROFY\Documents\Diamond\Project\step_project01\step_project01.v" (library work)
@W:CG1249 : step_project01.v(84) | Redeclaration of implicit signal time_oled
@W:CG1249 : step_project01.v(85) | Redeclaration of implicit signal temp_oled
@I::"C:\Users\CROFY\Documents\Diamond\Project\step_project01\impl1\source\Uart_Tx.v" (library work)
@I::"C:\Users\CROFY\Documents\Diamond\Project\step_project01\impl1\source\Uart_Rx.v" (library work)
@I::"C:\Users\CROFY\Documents\Diamond\Project\step_project01\impl1\source\Baud.v" (library work)
@I::"C:\Users\CROFY\Documents\Diamond\Project\step_project01\impl1\source\Uart_Bus.v" (library work)
Verilog syntax check successful!
Selecting top level module step_project01
@N:CG364 : DS18B20Z.v(18) | Synthesizing module DS18B20Z in library work.
Running optimization stage 1 on DS18B20Z .......
@A:CL282 : DS18B20Z.v(61) | Feedback mux created for signal temperature_buffer[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : DS18B20Z.v(61) | Feedback mux created for signal num_delay[19:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : DS18B20Z.v(61) | Feedback mux created for signal data_wr_buffer[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : DS18B20Z.v(61) | Feedback mux created for signal data_wr[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : DS18B20Z.v(61) | Feedback mux created for signal data_out[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@N:CL189 : DS18B20Z.v(61) | Register bit data_wr[0] is always 0.
@N:CL189 : DS18B20Z.v(61) | Register bit data_wr[2] is always 1.
@N:CL189 : DS18B20Z.v(61) | Register bit num_delay[9] is always 0.
@N:CL189 : DS18B20Z.v(61) | Register bit num_delay[10] is always 0.
@N:CL189 : DS18B20Z.v(61) | Register bit num_delay[11] is always 0.
@N:CL189 : DS18B20Z.v(61) | Register bit num_delay[15] is always 0.
@N:CL189 : DS18B20Z.v(61) | Register bit num_delay[18] is always 0.
@W:CL260 : DS18B20Z.v(61) | Pruning register bit 18 of num_delay[19:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : DS18B20Z.v(61) | Pruning register bit 15 of num_delay[19:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : DS18B20Z.v(61) | Pruning register bits 11 to 9 of num_delay[19:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : DS18B20Z.v(61) | Pruning register bit 2 of data_wr[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : DS18B20Z.v(61) | Pruning register bit 0 of data_wr[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N:CG364 : bin_to_bcd.v(18) | Synthesizing module bin_to_bcd in library work.
Running optimization stage 1 on bin_to_bcd .......
@N:CG364 : OLED12832.v(18) | Synthesizing module OLED12832 in library work.
Running optimization stage 1 on OLED12832 .......
@W:CL265 : OLED12832.v(47) | Removing unused bit 167 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 159 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 151 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 143 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 135 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 127 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 119 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 111 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 103 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 95 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 87 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 79 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 71 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 63 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 55 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 47 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 39 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 31 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 23 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 15 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : OLED12832.v(47) | Removing unused bit 7 of char[167:0]. Either assign all bits or reduce the width of the signal.
@W:CL190 : OLED12832.v(47) | Optimizing register bit x_ph[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit x_ph[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit x_ph[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit x_ph[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit x_pl[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit x_pl[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit x_pl[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit x_pl[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit x_pl[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit x_pl[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit x_pl[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit x_pl[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit y_p[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit y_p[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit y_p[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[40] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[41] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[42] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[43] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[44] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[46] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[48] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[49] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[50] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[51] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[52] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[54] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[56] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[57] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[58] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[59] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[60] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[62] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[64] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[65] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[66] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[67] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[68] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[70] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[72] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[73] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[74] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[75] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[76] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[78] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[80] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[81] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[82] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[83] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[84] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[86] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[88] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[89] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[90] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[91] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[92] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[94] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[97] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[99] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[105] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[108] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[113] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[116] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[120] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[121] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[123] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[128] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[129] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[130] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[131] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[132] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[133] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[134] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[136] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[137] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[138] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[139] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[140] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[141] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[142] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[144] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[145] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[146] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[147] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[148] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[149] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[150] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[152] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[153] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[154] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[155] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[156] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[157] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[158] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[160] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[161] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[162] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : OLED12832.v(47) | Optimizing register bit char[163] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.

Only the first 100 messages of id 'CL190' are reported. To see all messages use 'report_messages -log C:\Users\CROFY\Documents\Diamond\Project\step_project01\impl1\synlog\step_project01_impl1_compiler.srr -id CL190' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL190} -count unlimited' in the Tcl shell.
@N:CL189 : OLED12832.v(162) | Register bit cmd[0][0] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[0][1] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[0][2] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[0][3] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[0][4] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[0][5] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[0][6] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[0][7] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[1][0] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[1][1] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[1][2] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[1][3] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[1][4] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[1][5] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[1][6] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[1][7] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[2][0] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[2][1] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[2][2] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[2][3] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[2][4] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[2][5] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[2][6] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[2][7] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[3][0] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[3][1] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[3][2] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[3][3] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[3][4] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[3][5] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[3][6] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[3][7] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[4][0] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[4][1] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[4][2] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[4][3] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[4][4] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[4][5] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[4][6] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[4][7] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[5][0] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[5][1] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[5][2] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[5][3] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[5][4] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[5][5] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[5][6] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[5][7] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[6][0] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[6][1] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[6][2] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[6][3] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[6][4] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[6][5] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[6][6] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[6][7] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[7][0] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[7][1] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[7][2] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[7][3] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[7][4] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[7][5] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[7][6] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[7][7] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[8][0] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[8][1] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[8][2] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[8][3] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[8][4] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[8][5] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[8][6] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[8][7] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[9][0] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[9][1] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[9][2] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[9][3] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[9][4] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[9][5] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[9][6] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[9][7] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[10][0] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[10][1] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[10][2] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[10][3] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[10][4] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[10][5] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[10][6] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[10][7] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[11][0] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[11][1] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[11][2] is always 0.
@N:CL189 : OLED12832.v(162) | Register bit cmd[11][3] is always 1.
@N:CL189 : OLED12832.v(162) | Register bit cmd[11][4] is always 0.

Only the first 100 messages of id 'CL189' are reported. To see all messages use 'report_messages -log C:\Users\CROFY\Documents\Diamond\Project\step_project01\impl1\synlog\step_project01_impl1_compiler.srr -id CL189' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL189} -count unlimited' in the Tcl shell.
@W:CL260 : OLED12832.v(47) | Pruning register bit 22 of char[22:16]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 16 of char[22:16]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 46 of char[46:40]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : OLED12832.v(47) | Pruning register bits 44 to 40 of char[46:40]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 54 of char[54:48]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : OLED12832.v(47) | Pruning register bits 52 to 48 of char[54:48]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 62 of char[62:56]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : OLED12832.v(47) | Pruning register bits 60 to 56 of char[62:56]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 70 of char[70:64]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : OLED12832.v(47) | Pruning register bits 68 to 64 of char[70:64]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 78 of char[78:72]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : OLED12832.v(47) | Pruning register bits 76 to 72 of char[78:72]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 86 of char[86:80]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : OLED12832.v(47) | Pruning register bits 84 to 80 of char[86:80]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 94 of char[94:88]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : OLED12832.v(47) | Pruning register bits 92 to 88 of char[94:88]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 99 of char[102:96]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 97 of char[102:96]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 108 of char[110:104]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 105 of char[110:104]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 116 of char[118:112]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 113 of char[118:112]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 123 of char[126:120]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : OLED12832.v(47) | Pruning register bits 121 to 120 of char[126:120]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL169 : OLED12832.v(47) | Pruning unused register char[134:128]. Make sure that there are no unused intermediate registers.
@W:CL169 : OLED12832.v(47) | Pruning unused register char[142:136]. Make sure that there are no unused intermediate registers.
@W:CL169 : OLED12832.v(47) | Pruning unused register char[150:144]. Make sure that there are no unused intermediate registers.
@W:CL169 : OLED12832.v(47) | Pruning unused register char[158:152]. Make sure that there are no unused intermediate registers.
@W:CL169 : OLED12832.v(47) | Pruning unused register char[166:160]. Make sure that there are no unused intermediate registers.
@W:CL279 : OLED12832.v(47) | Pruning register bits 7 to 5 of x_ph[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 3 of x_ph[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 6 of y_p[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : OLED12832.v(47) | Pruning register bits 3 to 2 of y_p[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL169 : OLED12832.v(47) | Pruning unused register x_pl[7:0]. Make sure that there are no unused intermediate registers.
@N:CG364 : Baud.v(18) | Synthesizing module Baud in library work.

	BPS_PARA=32'b00000000000000000000010011100010
   Generated name = Baud_1250s
Running optimization stage 1 on Baud_1250s .......
@N:CG364 : Uart_Rx.v(18) | Synthesizing module Uart_Rx in library work.
@N:CG179 : Uart_Rx.v(80) | Removing redundant assignment.
Running optimization stage 1 on Uart_Rx .......
@N:CG364 : Uart_Tx.v(18) | Synthesizing module Uart_Tx in library work.
Running optimization stage 1 on Uart_Tx .......
@W:CL260 : Uart_Tx.v(34) | Pruning register bit 0 of tx_data_r[9:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N:CG364 : Uart_Bus.v(18) | Synthesizing module Uart_Bus in library work.
Running optimization stage 1 on Uart_Bus .......
@N:CG364 : control_module.v(1) | Synthesizing module control_module in library work.
@N:CG179 : control_module.v(36) | Removing redundant assignment.
@N:CG179 : control_module.v(37) | Removing redundant assignment.
@N:CG179 : control_module.v(87) | Removing redundant assignment.
@N:CG179 : control_module.v(87) | Removing redundant assignment.
Running optimization stage 1 on control_module .......
@A:CL282 : control_module.v(66) | Feedback mux created for signal cnt_tx. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 0 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 1 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 2 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 3 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 4 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 5 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 6 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 7 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 12 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 13 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 14 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 15 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 20 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 21 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 22 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 23 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 28 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 29 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 30 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL208 : control_module.v(44) | All reachable assignments to bit 31 of temp_out[31:0] assign 0, register removed by optimization.
@W:CL113 : control_module.v(21) | Feedback mux created for signal time_out[31:28]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL113 : control_module.v(21) | Feedback mux created for signal time_out[23:20]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL113 : control_module.v(21) | Feedback mux created for signal time_out[15:12]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL113 : control_module.v(21) | Feedback mux created for signal time_out[7:4]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL250 : control_module.v(21) | All reachable assignments to time_out[31:28] assign 0, register removed by optimization
@W:CL250 : control_module.v(21) | All reachable assignments to time_out[23:20] assign 0, register removed by optimization
@W:CL250 : control_module.v(21) | All reachable assignments to time_out[15:12] assign 0, register removed by optimization
@W:CL250 : control_module.v(21) | All reachable assignments to time_out[7:4] assign 0, register removed by optimization
@N:CG364 : step_project01.v(1) | Synthesizing module step_project01 in library work.
Running optimization stage 1 on step_project01 .......
Running optimization stage 2 on step_project01 .......
Running optimization stage 2 on control_module .......
@N:CL159 : control_module.v(5) | Input sw is unused.
Running optimization stage 2 on Uart_Bus .......
Running optimization stage 2 on Uart_Tx .......
Running optimization stage 2 on Uart_Rx .......
Running optimization stage 2 on Baud_1250s .......
@W:CL279 : Baud.v(31) | Pruning register bits 12 to 11 of cnt[12:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Running optimization stage 2 on OLED12832 .......
@W:CL279 : OLED12832.v(47) | Pruning register bits 15 to 5 of cnt[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 4 of cnt_main[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N:CL201 : OLED12832.v(47) | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 6 reachable states with original encodings of:
   000001
   000010
   000100
   001000
   010000
   100000
@N:CL201 : OLED12832.v(47) | Trying to extract state machine for register cnt_init.
Extracted state machine for register cnt_init
State machine has 6 reachable states with original encodings of:
   00000
   00001
   00010
   00011
   00100
   00101
@W:CL260 : OLED12832.v(47) | Pruning register bit 19 of char[21:17]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 2 of x_ph[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 5 of y_p[5:4]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 107 of char[107:106]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : OLED12832.v(47) | Pruning register bit 126 of char[126:124]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL247 : OLED12832.v(23) | Input port bit 31 of tim[31:0] is unused

@W:CL247 : OLED12832.v(23) | Input port bit 23 of tim[31:0] is unused

@W:CL247 : OLED12832.v(23) | Input port bit 15 of tim[31:0] is unused

@W:CL247 : OLED12832.v(23) | Input port bit 7 of tim[31:0] is unused

@W:CL247 : OLED12832.v(24) | Input port bit 31 of tem[31:0] is unused

@W:CL247 : OLED12832.v(24) | Input port bit 23 of tem[31:0] is unused

@W:CL247 : OLED12832.v(24) | Input port bit 15 of tem[31:0] is unused

@W:CL247 : OLED12832.v(24) | Input port bit 7 of tem[31:0] is unused

@A:CL153 : OLED12832.v(39) | *Unassigned bits of mem[16][39:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : OLED12832.v(39) | *Unassigned bits of mem[17][39:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : OLED12832.v(39) | *Unassigned bits of mem[18][39:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : OLED12832.v(39) | *Unassigned bits of mem[19][39:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : OLED12832.v(39) | *Unassigned bits of mem[20][39:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : OLED12832.v(39) | *Unassigned bits of mem[21][39:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : OLED12832.v(39) | *Unassigned bits of mem[22][39:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : OLED12832.v(39) | *Unassigned bits of mem[23][39:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : OLED12832.v(39) | *Unassigned bits of mem[24][39:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : OLED12832.v(39) | *Unassigned bits of mem[25][39:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : OLED12832.v(39) | *Unassigned bits of mem[26][39:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : OLED12832.v(39) | *Unassigned bits of mem[27][39:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : OLED12832.v(39) | *Unassigned bits of mem[28][39:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : OLED12832.v(39) | *Unassigned bits of mem[29][39:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : OLED12832.v(39) | *Unassigned bits of mem[30][39:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : OLED12832.v(39) | *Unassigned bits of mem[31][39:0] are referenced and tied to 0 -- simulation mismatch possible.
Running optimization stage 2 on bin_to_bcd .......
Running optimization stage 2 on DS18B20Z .......
@W:CL260 : DS18B20Z.v(61) | Pruning register bit 2 of data_wr_buffer[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : DS18B20Z.v(61) | Pruning register bit 0 of data_wr_buffer[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N:CL201 : DS18B20Z.v(61) | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 8 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
   111
@W:CL249 : DS18B20Z.v(61) | Initial value is not supported on state machine state
@W:CL260 : DS18B20Z.v(61) | Pruning register bit 8 of num_delay[8:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : DS18B20Z.v(61) | Pruning register bits 14 to 13 of num_delay[14:12]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : DS18B20Z.v(61) | Pruning register bit 17 of num_delay[17:16]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : DS18B20Z.v(61) | Pruning register bit 7 of data_wr[7:3]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : DS18B20Z.v(61) | Pruning register bit 5 of data_wr[7:3]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : DS18B20Z.v(61) | Pruning register bit 7 of data_wr_buffer[7:3]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : DS18B20Z.v(61) | Pruning register bit 5 of data_wr_buffer[7:3]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 90MB peak: 102MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime

Process completed successfully.
# Mon Feb 15 12:42:42 2021

###########################################################]

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2

Hostname: COMPUTERYT

Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43

@N: :  | Running in 64-bit mode 
File C:\Users\CROFY\Documents\Diamond\Project\step_project01\impl1\synwork\layer0.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Feb 15 12:42:43 2021

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File:  step_project01_impl1_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime

Process completed successfully.
# Mon Feb 15 12:42:43 2021

###########################################################]



Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2

Hostname: COMPUTERYT

Database state : C:\Users\CROFY\Documents\Diamond\Project\step_project01\impl1\synwork\|impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43

@N: :  | Running in 64-bit mode 
File C:\Users\CROFY\Documents\Diamond\Project\step_project01\impl1\synwork\step_project01_impl1_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Feb 15 12:42:44 2021

###########################################################]


# Mon Feb 15 12:42:44 2021


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2

Hostname: COMPUTERYT

Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr  3 2019 09:51:54


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A:MF827 :  | No constraint file specified. 
@N:MF284 :  | Setting synthesis effort to medium for the design 
Linked File:  step_project01_impl1_scck.rpt
Printing clock  summary report in "C:\Users\CROFY\Documents\Diamond\Project\step_project01\impl1\step_project01_impl1_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
@W:BN132 : ds18b20z.v(61) | Removing sequential instance DS18B20Z_uut.num_delay[16] because it is equivalent to instance DS18B20Z_uut.num_delay[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing sequential instance OLED12832_uut.y_p[7] because it is equivalent to instance OLED12832_uut.y_p[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing sequential instance OLED12832_uut.x_ph[4] because it is equivalent to instance OLED12832_uut.y_p[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing sequential instance OLED12832_uut.char[98] because it is equivalent to instance OLED12832_uut.char[96]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing sequential instance OLED12832_uut.char[122] because it is equivalent to instance OLED12832_uut.char[112]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing sequential instance OLED12832_uut.char[112] because it is equivalent to instance OLED12832_uut.char[106]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing sequential instance OLED12832_uut.char[106] because it is equivalent to instance OLED12832_uut.char[104]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing sequential instance OLED12832_uut.char[93] because it is equivalent to instance OLED12832_uut.char[85]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing sequential instance OLED12832_uut.char[85] because it is equivalent to instance OLED12832_uut.char[77]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing sequential instance OLED12832_uut.char[77] because it is equivalent to instance OLED12832_uut.char[69]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing sequential instance OLED12832_uut.char[69] because it is equivalent to instance OLED12832_uut.char[61]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing sequential instance OLED12832_uut.char[61] because it is equivalent to instance OLED12832_uut.char[53]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing sequential instance OLED12832_uut.char[53] because it is equivalent to instance OLED12832_uut.char[45]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing sequential instance OLED12832_uut.char[118:117] because it is equivalent to instance OLED12832_uut.char[110:109]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
Encoding state machine state[7:0] (in view: work.DS18B20Z(verilog))
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
Encoding state machine cnt_init[5:0] (in view: work.OLED12832(verilog))
original code -> new code
   00000 -> 000001
   00001 -> 000010
   00010 -> 000100
   00011 -> 001000
   00100 -> 010000
   00101 -> 100000
Encoding state machine state[5:0] (in view: work.OLED12832(verilog))
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
@N:MF578 :  | Incompatible asynchronous control logic preventing generated clock conversion. 
syn_allowed_resources : blockrams=10  set on top level netlist step_project01

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)



Clock Summary
******************

          Start                                 Requested     Requested     Clock                                 Clock                   Clock
Level     Clock                                 Frequency     Period        Type                                  Group                   Load 
-----------------------------------------------------------------------------------------------------------------------------------------------
0 -       step_project01|clk                    200.0 MHz     5.000         inferred                              Inferred_clkgroup_0     270  
1 .         DS18B20Z|clk_1mhz_derived_clock     200.0 MHz     5.000         derived (from step_project01|clk)     Inferred_clkgroup_0     110  
===============================================================================================================================================



Clock Load Summary
***********************

                                    Clock     Source                                Clock Pin                              Non-clock Pin     Non-clock Pin
Clock                               Load      Pin                                   Seq Example                            Seq Example       Comb Example 
----------------------------------------------------------------------------------------------------------------------------------------------------------
step_project01|clk                  270       clk(port)                             control_module_uut.cnt_rx.C            -                 -            
DS18B20Z|clk_1mhz_derived_clock     110       DS18B20Z_uut.clk_1mhz.Q[0](dffre)     DS18B20Z_uut.data_wr_buffer[4:3].C     -                 -            
==========================================================================================================================================================

@W:MT529 : ds18b20z.v(36) | Found inferred clock step_project01|clk which controls 270 sequential elements including DS18B20Z_uut.cnt_1mhz[2:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 270 clock pin(s) of sequential element(s)
1 gated/generated clock tree(s) driving 110 clock pin(s) of sequential element(s)
0 instances converted, 110 sequential instances remain driven by gated/generated clocks

================================== Non-Gated/Non-Generated Clocks ==================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance             
----------------------------------------------------------------------------------------------------
ClockId_0_0       clk                 Unconstrained_port     270        control_module_uut.cnt[23:0]
====================================================================================================
===================================================================== Gated/Generated Clocks ======================================================================
Clock Tree ID     Driving Element                Drive Element Type     Unconverted Fanout     Sample Instance           Explanation                               
-------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId_0_1       DS18B20Z_uut.clk_1mhz.Q[0]     dffre                  110                    DS18B20Z_uut.state[7]     Derived clock on input (not legal for GCC)
===================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 145MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Feb 15 12:42:45 2021

###########################################################]


# Mon Feb 15 12:42:45 2021


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2

Hostname: COMPUTERYT

Implementation : impl1
Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr  3 2019 09:51:54


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)


Available hyper_sources - for debug and ip models
	None Found

@W:FA239 : oled12832.v(95) | ROM char_reg_2[7:0] (in view: work.OLED12832(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W:FA239 : oled12832.v(95) | ROM char_reg_2[7:0] (in view: work.OLED12832(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N:MO106 : oled12832.v(95) | Found ROM char_reg_2[7:0] (in view: work.OLED12832(verilog)) with 25 words by 8 bits.
@N:FX493 :  | Applying initial value "000" on instance DS18B20Z_uut.state_back[2:0]. 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)

@W:BN132 : ds18b20z.v(61) | Removing instance DS18B20Z_uut.data_wr[4] because it is equivalent to instance DS18B20Z_uut.data_wr[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ds18b20z.v(61) | Removing instance DS18B20Z_uut.data_wr_buffer[4] because it is equivalent to instance DS18B20Z_uut.data_wr_buffer[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:MO231 : ds18b20z.v(61) | Found counter in view:work.DS18B20Z(verilog) instance cnt_read[5:0] 
@N:MO231 : ds18b20z.v(61) | Found counter in view:work.DS18B20Z(verilog) instance cnt_delay[19:0] 
@N:MO231 : ds18b20z.v(61) | Found counter in view:work.DS18B20Z(verilog) instance cnt_write[5:0] 
@N:MO231 : ds18b20z.v(61) | Found counter in view:work.DS18B20Z(verilog) instance cnt_main[3:0] 
@W:BN132 : ds18b20z.v(61) | Removing instance DS18B20Z_uut.num_delay[19] because it is equivalent to instance DS18B20Z_uut.num_delay[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.num_delay[14] because it is equivalent to instance OLED12832_uut.num_delay[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.num_delay[8] because it is equivalent to instance OLED12832_uut.num_delay[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.num_delay[7] because it is equivalent to instance OLED12832_uut.num_delay[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.num_delay[5] because it is equivalent to instance OLED12832_uut.num_delay[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.num_delay[3] because it is equivalent to instance OLED12832_uut.num_delay[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.char[14] because it is equivalent to instance OLED12832_uut.char[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.char[30] because it is equivalent to instance OLED12832_uut.char[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.char[28] because it is equivalent to instance OLED12832_uut.char[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.char[38] because it is equivalent to instance OLED12832_uut.char[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.char[36] because it is equivalent to instance OLED12832_uut.char[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.char[6] because it is equivalent to instance OLED12832_uut.char[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.char[4] because it is equivalent to instance OLED12832_uut.char[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.char[17] because it is equivalent to instance OLED12832_uut.x_ph[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.char[115] because it is equivalent to instance OLED12832_uut.char[96]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.char[114] because it is equivalent to instance OLED12832_uut.char[100]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.char[104] because it is equivalent to instance OLED12832_uut.char[102]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.char[110] because it is equivalent to instance OLED12832_uut.char[102]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.char[124] because it is equivalent to instance OLED12832_uut.char[102]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.char[109] because it is equivalent to instance OLED12832_uut.char[101]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.char[125] because it is equivalent to instance OLED12832_uut.char[101]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.state_back[5] because it is equivalent to instance OLED12832_uut.state_back[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.num_delay[15] because it is equivalent to instance OLED12832_uut.num_delay[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.num_delay[12] because it is equivalent to instance OLED12832_uut.num_delay[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.num_delay[11] because it is equivalent to instance OLED12832_uut.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.num_delay[9] because it is equivalent to instance OLED12832_uut.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.num_delay[6] because it is equivalent to instance OLED12832_uut.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.num_delay[4] because it is equivalent to instance OLED12832_uut.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.num_delay[1] because it is equivalent to instance OLED12832_uut.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.num_delay[2] because it is equivalent to instance OLED12832_uut.num_delay[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:MO231 : oled12832.v(47) | Found counter in view:work.OLED12832(verilog) instance num[7:0] 
@N:MO231 : oled12832.v(47) | Found counter in view:work.OLED12832(verilog) instance cnt_scan[4:0] 
@N:MO231 : oled12832.v(47) | Found counter in view:work.OLED12832(verilog) instance cnt[4:0] 
@N:MO231 : oled12832.v(47) | Found counter in view:work.OLED12832(verilog) instance cnt_delay[15:0] 
@N:MO231 : oled12832.v(47) | Found counter in view:work.OLED12832(verilog) instance cnt_write[4:0] 
@N:MO231 : oled12832.v(47) | Found counter in view:work.OLED12832(verilog) instance cnt_main[3:0] 
@N:BN362 : oled12832.v(47) | Removing sequential instance char[12] (in view: work.OLED12832(verilog)) because it does not drive other instances.
@N:BN362 : oled12832.v(47) | Removing sequential instance state_back[4] (in view: work.OLED12832(verilog)) because it does not drive other instances.
@N:BN362 : oled12832.v(47) | Removing sequential instance num_delay[10] (in view: work.OLED12832(verilog)) because it does not drive other instances.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.char[37] because it is equivalent to instance OLED12832_uut.char[29]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : oled12832.v(47) | Removing instance OLED12832_uut.char[29] because it is equivalent to instance OLED12832_uut.char[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:MO231 : baud.v(31) | Found counter in view:work.Baud_1250s(verilog) instance cnt[10:0] 
@N:MO231 : uart_tx.v(47) | Found counter in view:work.Uart_Tx(verilog) instance num[3:0] 

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 148MB peak: 149MB)


Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 184MB peak: 191MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 160MB peak: 191MB)

@N:FA113 : uart_tx.v(55) | Pipelining module un1_num_2. For more information, search for "pipelining" in Online Help.
@N:MF169 : uart_tx.v(47) | Pushed in register num[3:0].
@N:MF169 : uart_tx.v(34) | Pushed in register tx_data_r[9:1].
@N:MF169 : control_module.v(66) | Pushed in register tx_data_out[7:0].
@N:MF169 : control_module.v(66) | Pushed in register cnt_tx.

Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 191MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 192MB peak: 192MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 191MB peak: 192MB)


Finished preparing to map (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 190MB peak: 192MB)


Finished technology mapping (Real Time elapsed 0h:04m:55s; CPU Time elapsed 0h:04m:54s; Memory used current: 213MB peak: 245MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:04m:54s		   -56.59ns		1309 /       348
   2		0h:04m:55s		   -56.57ns		1282 /       348
   3		0h:04m:55s		   -54.73ns		1283 /       348
   4		0h:04m:55s		   -54.73ns		1282 /       348
   5		0h:04m:55s		   -54.73ns		1282 /       348
@N:FX271 : ds18b20z.v(61) | Replicating instance DS18B20Z_uut.data_out[0] (in view: work.step_project01(verilog)) with 7 loads 1 time to improve timing.
@N:FX271 :  | Replicating instance bin_to_bcd_uut.g0 (in view: work.step_project01(verilog)) with 2 loads 1 time(s) to improve timing. 
@N:FX271 : bin_to_bcd.v(31) | Replicating instance bin_to_bcd_uut.bcd_code[20] (in view: work.step_project01(verilog)) with 2 loads 1 time(s) to improve timing.
@N:FX271 : bin_to_bcd.v(31) | Replicating instance bin_to_bcd_uut.bcd_code[13] (in view: work.step_project01(verilog)) with 2 loads 1 time(s) to improve timing.
@N:FX271 :  | Replicating instance bin_to_bcd_uut.bcd_m3 (in view: work.step_project01(verilog)) with 2 loads 1 time(s) to improve timing. 
Timing driven replication report
Added 1 Registers via timing driven replication
Added 4 LUTs via timing driven replication

   6		0h:04m:56s		   -54.16ns		1286 /       349
   7		0h:04m:56s		   -53.74ns		1291 /       349
   8		0h:04m:56s		   -52.11ns		1292 /       349
   9		0h:04m:56s		   -52.67ns		1295 /       349
  10		0h:04m:56s		   -49.56ns		1314 /       349
  11		0h:04m:56s		   -49.56ns		1317 /       349
  12		0h:04m:56s		   -49.56ns		1317 /       349
  13		0h:04m:56s		   -49.56ns		1320 /       349
  14		0h:04m:56s		   -49.56ns		1321 /       349


  15		0h:04m:56s		   -47.75ns		1320 /       349
  16		0h:04m:57s		   -47.09ns		1323 /       349
  17		0h:04m:57s		   -46.91ns		1327 /       349
  18		0h:04m:57s		   -46.46ns		1328 /       349
  19		0h:04m:57s		   -45.73ns		1330 /       349
  20		0h:04m:57s		   -45.34ns		1331 /       349
  21		0h:04m:57s		   -44.06ns		1343 /       349
  22		0h:04m:57s		   -44.06ns		1343 /       349
  23		0h:04m:57s		   -44.06ns		1344 /       349

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:04m:58s; CPU Time elapsed 0h:04m:57s; Memory used current: 222MB peak: 245MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Warning: Forcing use of GSR for flip-flops and
latches that do not specify sets or resets
   DS18B20Z_uut.data_out[15] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_out[14] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_out[13] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_out[12] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_out[11] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_out[10] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_out[9] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_out[8] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_out[7] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_out[6] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_out[5] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_out[4] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_out[3] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_out[2] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_out[1] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_out_fast[0] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_out[0] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_wr_buffer[6] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_wr[6] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_wr_buffer[3] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_wr[3] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_wr[1] (in view: work.step_project01(verilog))
   DS18B20Z_uut.data_wr_buffer[1] (in view: work.step_project01(verilog))
   DS18B20Z_uut.num_delay[12] (in view: work.step_project01(verilog))
   DS18B20Z_uut.num_delay[7] (in view: work.step_project01(verilog))
   DS18B20Z_uut.num_delay[6] (in view: work.step_project01(verilog))
   DS18B20Z_uut.num_delay[5] (in view: work.step_project01(verilog))
   DS18B20Z_uut.num_delay[4] (in view: work.step_project01(verilog))
   DS18B20Z_uut.num_delay[3] (in view: work.step_project01(verilog))
   DS18B20Z_uut.num_delay[2] (in view: work.step_project01(verilog))
   DS18B20Z_uut.num_delay[1] (in view: work.step_project01(verilog))
   DS18B20Z_uut.num_delay[0] (in view: work.step_project01(verilog))
   DS18B20Z_uut.temperature_buffer[7] (in view: work.step_project01(verilog))
   DS18B20Z_uut.temperature_buffer[6] (in view: work.step_project01(verilog))
   DS18B20Z_uut.temperature_buffer[5] (in view: work.step_project01(verilog))
   DS18B20Z_uut.temperature_buffer[4] (in view: work.step_project01(verilog))
   DS18B20Z_uut.temperature_buffer[3] (in view: work.step_project01(verilog))
   DS18B20Z_uut.temperature_buffer[2] (in view: work.step_project01(verilog))
   DS18B20Z_uut.temperature_buffer[1] (in view: work.step_project01(verilog))
   DS18B20Z_uut.temperature_buffer[0] (in view: work.step_project01(verilog))
   control_module_uut.cnt_tx (in view: work.step_project01(verilog))
   u1.Uart_Rx_uut.uart_rx0 (in view: work.step_project01(verilog))
   u1.Uart_Rx_uut.uart_rx1 (in view: work.step_project01(verilog))
   u1.Uart_Rx_uut.uart_rx2 (in view: work.step_project01(verilog))


Finished restoring hierarchy (Real Time elapsed 0h:04m:58s; CPU Time elapsed 0h:04m:58s; Memory used current: 222MB peak: 245MB)


Start Writing Netlists (Real Time elapsed 0h:04m:58s; CPU Time elapsed 0h:04m:58s; Memory used current: 182MB peak: 245MB)

Writing Analyst data base C:\Users\CROFY\Documents\Diamond\Project\step_project01\impl1\synwork\step_project01_impl1_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:04m:58s; CPU Time elapsed 0h:04m:58s; Memory used current: 222MB peak: 245MB)

Writing EDIF Netlist and constraint files
@N:FX1056 :  | Writing EDF file: C:\Users\CROFY\Documents\Diamond\Project\step_project01\impl1\step_project01_impl1.edi 
N-2018.03L-SP1-1
@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:04m:59s; CPU Time elapsed 0h:04m:59s; Memory used current: 227MB peak: 245MB)


Start final timing analysis (Real Time elapsed 0h:04m:59s; CPU Time elapsed 0h:04m:59s; Memory used current: 220MB peak: 245MB)

@W:MT420 :  | Found inferred clock step_project01|clk with period 5.00ns. Please declare a user-defined clock on port clk. 
@N:MT615 :  | Found clock DS18B20Z|clk_1mhz_derived_clock with period 5.00ns  


##### START OF TIMING REPORT #####[
# Timing Report written on Mon Feb 15 12:47:45 2021
#


Top view:               step_project01
Requested Frequency:    200.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -45.818

                                    Requested     Estimated     Requested     Estimated                 Clock                                 Clock              
Starting Clock                      Frequency     Frequency     Period        Period        Slack       Type                                  Group              
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
DS18B20Z|clk_1mhz_derived_clock     200.0 MHz     19.7 MHz      5.000         50.818        -45.818     derived (from step_project01|clk)     Inferred_clkgroup_0
step_project01|clk                  200.0 MHz     19.7 MHz      5.000         50.818        -7.920      inferred                              Inferred_clkgroup_0
System                              200.0 MHz     NA            5.000         NA            NA          system                                system_clkgroup    
=================================================================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform





Clock Relationships
*******************

Clocks                                                            |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                         Ending                           |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------------------------------------
step_project01|clk               step_project01|clk               |  5.000       -7.920   |  No paths    -      |  No paths    -      |  No paths    -    
DS18B20Z|clk_1mhz_derived_clock  step_project01|clk               |  5.000       -45.818  |  No paths    -      |  No paths    -      |  No paths    -    
DS18B20Z|clk_1mhz_derived_clock  DS18B20Z|clk_1mhz_derived_clock  |  5.000       -1.412   |  No paths    -      |  No paths    -      |  No paths    -    
==========================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: DS18B20Z|clk_1mhz_derived_clock
====================================



Starting Points with Worst Slack
********************************

                                  Starting                                                                     Arrival            
Instance                          Reference                           Type        Pin     Net                  Time        Slack  
                                  Clock                                                                                           
----------------------------------------------------------------------------------------------------------------------------------
DS18B20Z_uut.data_out_fast[0]     DS18B20Z|clk_1mhz_derived_clock     FD1P3AX     Q       data_out_fast[0]     0.972       -45.818
DS18B20Z_uut.data_out[1]          DS18B20Z|clk_1mhz_derived_clock     FD1P3AX     Q       data_out[1]          1.044       -45.747
DS18B20Z_uut.data_out[2]          DS18B20Z|clk_1mhz_derived_clock     FD1P3AX     Q       data_out[2]          1.044       -45.747
DS18B20Z_uut.data_out[4]          DS18B20Z|clk_1mhz_derived_clock     FD1P3AX     Q       data_out[4]          1.108       -45.668
DS18B20Z_uut.data_out[3]          DS18B20Z|clk_1mhz_derived_clock     FD1P3AX     Q       data_out[3]          1.044       -45.604
DS18B20Z_uut.data_out[5]          DS18B20Z|clk_1mhz_derived_clock     FD1P3AX     Q       data_out[5]          1.044       -45.461
DS18B20Z_uut.data_out[6]          DS18B20Z|clk_1mhz_derived_clock     FD1P3AX     Q       data_out[6]          1.044       -45.461
DS18B20Z_uut.data_out[8]          DS18B20Z|clk_1mhz_derived_clock     FD1P3AX     Q       data_out[8]          1.108       -45.240
DS18B20Z_uut.data_out[7]          DS18B20Z|clk_1mhz_derived_clock     FD1P3AX     Q       data_out[7]          1.044       -45.176
DS18B20Z_uut.data_out[10]         DS18B20Z|clk_1mhz_derived_clock     FD1P3AX     Q       data_out[10]         1.108       -43.924
==================================================================================================================================


Ending Points with Worst Slack
******************************

                                          Starting                                                                     Required            
Instance                                  Reference                           Type        Pin     Net                  Time         Slack  
                                          Clock                                                                                            
-------------------------------------------------------------------------------------------------------------------------------------------
control_module_uut.temp_out_1[18]         DS18B20Z|clk_1mhz_derived_clock     FD1S3AX     D       bcd_code_14_rep1     4.894        -45.818
control_module_uut.tx_data_out_pipe_4     DS18B20Z|clk_1mhz_derived_clock     FD1P3AX     D       bcd_code[14]         4.894        -45.818
control_module_uut.tx_data_out[2]         DS18B20Z|clk_1mhz_derived_clock     FD1P3AX     D       tx_data_out_8[2]     5.462        -45.768
control_module_uut.temp_out_1[22]         DS18B20Z|clk_1mhz_derived_clock     FD1S3AX     D       bcd_code[18]         4.894        -45.554
control_module_uut.temp_out_1[23]         DS18B20Z|clk_1mhz_derived_clock     FD1S3AX     D       bcd_code[19]         4.894        -45.554
control_module_uut.temp_out_1[24]         DS18B20Z|clk_1mhz_derived_clock     FD1S3AX     D       bcd_code_20_rep1     4.894        -45.554
control_module_uut.tx_data_out_pipe_9     DS18B20Z|clk_1mhz_derived_clock     FD1P3AX     D       bcd_code[20]         4.894        -45.554
control_module_uut.tx_data_out[3]         DS18B20Z|clk_1mhz_derived_clock     FD1P3AX     D       tx_data_out_8[3]     5.462        -45.450
control_module_uut.temp_out_1[17]         DS18B20Z|clk_1mhz_derived_clock     FD1S3AX     D       bcd_code_13_rep1     4.894        -44.801
control_module_uut.temp_out_1[19]         DS18B20Z|clk_1mhz_derived_clock     FD1S3AX     D       bcd_code_15_rep1     4.894        -44.801
===========================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      5.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.894

    - Propagation time:                      50.712
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -45.818

    Number of logic level(s):                48
    Starting point:                          DS18B20Z_uut.data_out_fast[0] / Q
    Ending point:                            control_module_uut.tx_data_out_pipe_4 / D
    The start point is clocked by            DS18B20Z|clk_1mhz_derived_clock [rising] on pin CK
    The end   point is clocked by            step_project01|clk [rising] on pin CK

Instance / Net                                                    Pin      Pin               Arrival     No. of    
Name                                                 Type         Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
DS18B20Z_uut.data_out_fast[0]                        FD1P3AX      Q        Out     0.972     0.972       -         
data_out_fast[0]                                     Net          -        -       -         -           1         
temperature_code_0_cry_0_0                           CCU2D        A1       In      0.000     0.972       -         
temperature_code_0_cry_0_0                           CCU2D        COUT     Out     1.544     2.516       -         
temperature_code_0_cry_0                             Net          -        -       -         -           1         
temperature_code_0_cry_1_0                           CCU2D        CIN      In      0.000     2.516       -         
temperature_code_0_cry_1_0                           CCU2D        COUT     Out     0.143     2.659       -         
temperature_code_0_cry_2                             Net          -        -       -         -           1         
temperature_code_0_cry_3_0                           CCU2D        CIN      In      0.000     2.659       -         
temperature_code_0_cry_3_0                           CCU2D        COUT     Out     0.143     2.802       -         
temperature_code_0_cry_4                             Net          -        -       -         -           1         
temperature_code_0_cry_5_0                           CCU2D        CIN      In      0.000     2.802       -         
temperature_code_0_cry_5_0                           CCU2D        COUT     Out     0.143     2.945       -         
temperature_code_0_cry_6                             Net          -        -       -         -           1         
temperature_code_0_cry_7_0                           CCU2D        CIN      In      0.000     2.945       -         
temperature_code_0_cry_7_0                           CCU2D        S0       Out     1.549     4.494       -         
temperature_code_0_cry_7_0_S0                        Net          -        -       -         -           1         
temperature_code_0_cry_7_0_RNIRO9B1                  ORCALUT4     A        In      0.000     4.494       -         
temperature_code_0_cry_7_0_RNIRO9B1                  ORCALUT4     Z        Out     1.225     5.718       -         
bin_code_0_5                                         Net          -        -       -         -           5         
bin_code_0_5_cry_3_0                                 CCU2D        A1       In      0.000     5.718       -         
bin_code_0_5_cry_3_0                                 CCU2D        COUT     Out     1.544     7.263       -         
bin_code_0_5_cry_3                                   Net          -        -       -         -           1         
bin_code_0_5_cry_4_0                                 CCU2D        CIN      In      0.000     7.263       -         
bin_code_0_5_cry_4_0                                 CCU2D        S0       Out     1.549     8.812       -         
bin_code_0_5[8]                                      Net          -        -       -         -           1         
bin_code_0_cry_7_0                                   CCU2D        B1       In      0.000     8.812       -         
bin_code_0_cry_7_0                                   CCU2D        COUT     Out     1.544     10.357      -         
bin_code_0_cry_8                                     Net          -        -       -         -           1         
bin_code_0_cry_9_0                                   CCU2D        CIN      In      0.000     10.357      -         
bin_code_0_cry_9_0                                   CCU2D        COUT     Out     0.143     10.499      -         
bin_code_0_cry_10                                    Net          -        -       -         -           1         
bin_code_0_cry_11_0                                  CCU2D        CIN      In      0.000     10.499      -         
bin_code_0_cry_11_0                                  CCU2D        COUT     Out     0.143     10.642      -         
bin_code_0_cry_12                                    Net          -        -       -         -           1         
bin_code_0_cry_13_0                                  CCU2D        CIN      In      0.000     10.642      -         
bin_code_0_cry_13_0                                  CCU2D        COUT     Out     0.143     10.785      -         
bin_code_0_cry_14                                    Net          -        -       -         -           1         
bin_code_0_cry_15_0                                  CCU2D        CIN      In      0.000     10.785      -         
bin_code_0_cry_15_0                                  CCU2D        COUT     Out     0.143     10.928      -         
bin_code_0_cry_16                                    Net          -        -       -         -           1         
bin_code_0_cry_17_0                                  CCU2D        CIN      In      0.000     10.928      -         
bin_code_0_cry_17_0                                  CCU2D        S1       Out     0.981     11.909      -         
bin_code[18]                                         Net          -        -       -         -           12        
bin_to_bcd_uut.shift_reg_0_0_0_1[23]                 ORCALUT4     C        In      0.000     11.909      -         
bin_to_bcd_uut.shift_reg_0_0_0_1[23]                 ORCALUT4     Z        Out     1.017     12.925      -         
shift_reg_0_0_0_1[23]                                Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_0_0_0[23]                   ORCALUT4     D        In      0.000     12.925      -         
bin_to_bcd_uut.shift_reg_0_0_0[23]                   ORCALUT4     Z        Out     1.017     13.942      -         
shift_reg_0_0[23]                                    Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_16_a1_0_RNIO9803[23]        ORCALUT4     A        In      0.000     13.942      -         
bin_to_bcd_uut.shift_reg_16_a1_0_RNIO9803[23]        ORCALUT4     Z        Out     1.233     15.175      -         
shift_reg_16[23]                                     Net          -        -       -         -           6         
bin_to_bcd_uut.shift_reg_16_mb_RNIUSU06[22]          ORCALUT4     C        In      0.000     15.175      -         
bin_to_bcd_uut.shift_reg_16_mb_RNIUSU06[22]          ORCALUT4     Z        Out     1.017     16.192      -         
shift_reg_16_mb_RNIUSU06[22]                         Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_16_mb_RNITKI1B[22]          PFUMX        C0       In      0.000     16.192      -         
bin_to_bcd_uut.shift_reg_16_mb_RNITKI1B[22]          PFUMX        Z        Out     1.129     17.321      -         
shift_reg_20[22]                                     Net          -        -       -         -           6         
bin_to_bcd_uut.shift_reg_20_i_RNI927CH[21]           ORCALUT4     D        In      0.000     17.321      -         
bin_to_bcd_uut.shift_reg_20_i_RNI927CH[21]           ORCALUT4     Z        Out     1.277     18.598      -         
N_200                                                Net          -        -       -         -           10        
bin_to_bcd_uut.shift_reg_20_i_RNI4M9S91[21]          ORCALUT4     B        In      0.000     18.598      -         
bin_to_bcd_uut.shift_reg_20_i_RNI4M9S91[21]          ORCALUT4     Z        Out     1.017     19.614      -         
shift_reg_20_i_RNI4M9S91[21]                         Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_20_i_RNINLFD62[21]          ORCALUT4     B        In      0.000     19.614      -         
bin_to_bcd_uut.shift_reg_20_i_RNINLFD62[21]          ORCALUT4     Z        Out     1.297     20.911      -         
shift_reg_20_i_RNINLFD62[21]                         Net          -        -       -         -           13        
bin_to_bcd_uut.shift_reg_54_i_o3_N_3L3_RNI6RFFO2     ORCALUT4     A        In      0.000     20.911      -         
bin_to_bcd_uut.shift_reg_54_i_o3_N_3L3_RNI6RFFO2     ORCALUT4     Z        Out     1.017     21.928      -         
shift_reg_54_i_o3_N_3L3_RNI6RFFO2                    Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_34_N_2L1_RNIVG34H5          ORCALUT4     D        In      0.000     21.928      -         
bin_to_bcd_uut.shift_reg_34_N_2L1_RNIVG34H5          ORCALUT4     Z        Out     1.249     23.177      -         
N_184                                                Net          -        -       -         -           7         
bin_to_bcd_uut.shift_reg_41[22]                      ORCALUT4     C        In      0.000     23.177      -         
bin_to_bcd_uut.shift_reg_41[22]                      ORCALUT4     Z        Out     1.193     24.370      -         
shift_reg_41[22]                                     Net          -        -       -         -           4         
bin_to_bcd_uut.shift_reg_41_RNI2UKG1_0[22]           ORCALUT4     C        In      0.000     24.370      -         
bin_to_bcd_uut.shift_reg_41_RNI2UKG1_0[22]           ORCALUT4     Z        Out     1.017     25.387      -         
SUM1_30_3_N_4L6_sx                                   Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_54_i_0_RNIJUB71A[26]        ORCALUT4     B        In      0.000     25.387      -         
bin_to_bcd_uut.shift_reg_54_i_0_RNIJUB71A[26]        ORCALUT4     Z        Out     1.017     26.403      -         
shift_reg_54_i_0_RNIJUB71A[26]                       Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_54_i_0_RNIHD22E21[26]       ORCALUT4     D        In      0.000     26.403      -         
bin_to_bcd_uut.shift_reg_54_i_0_RNIHD22E21[26]       ORCALUT4     Z        Out     1.017     27.420      -         
shift_reg_54_i_0_RNIHD22E21[26]                      Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_44_RNIGNFC6N1[27]           ORCALUT4     C        In      0.000     27.420      -         
bin_to_bcd_uut.shift_reg_44_RNIGNFC6N1[27]           ORCALUT4     Z        Out     1.249     28.669      -         
shift_reg_44_RNIGNFC6N1[27]                          Net          -        -       -         -           7         
bin_to_bcd_uut.shift_reg_57_RNIFVFH2K2[32]           ORCALUT4     A        In      0.000     28.669      -         
bin_to_bcd_uut.shift_reg_57_RNIFVFH2K2[32]           ORCALUT4     Z        Out     1.153     29.822      -         
CO1_37                                               Net          -        -       -         -           3         
bin_to_bcd_uut.shift_reg_57_RNIFO62VG3[31]           ORCALUT4     A        In      0.000     29.822      -         
bin_to_bcd_uut.shift_reg_57_RNIFO62VG3[31]           ORCALUT4     Z        Out     1.273     31.095      -         
shift_reg_57_RNIFO62VG3[31]                          Net          -        -       -         -           9         
bin_to_bcd_uut.shift_reg_77[31]                      ORCALUT4     C        In      0.000     31.095      -         
bin_to_bcd_uut.shift_reg_77[31]                      ORCALUT4     Z        Out     1.193     32.287      -         
shift_reg_77[31]                                     Net          -        -       -         -           4         
bin_to_bcd_uut.shift_reg_77_RNI8FFGAB2[31]           ORCALUT4     C        In      0.000     32.287      -         
bin_to_bcd_uut.shift_reg_77_RNI8FFGAB2[31]           ORCALUT4     Z        Out     1.225     33.512      -         
CO2_31                                               Net          -        -       -         -           5         
bin_to_bcd_uut.shift_reg_77_RNIDAGITV1[32]           ORCALUT4     A        In      0.000     33.512      -         
bin_to_bcd_uut.shift_reg_77_RNIDAGITV1[32]           ORCALUT4     Z        Out     1.225     34.737      -         
CO1_30                                               Net          -        -       -         -           5         
bin_to_bcd_uut.shift_reg_93_RNI06PKK32[36]           ORCALUT4     A        In      0.000     34.737      -         
bin_to_bcd_uut.shift_reg_93_RNI06PKK32[36]           ORCALUT4     Z        Out     1.249     35.986      -         
N_128                                                Net          -        -       -         -           7         
bin_to_bcd_uut.shift_reg_106[35]                     ORCALUT4     C        In      0.000     35.986      -         
bin_to_bcd_uut.shift_reg_106[35]                     ORCALUT4     Z        Out     1.225     37.211      -         
shift_reg_106[35]                                    Net          -        -       -         -           5         
bin_to_bcd_uut.shift_reg_106_i_RNIPKB5UK1[34]        ORCALUT4     C        In      0.000     37.211      -         
bin_to_bcd_uut.shift_reg_106_i_RNIPKB5UK1[34]        ORCALUT4     Z        Out     1.233     38.443      -         
CO2_24                                               Net          -        -       -         -           6         
bin_to_bcd_uut.shift_reg_119_i_o3[34]                ORCALUT4     B        In      0.000     38.443      -         
bin_to_bcd_uut.shift_reg_119_i_o3[34]                ORCALUT4     Z        Out     1.277     39.720      -         
N_112                                                Net          -        -       -         -           10        
bin_to_bcd_uut.shift_reg_106_i_RNI4TQ8UK1[34]        ORCALUT4     B        In      0.000     39.720      -         
bin_to_bcd_uut.shift_reg_106_i_RNI4TQ8UK1[34]        ORCALUT4     Z        Out     1.153     40.873      -         
shift_reg_119[36]                                    Net          -        -       -         -           3         
bin_to_bcd_uut.shift_reg_135[36]                     ORCALUT4     C        In      0.000     40.873      -         
bin_to_bcd_uut.shift_reg_135[36]                     ORCALUT4     Z        Out     1.193     42.066      -         
shift_reg_135[36]                                    Net          -        -       -         -           4         
bin_to_bcd_uut.shift_reg_135_RNI3S467T2[36]          ORCALUT4     D        In      0.000     42.066      -         
bin_to_bcd_uut.shift_reg_135_RNI3S467T2[36]          ORCALUT4     Z        Out     1.017     43.083      -         
g0_5_1                                               Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_135_i_RNIN10V56[34]         ORCALUT4     B        In      0.000     43.083      -         
bin_to_bcd_uut.shift_reg_135_i_RNIN10V56[34]         ORCALUT4     Z        Out     1.193     44.275      -         
shift_reg_151[35]                                    Net          -        -       -         -           4         
bin_to_bcd_uut.shift_reg_151_i_RNIKDGFA6[34]         ORCALUT4     A        In      0.000     44.275      -         
bin_to_bcd_uut.shift_reg_151_i_RNIKDGFA6[34]         ORCALUT4     Z        Out     1.233     45.508      -         
CO2_10                                               Net          -        -       -         -           6         
bin_to_bcd_uut.shift_reg_151_i_RNI86NAB1[34]         ORCALUT4     A        In      0.000     45.508      -         
bin_to_bcd_uut.shift_reg_151_i_RNI86NAB1[34]         ORCALUT4     Z        Out     1.225     46.733      -         
shift_reg_167[35]                                    Net          -        -       -         -           5         
bin_to_bcd_uut.shift_reg_167_i_RNIQO65L1_0[34]       ORCALUT4     C        In      0.000     46.733      -         
bin_to_bcd_uut.shift_reg_167_i_RNIQO65L1_0[34]       ORCALUT4     Z        Out     1.249     47.982      -         
N_32                                                 Net          -        -       -         -           7         
bin_to_bcd_uut.shift_reg_151_i_RNI22FM7H1[34]        ORCALUT4     A        In      0.000     47.982      -         
bin_to_bcd_uut.shift_reg_151_i_RNI22FM7H1[34]        ORCALUT4     Z        Out     1.265     49.246      -         
shift_reg_186[35]                                    Net          -        -       -         -           8         
bin_to_bcd_uut.shift_reg_186_RNI29H0TK1[36]          ORCALUT4     C        In      0.000     49.246      -         
bin_to_bcd_uut.shift_reg_186_RNI29H0TK1[36]          ORCALUT4     Z        Out     1.017     50.263      -         
g0_1_2                                               Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_186_i_RNIIVHDNN1[34]        ORCALUT4     B        In      0.000     50.263      -         
bin_to_bcd_uut.shift_reg_186_i_RNIIVHDNN1[34]        ORCALUT4     Z        Out     0.449     50.712      -         
bcd_code[14]                                         Net          -        -       -         -           1         
control_module_uut.tx_data_out_pipe_4                FD1P3AX      D        In      0.000     50.712      -         
===================================================================================================================


Path information for path number 2: 
      Requested Period:                      5.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.894

    - Propagation time:                      50.712
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -45.818

    Number of logic level(s):                48
    Starting point:                          DS18B20Z_uut.data_out_fast[0] / Q
    Ending point:                            control_module_uut.tx_data_out_pipe_4 / D
    The start point is clocked by            DS18B20Z|clk_1mhz_derived_clock [rising] on pin CK
    The end   point is clocked by            step_project01|clk [rising] on pin CK

Instance / Net                                                    Pin      Pin               Arrival     No. of    
Name                                                 Type         Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
DS18B20Z_uut.data_out_fast[0]                        FD1P3AX      Q        Out     0.972     0.972       -         
data_out_fast[0]                                     Net          -        -       -         -           1         
temperature_code_0_cry_0_0                           CCU2D        A1       In      0.000     0.972       -         
temperature_code_0_cry_0_0                           CCU2D        COUT     Out     1.544     2.516       -         
temperature_code_0_cry_0                             Net          -        -       -         -           1         
temperature_code_0_cry_1_0                           CCU2D        CIN      In      0.000     2.516       -         
temperature_code_0_cry_1_0                           CCU2D        COUT     Out     0.143     2.659       -         
temperature_code_0_cry_2                             Net          -        -       -         -           1         
temperature_code_0_cry_3_0                           CCU2D        CIN      In      0.000     2.659       -         
temperature_code_0_cry_3_0                           CCU2D        COUT     Out     0.143     2.802       -         
temperature_code_0_cry_4                             Net          -        -       -         -           1         
temperature_code_0_cry_5_0                           CCU2D        CIN      In      0.000     2.802       -         
temperature_code_0_cry_5_0                           CCU2D        COUT     Out     0.143     2.945       -         
temperature_code_0_cry_6                             Net          -        -       -         -           1         
temperature_code_0_cry_7_0                           CCU2D        CIN      In      0.000     2.945       -         
temperature_code_0_cry_7_0                           CCU2D        S0       Out     1.549     4.494       -         
temperature_code_0_cry_7_0_S0                        Net          -        -       -         -           1         
temperature_code_0_cry_7_0_RNIRO9B1                  ORCALUT4     A        In      0.000     4.494       -         
temperature_code_0_cry_7_0_RNIRO9B1                  ORCALUT4     Z        Out     1.225     5.718       -         
bin_code_0_5                                         Net          -        -       -         -           5         
bin_code_0_5_cry_3_0                                 CCU2D        A1       In      0.000     5.718       -         
bin_code_0_5_cry_3_0                                 CCU2D        COUT     Out     1.544     7.263       -         
bin_code_0_5_cry_3                                   Net          -        -       -         -           1         
bin_code_0_5_cry_4_0                                 CCU2D        CIN      In      0.000     7.263       -         
bin_code_0_5_cry_4_0                                 CCU2D        COUT     Out     0.143     7.406       -         
bin_code_0_5_cry_5                                   Net          -        -       -         -           1         
bin_code_0_5_cry_6_0                                 CCU2D        CIN      In      0.000     7.406       -         
bin_code_0_5_cry_6_0                                 CCU2D        S0       Out     1.549     8.955       -         
bin_code_0_5[10]                                     Net          -        -       -         -           1         
bin_code_0_cry_9_0                                   CCU2D        B1       In      0.000     8.955       -         
bin_code_0_cry_9_0                                   CCU2D        COUT     Out     1.544     10.499      -         
bin_code_0_cry_10                                    Net          -        -       -         -           1         
bin_code_0_cry_11_0                                  CCU2D        CIN      In      0.000     10.499      -         
bin_code_0_cry_11_0                                  CCU2D        COUT     Out     0.143     10.642      -         
bin_code_0_cry_12                                    Net          -        -       -         -           1         
bin_code_0_cry_13_0                                  CCU2D        CIN      In      0.000     10.642      -         
bin_code_0_cry_13_0                                  CCU2D        COUT     Out     0.143     10.785      -         
bin_code_0_cry_14                                    Net          -        -       -         -           1         
bin_code_0_cry_15_0                                  CCU2D        CIN      In      0.000     10.785      -         
bin_code_0_cry_15_0                                  CCU2D        COUT     Out     0.143     10.928      -         
bin_code_0_cry_16                                    Net          -        -       -         -           1         
bin_code_0_cry_17_0                                  CCU2D        CIN      In      0.000     10.928      -         
bin_code_0_cry_17_0                                  CCU2D        S1       Out     0.981     11.909      -         
bin_code[18]                                         Net          -        -       -         -           12        
bin_to_bcd_uut.shift_reg_0_0_0_1[23]                 ORCALUT4     C        In      0.000     11.909      -         
bin_to_bcd_uut.shift_reg_0_0_0_1[23]                 ORCALUT4     Z        Out     1.017     12.925      -         
shift_reg_0_0_0_1[23]                                Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_0_0_0[23]                   ORCALUT4     D        In      0.000     12.925      -         
bin_to_bcd_uut.shift_reg_0_0_0[23]                   ORCALUT4     Z        Out     1.017     13.942      -         
shift_reg_0_0[23]                                    Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_16_a1_0_RNIO9803[23]        ORCALUT4     A        In      0.000     13.942      -         
bin_to_bcd_uut.shift_reg_16_a1_0_RNIO9803[23]        ORCALUT4     Z        Out     1.233     15.175      -         
shift_reg_16[23]                                     Net          -        -       -         -           6         
bin_to_bcd_uut.shift_reg_16_mb_RNIUSU06[22]          ORCALUT4     C        In      0.000     15.175      -         
bin_to_bcd_uut.shift_reg_16_mb_RNIUSU06[22]          ORCALUT4     Z        Out     1.017     16.192      -         
shift_reg_16_mb_RNIUSU06[22]                         Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_16_mb_RNITKI1B[22]          PFUMX        C0       In      0.000     16.192      -         
bin_to_bcd_uut.shift_reg_16_mb_RNITKI1B[22]          PFUMX        Z        Out     1.129     17.321      -         
shift_reg_20[22]                                     Net          -        -       -         -           6         
bin_to_bcd_uut.shift_reg_20_i_RNI927CH[21]           ORCALUT4     D        In      0.000     17.321      -         
bin_to_bcd_uut.shift_reg_20_i_RNI927CH[21]           ORCALUT4     Z        Out     1.277     18.598      -         
N_200                                                Net          -        -       -         -           10        
bin_to_bcd_uut.shift_reg_20_i_RNI4M9S91[21]          ORCALUT4     B        In      0.000     18.598      -         
bin_to_bcd_uut.shift_reg_20_i_RNI4M9S91[21]          ORCALUT4     Z        Out     1.017     19.614      -         
shift_reg_20_i_RNI4M9S91[21]                         Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_20_i_RNINLFD62[21]          ORCALUT4     B        In      0.000     19.614      -         
bin_to_bcd_uut.shift_reg_20_i_RNINLFD62[21]          ORCALUT4     Z        Out     1.297     20.911      -         
shift_reg_20_i_RNINLFD62[21]                         Net          -        -       -         -           13        
bin_to_bcd_uut.shift_reg_54_i_o3_N_3L3_RNI6RFFO2     ORCALUT4     A        In      0.000     20.911      -         
bin_to_bcd_uut.shift_reg_54_i_o3_N_3L3_RNI6RFFO2     ORCALUT4     Z        Out     1.017     21.928      -         
shift_reg_54_i_o3_N_3L3_RNI6RFFO2                    Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_34_N_2L1_RNIVG34H5          ORCALUT4     D        In      0.000     21.928      -         
bin_to_bcd_uut.shift_reg_34_N_2L1_RNIVG34H5          ORCALUT4     Z        Out     1.249     23.177      -         
N_184                                                Net          -        -       -         -           7         
bin_to_bcd_uut.shift_reg_41[22]                      ORCALUT4     C        In      0.000     23.177      -         
bin_to_bcd_uut.shift_reg_41[22]                      ORCALUT4     Z        Out     1.193     24.370      -         
shift_reg_41[22]                                     Net          -        -       -         -           4         
bin_to_bcd_uut.shift_reg_41_RNI2UKG1_0[22]           ORCALUT4     C        In      0.000     24.370      -         
bin_to_bcd_uut.shift_reg_41_RNI2UKG1_0[22]           ORCALUT4     Z        Out     1.017     25.387      -         
SUM1_30_3_N_4L6_sx                                   Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_54_i_0_RNIJUB71A[26]        ORCALUT4     B        In      0.000     25.387      -         
bin_to_bcd_uut.shift_reg_54_i_0_RNIJUB71A[26]        ORCALUT4     Z        Out     1.017     26.403      -         
shift_reg_54_i_0_RNIJUB71A[26]                       Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_54_i_0_RNIHD22E21[26]       ORCALUT4     D        In      0.000     26.403      -         
bin_to_bcd_uut.shift_reg_54_i_0_RNIHD22E21[26]       ORCALUT4     Z        Out     1.017     27.420      -         
shift_reg_54_i_0_RNIHD22E21[26]                      Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_44_RNIGNFC6N1[27]           ORCALUT4     C        In      0.000     27.420      -         
bin_to_bcd_uut.shift_reg_44_RNIGNFC6N1[27]           ORCALUT4     Z        Out     1.249     28.669      -         
shift_reg_44_RNIGNFC6N1[27]                          Net          -        -       -         -           7         
bin_to_bcd_uut.shift_reg_57_RNIFVFH2K2[32]           ORCALUT4     A        In      0.000     28.669      -         
bin_to_bcd_uut.shift_reg_57_RNIFVFH2K2[32]           ORCALUT4     Z        Out     1.153     29.822      -         
CO1_37                                               Net          -        -       -         -           3         
bin_to_bcd_uut.shift_reg_57_RNIFO62VG3[31]           ORCALUT4     A        In      0.000     29.822      -         
bin_to_bcd_uut.shift_reg_57_RNIFO62VG3[31]           ORCALUT4     Z        Out     1.273     31.095      -         
shift_reg_57_RNIFO62VG3[31]                          Net          -        -       -         -           9         
bin_to_bcd_uut.shift_reg_77[31]                      ORCALUT4     C        In      0.000     31.095      -         
bin_to_bcd_uut.shift_reg_77[31]                      ORCALUT4     Z        Out     1.193     32.287      -         
shift_reg_77[31]                                     Net          -        -       -         -           4         
bin_to_bcd_uut.shift_reg_77_RNI8FFGAB2[31]           ORCALUT4     C        In      0.000     32.287      -         
bin_to_bcd_uut.shift_reg_77_RNI8FFGAB2[31]           ORCALUT4     Z        Out     1.225     33.512      -         
CO2_31                                               Net          -        -       -         -           5         
bin_to_bcd_uut.shift_reg_77_RNIDAGITV1[32]           ORCALUT4     A        In      0.000     33.512      -         
bin_to_bcd_uut.shift_reg_77_RNIDAGITV1[32]           ORCALUT4     Z        Out     1.225     34.737      -         
CO1_30                                               Net          -        -       -         -           5         
bin_to_bcd_uut.shift_reg_93_RNI06PKK32[36]           ORCALUT4     A        In      0.000     34.737      -         
bin_to_bcd_uut.shift_reg_93_RNI06PKK32[36]           ORCALUT4     Z        Out     1.249     35.986      -         
N_128                                                Net          -        -       -         -           7         
bin_to_bcd_uut.shift_reg_106[35]                     ORCALUT4     C        In      0.000     35.986      -         
bin_to_bcd_uut.shift_reg_106[35]                     ORCALUT4     Z        Out     1.225     37.211      -         
shift_reg_106[35]                                    Net          -        -       -         -           5         
bin_to_bcd_uut.shift_reg_106_i_RNIPKB5UK1[34]        ORCALUT4     C        In      0.000     37.211      -         
bin_to_bcd_uut.shift_reg_106_i_RNIPKB5UK1[34]        ORCALUT4     Z        Out     1.233     38.443      -         
CO2_24                                               Net          -        -       -         -           6         
bin_to_bcd_uut.shift_reg_119_i_o3[34]                ORCALUT4     B        In      0.000     38.443      -         
bin_to_bcd_uut.shift_reg_119_i_o3[34]                ORCALUT4     Z        Out     1.277     39.720      -         
N_112                                                Net          -        -       -         -           10        
bin_to_bcd_uut.shift_reg_106_i_RNI4TQ8UK1[34]        ORCALUT4     B        In      0.000     39.720      -         
bin_to_bcd_uut.shift_reg_106_i_RNI4TQ8UK1[34]        ORCALUT4     Z        Out     1.153     40.873      -         
shift_reg_119[36]                                    Net          -        -       -         -           3         
bin_to_bcd_uut.shift_reg_135[36]                     ORCALUT4     C        In      0.000     40.873      -         
bin_to_bcd_uut.shift_reg_135[36]                     ORCALUT4     Z        Out     1.193     42.066      -         
shift_reg_135[36]                                    Net          -        -       -         -           4         
bin_to_bcd_uut.shift_reg_135_RNI3S467T2[36]          ORCALUT4     D        In      0.000     42.066      -         
bin_to_bcd_uut.shift_reg_135_RNI3S467T2[36]          ORCALUT4     Z        Out     1.017     43.083      -         
g0_5_1                                               Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_135_i_RNIN10V56[34]         ORCALUT4     B        In      0.000     43.083      -         
bin_to_bcd_uut.shift_reg_135_i_RNIN10V56[34]         ORCALUT4     Z        Out     1.193     44.275      -         
shift_reg_151[35]                                    Net          -        -       -         -           4         
bin_to_bcd_uut.shift_reg_151_i_RNIKDGFA6[34]         ORCALUT4     A        In      0.000     44.275      -         
bin_to_bcd_uut.shift_reg_151_i_RNIKDGFA6[34]         ORCALUT4     Z        Out     1.233     45.508      -         
CO2_10                                               Net          -        -       -         -           6         
bin_to_bcd_uut.shift_reg_151_i_RNI86NAB1[34]         ORCALUT4     A        In      0.000     45.508      -         
bin_to_bcd_uut.shift_reg_151_i_RNI86NAB1[34]         ORCALUT4     Z        Out     1.225     46.733      -         
shift_reg_167[35]                                    Net          -        -       -         -           5         
bin_to_bcd_uut.shift_reg_167_i_RNIQO65L1_0[34]       ORCALUT4     C        In      0.000     46.733      -         
bin_to_bcd_uut.shift_reg_167_i_RNIQO65L1_0[34]       ORCALUT4     Z        Out     1.249     47.982      -         
N_32                                                 Net          -        -       -         -           7         
bin_to_bcd_uut.shift_reg_151_i_RNI22FM7H1[34]        ORCALUT4     A        In      0.000     47.982      -         
bin_to_bcd_uut.shift_reg_151_i_RNI22FM7H1[34]        ORCALUT4     Z        Out     1.265     49.246      -         
shift_reg_186[35]                                    Net          -        -       -         -           8         
bin_to_bcd_uut.shift_reg_186_RNI29H0TK1[36]          ORCALUT4     C        In      0.000     49.246      -         
bin_to_bcd_uut.shift_reg_186_RNI29H0TK1[36]          ORCALUT4     Z        Out     1.017     50.263      -         
g0_1_2                                               Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_186_i_RNIIVHDNN1[34]        ORCALUT4     B        In      0.000     50.263      -         
bin_to_bcd_uut.shift_reg_186_i_RNIIVHDNN1[34]        ORCALUT4     Z        Out     0.449     50.712      -         
bcd_code[14]                                         Net          -        -       -         -           1         
control_module_uut.tx_data_out_pipe_4                FD1P3AX      D        In      0.000     50.712      -         
===================================================================================================================


Path information for path number 3: 
      Requested Period:                      5.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.894

    - Propagation time:                      50.712
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -45.818

    Number of logic level(s):                48
    Starting point:                          DS18B20Z_uut.data_out_fast[0] / Q
    Ending point:                            control_module_uut.tx_data_out_pipe_4 / D
    The start point is clocked by            DS18B20Z|clk_1mhz_derived_clock [rising] on pin CK
    The end   point is clocked by            step_project01|clk [rising] on pin CK

Instance / Net                                                    Pin      Pin               Arrival     No. of    
Name                                                 Type         Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
DS18B20Z_uut.data_out_fast[0]                        FD1P3AX      Q        Out     0.972     0.972       -         
data_out_fast[0]                                     Net          -        -       -         -           1         
temperature_code_0_cry_0_0                           CCU2D        A1       In      0.000     0.972       -         
temperature_code_0_cry_0_0                           CCU2D        COUT     Out     1.544     2.516       -         
temperature_code_0_cry_0                             Net          -        -       -         -           1         
temperature_code_0_cry_1_0                           CCU2D        CIN      In      0.000     2.516       -         
temperature_code_0_cry_1_0                           CCU2D        COUT     Out     0.143     2.659       -         
temperature_code_0_cry_2                             Net          -        -       -         -           1         
temperature_code_0_cry_3_0                           CCU2D        CIN      In      0.000     2.659       -         
temperature_code_0_cry_3_0                           CCU2D        COUT     Out     0.143     2.802       -         
temperature_code_0_cry_4                             Net          -        -       -         -           1         
temperature_code_0_cry_5_0                           CCU2D        CIN      In      0.000     2.802       -         
temperature_code_0_cry_5_0                           CCU2D        COUT     Out     0.143     2.945       -         
temperature_code_0_cry_6                             Net          -        -       -         -           1         
temperature_code_0_cry_7_0                           CCU2D        CIN      In      0.000     2.945       -         
temperature_code_0_cry_7_0                           CCU2D        S0       Out     1.549     4.494       -         
temperature_code_0_cry_7_0_S0                        Net          -        -       -         -           1         
temperature_code_0_cry_7_0_RNIRO9B1                  ORCALUT4     A        In      0.000     4.494       -         
temperature_code_0_cry_7_0_RNIRO9B1                  ORCALUT4     Z        Out     1.225     5.718       -         
bin_code_0_5                                         Net          -        -       -         -           5         
bin_code_0_5_cry_3_0                                 CCU2D        A1       In      0.000     5.718       -         
bin_code_0_5_cry_3_0                                 CCU2D        COUT     Out     1.544     7.263       -         
bin_code_0_5_cry_3                                   Net          -        -       -         -           1         
bin_code_0_5_cry_4_0                                 CCU2D        CIN      In      0.000     7.263       -         
bin_code_0_5_cry_4_0                                 CCU2D        S0       Out     1.549     8.812       -         
bin_code_0_5[8]                                      Net          -        -       -         -           1         
bin_code_0_cry_7_0                                   CCU2D        B1       In      0.000     8.812       -         
bin_code_0_cry_7_0                                   CCU2D        COUT     Out     1.544     10.357      -         
bin_code_0_cry_8                                     Net          -        -       -         -           1         
bin_code_0_cry_9_0                                   CCU2D        CIN      In      0.000     10.357      -         
bin_code_0_cry_9_0                                   CCU2D        COUT     Out     0.143     10.499      -         
bin_code_0_cry_10                                    Net          -        -       -         -           1         
bin_code_0_cry_11_0                                  CCU2D        CIN      In      0.000     10.499      -         
bin_code_0_cry_11_0                                  CCU2D        COUT     Out     0.143     10.642      -         
bin_code_0_cry_12                                    Net          -        -       -         -           1         
bin_code_0_cry_13_0                                  CCU2D        CIN      In      0.000     10.642      -         
bin_code_0_cry_13_0                                  CCU2D        COUT     Out     0.143     10.785      -         
bin_code_0_cry_14                                    Net          -        -       -         -           1         
bin_code_0_cry_15_0                                  CCU2D        CIN      In      0.000     10.785      -         
bin_code_0_cry_15_0                                  CCU2D        COUT     Out     0.143     10.928      -         
bin_code_0_cry_16                                    Net          -        -       -         -           1         
bin_code_0_cry_17_0                                  CCU2D        CIN      In      0.000     10.928      -         
bin_code_0_cry_17_0                                  CCU2D        S0       Out     0.981     11.909      -         
bin_code[17]                                         Net          -        -       -         -           12        
bin_to_bcd_uut.CO2_51_a0_0                           ORCALUT4     B        In      0.000     11.909      -         
bin_to_bcd_uut.CO2_51_a0_0                           ORCALUT4     Z        Out     1.017     12.925      -         
CO2_51_a0_0                                          Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_0_2[23]                     ORCALUT4     D        In      0.000     12.925      -         
bin_to_bcd_uut.shift_reg_0_2[23]                     ORCALUT4     Z        Out     1.017     13.942      -         
shift_reg_0_2[23]                                    Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_16_a1_0_RNIO9803[23]        ORCALUT4     C        In      0.000     13.942      -         
bin_to_bcd_uut.shift_reg_16_a1_0_RNIO9803[23]        ORCALUT4     Z        Out     1.233     15.175      -         
shift_reg_16[23]                                     Net          -        -       -         -           6         
bin_to_bcd_uut.shift_reg_16_mb_RNIUSU06[22]          ORCALUT4     C        In      0.000     15.175      -         
bin_to_bcd_uut.shift_reg_16_mb_RNIUSU06[22]          ORCALUT4     Z        Out     1.017     16.192      -         
shift_reg_16_mb_RNIUSU06[22]                         Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_16_mb_RNITKI1B[22]          PFUMX        C0       In      0.000     16.192      -         
bin_to_bcd_uut.shift_reg_16_mb_RNITKI1B[22]          PFUMX        Z        Out     1.129     17.321      -         
shift_reg_20[22]                                     Net          -        -       -         -           6         
bin_to_bcd_uut.shift_reg_20_i_RNI927CH[21]           ORCALUT4     D        In      0.000     17.321      -         
bin_to_bcd_uut.shift_reg_20_i_RNI927CH[21]           ORCALUT4     Z        Out     1.277     18.598      -         
N_200                                                Net          -        -       -         -           10        
bin_to_bcd_uut.shift_reg_20_i_RNI4M9S91[21]          ORCALUT4     B        In      0.000     18.598      -         
bin_to_bcd_uut.shift_reg_20_i_RNI4M9S91[21]          ORCALUT4     Z        Out     1.017     19.614      -         
shift_reg_20_i_RNI4M9S91[21]                         Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_20_i_RNINLFD62[21]          ORCALUT4     B        In      0.000     19.614      -         
bin_to_bcd_uut.shift_reg_20_i_RNINLFD62[21]          ORCALUT4     Z        Out     1.297     20.911      -         
shift_reg_20_i_RNINLFD62[21]                         Net          -        -       -         -           13        
bin_to_bcd_uut.shift_reg_54_i_o3_N_3L3_RNI6RFFO2     ORCALUT4     A        In      0.000     20.911      -         
bin_to_bcd_uut.shift_reg_54_i_o3_N_3L3_RNI6RFFO2     ORCALUT4     Z        Out     1.017     21.928      -         
shift_reg_54_i_o3_N_3L3_RNI6RFFO2                    Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_34_N_2L1_RNIVG34H5          ORCALUT4     D        In      0.000     21.928      -         
bin_to_bcd_uut.shift_reg_34_N_2L1_RNIVG34H5          ORCALUT4     Z        Out     1.249     23.177      -         
N_184                                                Net          -        -       -         -           7         
bin_to_bcd_uut.shift_reg_41[22]                      ORCALUT4     C        In      0.000     23.177      -         
bin_to_bcd_uut.shift_reg_41[22]                      ORCALUT4     Z        Out     1.193     24.370      -         
shift_reg_41[22]                                     Net          -        -       -         -           4         
bin_to_bcd_uut.shift_reg_41_RNI2UKG1_0[22]           ORCALUT4     C        In      0.000     24.370      -         
bin_to_bcd_uut.shift_reg_41_RNI2UKG1_0[22]           ORCALUT4     Z        Out     1.017     25.387      -         
SUM1_30_3_N_4L6_sx                                   Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_54_i_0_RNIJUB71A[26]        ORCALUT4     B        In      0.000     25.387      -         
bin_to_bcd_uut.shift_reg_54_i_0_RNIJUB71A[26]        ORCALUT4     Z        Out     1.017     26.403      -         
shift_reg_54_i_0_RNIJUB71A[26]                       Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_54_i_0_RNIHD22E21[26]       ORCALUT4     D        In      0.000     26.403      -         
bin_to_bcd_uut.shift_reg_54_i_0_RNIHD22E21[26]       ORCALUT4     Z        Out     1.017     27.420      -         
shift_reg_54_i_0_RNIHD22E21[26]                      Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_44_RNIGNFC6N1[27]           ORCALUT4     C        In      0.000     27.420      -         
bin_to_bcd_uut.shift_reg_44_RNIGNFC6N1[27]           ORCALUT4     Z        Out     1.249     28.669      -         
shift_reg_44_RNIGNFC6N1[27]                          Net          -        -       -         -           7         
bin_to_bcd_uut.shift_reg_57_RNIFVFH2K2[32]           ORCALUT4     A        In      0.000     28.669      -         
bin_to_bcd_uut.shift_reg_57_RNIFVFH2K2[32]           ORCALUT4     Z        Out     1.153     29.822      -         
CO1_37                                               Net          -        -       -         -           3         
bin_to_bcd_uut.shift_reg_57_RNIFO62VG3[31]           ORCALUT4     A        In      0.000     29.822      -         
bin_to_bcd_uut.shift_reg_57_RNIFO62VG3[31]           ORCALUT4     Z        Out     1.273     31.095      -         
shift_reg_57_RNIFO62VG3[31]                          Net          -        -       -         -           9         
bin_to_bcd_uut.shift_reg_77[31]                      ORCALUT4     C        In      0.000     31.095      -         
bin_to_bcd_uut.shift_reg_77[31]                      ORCALUT4     Z        Out     1.193     32.287      -         
shift_reg_77[31]                                     Net          -        -       -         -           4         
bin_to_bcd_uut.shift_reg_77_RNI8FFGAB2[31]           ORCALUT4     C        In      0.000     32.287      -         
bin_to_bcd_uut.shift_reg_77_RNI8FFGAB2[31]           ORCALUT4     Z        Out     1.225     33.512      -         
CO2_31                                               Net          -        -       -         -           5         
bin_to_bcd_uut.shift_reg_77_RNIDAGITV1[32]           ORCALUT4     A        In      0.000     33.512      -         
bin_to_bcd_uut.shift_reg_77_RNIDAGITV1[32]           ORCALUT4     Z        Out     1.225     34.737      -         
CO1_30                                               Net          -        -       -         -           5         
bin_to_bcd_uut.shift_reg_93_RNI06PKK32[36]           ORCALUT4     A        In      0.000     34.737      -         
bin_to_bcd_uut.shift_reg_93_RNI06PKK32[36]           ORCALUT4     Z        Out     1.249     35.986      -         
N_128                                                Net          -        -       -         -           7         
bin_to_bcd_uut.shift_reg_106[35]                     ORCALUT4     C        In      0.000     35.986      -         
bin_to_bcd_uut.shift_reg_106[35]                     ORCALUT4     Z        Out     1.225     37.211      -         
shift_reg_106[35]                                    Net          -        -       -         -           5         
bin_to_bcd_uut.shift_reg_106_i_RNIPKB5UK1[34]        ORCALUT4     C        In      0.000     37.211      -         
bin_to_bcd_uut.shift_reg_106_i_RNIPKB5UK1[34]        ORCALUT4     Z        Out     1.233     38.443      -         
CO2_24                                               Net          -        -       -         -           6         
bin_to_bcd_uut.shift_reg_119_i_o3[34]                ORCALUT4     B        In      0.000     38.443      -         
bin_to_bcd_uut.shift_reg_119_i_o3[34]                ORCALUT4     Z        Out     1.277     39.720      -         
N_112                                                Net          -        -       -         -           10        
bin_to_bcd_uut.shift_reg_106_i_RNI4TQ8UK1[34]        ORCALUT4     B        In      0.000     39.720      -         
bin_to_bcd_uut.shift_reg_106_i_RNI4TQ8UK1[34]        ORCALUT4     Z        Out     1.153     40.873      -         
shift_reg_119[36]                                    Net          -        -       -         -           3         
bin_to_bcd_uut.shift_reg_135[36]                     ORCALUT4     C        In      0.000     40.873      -         
bin_to_bcd_uut.shift_reg_135[36]                     ORCALUT4     Z        Out     1.193     42.066      -         
shift_reg_135[36]                                    Net          -        -       -         -           4         
bin_to_bcd_uut.shift_reg_135_RNI3S467T2[36]          ORCALUT4     D        In      0.000     42.066      -         
bin_to_bcd_uut.shift_reg_135_RNI3S467T2[36]          ORCALUT4     Z        Out     1.017     43.083      -         
g0_5_1                                               Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_135_i_RNIN10V56[34]         ORCALUT4     B        In      0.000     43.083      -         
bin_to_bcd_uut.shift_reg_135_i_RNIN10V56[34]         ORCALUT4     Z        Out     1.193     44.275      -         
shift_reg_151[35]                                    Net          -        -       -         -           4         
bin_to_bcd_uut.shift_reg_151_i_RNIKDGFA6[34]         ORCALUT4     A        In      0.000     44.275      -         
bin_to_bcd_uut.shift_reg_151_i_RNIKDGFA6[34]         ORCALUT4     Z        Out     1.233     45.508      -         
CO2_10                                               Net          -        -       -         -           6         
bin_to_bcd_uut.shift_reg_151_i_RNI86NAB1[34]         ORCALUT4     A        In      0.000     45.508      -         
bin_to_bcd_uut.shift_reg_151_i_RNI86NAB1[34]         ORCALUT4     Z        Out     1.225     46.733      -         
shift_reg_167[35]                                    Net          -        -       -         -           5         
bin_to_bcd_uut.shift_reg_167_i_RNIQO65L1_0[34]       ORCALUT4     C        In      0.000     46.733      -         
bin_to_bcd_uut.shift_reg_167_i_RNIQO65L1_0[34]       ORCALUT4     Z        Out     1.249     47.982      -         
N_32                                                 Net          -        -       -         -           7         
bin_to_bcd_uut.shift_reg_151_i_RNI22FM7H1[34]        ORCALUT4     A        In      0.000     47.982      -         
bin_to_bcd_uut.shift_reg_151_i_RNI22FM7H1[34]        ORCALUT4     Z        Out     1.265     49.246      -         
shift_reg_186[35]                                    Net          -        -       -         -           8         
bin_to_bcd_uut.shift_reg_186_RNI29H0TK1[36]          ORCALUT4     C        In      0.000     49.246      -         
bin_to_bcd_uut.shift_reg_186_RNI29H0TK1[36]          ORCALUT4     Z        Out     1.017     50.263      -         
g0_1_2                                               Net          -        -       -         -           1         
bin_to_bcd_uut.shift_reg_186_i_RNIIVHDNN1[34]        ORCALUT4     B        In      0.000     50.263      -         
bin_to_bcd_uut.shift_reg_186_i_RNIIVHDNN1[34]        ORCALUT4     Z        Out     0.449     50.712      -         
bcd_code[14]                                         Net          -        -       -         -           1         
control_module_uut.tx_data_out_pipe_4                FD1P3AX      D        In      0.000     50.712      -         
===================================================================================================================




====================================
Detailed Report for Clock: step_project01|clk
====================================



Starting Points with Worst Slack
********************************

                            Starting                                                 Arrival           
Instance                    Reference              Type        Pin     Net           Time        Slack 
                            Clock                                                                      
-------------------------------------------------------------------------------------------------------
OLED12832_uut.num[2]        step_project01|clk     FD1P3AX     Q       num[2]        1.236       -7.920
OLED12832_uut.num[3]        step_project01|clk     FD1P3AX     Q       num[3]        1.236       -7.920
OLED12832_uut.num[0]        step_project01|clk     FD1P3AX     Q       num[0]        1.296       -7.908
OLED12832_uut.num[1]        step_project01|clk     FD1P3AX     Q       num[1]        1.292       -7.904
OLED12832_uut.num[4]        step_project01|clk     FD1P3AX     Q       num[4]        1.044       -7.808
OLED12832_uut.num[5]        step_project01|clk     FD1P3AX     Q       num[5]        1.044       -7.808
OLED12832_uut.num[6]        step_project01|clk     FD1P3AX     Q       num[6]        1.044       -7.808
OLED12832_uut.num[7]        step_project01|clk     FD1P3AX     Q       num[7]        1.044       -7.808
OLED12832_uut.char[102]     step_project01|clk     FD1P3AX     Q       char[102]     1.204       -7.745
OLED12832_uut.char[100]     step_project01|clk     FD1P3AX     Q       char[100]     1.108       -7.649
=======================================================================================================


Ending Points with Worst Slack
******************************

                              Starting                                                         Required           
Instance                      Reference              Type        Pin     Net                   Time         Slack 
                              Clock                                                                               
------------------------------------------------------------------------------------------------------------------
OLED12832_uut.char_reg[6]     step_project01|clk     FD1P3AX     D       N_584                 5.089        -7.920
OLED12832_uut.char_reg[1]     step_project01|clk     FD1P3AX     D       char_reg_RNO[1]       5.089        -7.736
OLED12832_uut.char_reg[5]     step_project01|clk     FD1P3AX     D       N_562                 5.089        -7.496
OLED12832_uut.char_reg[4]     step_project01|clk     FD1P3AX     D       N_540                 5.089        -7.466
OLED12832_uut.char_reg[0]     step_project01|clk     FD1P3AX     D       N_454                 5.089        -7.175
OLED12832_uut.char_reg[2]     step_project01|clk     FD1P3AX     D       char_reg_RNO[2]       5.089        -7.175
OLED12832_uut.char_reg[3]     step_project01|clk     FD1P3AX     D       N_520                 5.089        -6.934
OLED12832_uut.char_reg[7]     step_project01|clk     FD1P3AX     D       N_604                 5.089        -6.439
OLED12832_uut.state[0]        step_project01|clk     FD1S3AY     D       N_323_i               5.089        -4.155
OLED12832_uut.state[1]        step_project01|clk     FD1S3AX     D       state_ns_0_i_i[1]     5.089        -3.139
==================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      5.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.089

    - Propagation time:                      13.009
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -7.920

    Number of logic level(s):                13
    Starting point:                          OLED12832_uut.num[2] / Q
    Ending point:                            OLED12832_uut.char_reg[6] / D
    The start point is clocked by            step_project01|clk [rising] on pin CK
    The end   point is clocked by            step_project01|clk [rising] on pin CK

Instance / Net                                                    Pin      Pin                Arrival     No. of    
Name                                                 Type         Name     Dir     Delay      Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------
OLED12832_uut.num[2]                                 FD1P3AX      Q        Out     1.236      1.236       -         
num[2]                                               Net          -        -       -          -           11        
OLED12832_uut._decfrac19_0_a2_1_a2_0_0               ORCALUT4     A        In      0.000      1.236       -         
OLED12832_uut._decfrac19_0_a2_1_a2_0_0               ORCALUT4     Z        Out     1.297      2.533       -         
_decfrac19_0_a2_1_a2_0_0                             Net          -        -       -          -           13        
OLED12832_uut.un23_char_reg_1_iv_N_2L1_0_RNO         ORCALUT4     C        In      0.000      2.533       -         
OLED12832_uut.un23_char_reg_1_iv_N_2L1_0_RNO         ORCALUT4     Z        Out     1.017      3.549       -         
char_m[0]                                            Net          -        -       -          -           1         
OLED12832_uut.un23_char_reg_1_iv_N_2L1_0             ORCALUT4     D        In      0.000      3.549       -         
OLED12832_uut.un23_char_reg_1_iv_N_2L1_0             ORCALUT4     Z        Out     1.225      4.774       -         
un23_char_reg_1_iv_N_2L1_0                           Net          -        -       -          -           5         
OLED12832_uut.un23_char_reg_1_iv[0]                  ORCALUT4     D        In      0.000      4.774       -         
OLED12832_uut.un23_char_reg_1_iv[0]                  ORCALUT4     Z        Out     1.651      6.425       -         
N_1_i                                                Net          -        -       -          -           208       
OLED12832_uut.un112_char_reg_cnst_23_16_.m132        ORCALUT4     B        In      0.000      6.425       -         
OLED12832_uut.un112_char_reg_cnst_23_16_.m132        ORCALUT4     Z        Out     1.017      7.442       -         
N_133_0                                              Net          -        -       -          -           1         
OLED12832_uut.un112_char_reg_cnst_23_16_.m134_bm     ORCALUT4     B        In      0.000      7.442       -         
OLED12832_uut.un112_char_reg_cnst_23_16_.m134_bm     ORCALUT4     Z        Out     1.017      8.459       -         
m134_bm                                              Net          -        -       -          -           1         
OLED12832_uut.un112_char_reg_cnst_23_16_.m134        PFUMX        ALUT     In      0.000      8.459       -         
OLED12832_uut.un112_char_reg_cnst_23_16_.m134        PFUMX        Z        Out     -0.064     8.395       -         
N_135_0                                              Net          -        -       -          -           1         
OLED12832_uut.un112_char_reg_cnst_23_16_.m135        L6MUX21      D1       In      0.000      8.395       -         
OLED12832_uut.un112_char_reg_cnst_23_16_.m135        L6MUX21      Z        Out     0.732      9.127       -         
N_136                                                Net          -        -       -          -           1         
OLED12832_uut.char_reg_RNO_6[6]                      ORCALUT4     D        In      0.000      9.127       -         
OLED12832_uut.char_reg_RNO_6[6]                      ORCALUT4     Z        Out     1.017      10.144      -         
d_m4_1_bm_1                                          Net          -        -       -          -           1         
OLED12832_uut.char_reg_RNO_4[6]                      ORCALUT4     D        In      0.000      10.144      -         
OLED12832_uut.char_reg_RNO_4[6]                      ORCALUT4     Z        Out     1.017      11.161      -         
char_reg_RNO_4[6]                                    Net          -        -       -          -           1         
OLED12832_uut.char_reg_RNO_2[6]                      PFUMX        ALUT     In      0.000      11.161      -         
OLED12832_uut.char_reg_RNO_2[6]                      PFUMX        Z        Out     0.214      11.375      -         
char_reg_RNO_2[6]                                    Net          -        -       -          -           1         
OLED12832_uut.char_reg_RNO_0[6]                      ORCALUT4     C        In      0.000      11.375      -         
OLED12832_uut.char_reg_RNO_0[6]                      ORCALUT4     Z        Out     1.017      12.392      -         
N_599                                                Net          -        -       -          -           1         
OLED12832_uut.char_reg_RNO[6]                        ORCALUT4     A        In      0.000      12.392      -         
OLED12832_uut.char_reg_RNO[6]                        ORCALUT4     Z        Out     0.617      13.009      -         
N_584                                                Net          -        -       -          -           1         
OLED12832_uut.char_reg[6]                            FD1P3AX      D        In      0.000      13.009      -         
====================================================================================================================


Path information for path number 2: 
      Requested Period:                      5.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.089

    - Propagation time:                      13.009
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -7.920

    Number of logic level(s):                13
    Starting point:                          OLED12832_uut.num[3] / Q
    Ending point:                            OLED12832_uut.char_reg[6] / D
    The start point is clocked by            step_project01|clk [rising] on pin CK
    The end   point is clocked by            step_project01|clk [rising] on pin CK

Instance / Net                                                    Pin      Pin                Arrival     No. of    
Name                                                 Type         Name     Dir     Delay      Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------
OLED12832_uut.num[3]                                 FD1P3AX      Q        Out     1.236      1.236       -         
num[3]                                               Net          -        -       -          -           11        
OLED12832_uut._decfrac19_0_a2_1_a2_0_0               ORCALUT4     B        In      0.000      1.236       -         
OLED12832_uut._decfrac19_0_a2_1_a2_0_0               ORCALUT4     Z        Out     1.297      2.533       -         
_decfrac19_0_a2_1_a2_0_0                             Net          -        -       -          -           13        
OLED12832_uut.un23_char_reg_1_iv_N_2L1_0_RNO         ORCALUT4     C        In      0.000      2.533       -         
OLED12832_uut.un23_char_reg_1_iv_N_2L1_0_RNO         ORCALUT4     Z        Out     1.017      3.549       -         
char_m[0]                                            Net          -        -       -          -           1         
OLED12832_uut.un23_char_reg_1_iv_N_2L1_0             ORCALUT4     D        In      0.000      3.549       -         
OLED12832_uut.un23_char_reg_1_iv_N_2L1_0             ORCALUT4     Z        Out     1.225      4.774       -         
un23_char_reg_1_iv_N_2L1_0                           Net          -        -       -          -           5         
OLED12832_uut.un23_char_reg_1_iv[0]                  ORCALUT4     D        In      0.000      4.774       -         
OLED12832_uut.un23_char_reg_1_iv[0]                  ORCALUT4     Z        Out     1.651      6.425       -         
N_1_i                                                Net          -        -       -          -           208       
OLED12832_uut.un112_char_reg_cnst_23_16_.m132        ORCALUT4     B        In      0.000      6.425       -         
OLED12832_uut.un112_char_reg_cnst_23_16_.m132        ORCALUT4     Z        Out     1.017      7.442       -         
N_133_0                                              Net          -        -       -          -           1         
OLED12832_uut.un112_char_reg_cnst_23_16_.m134_bm     ORCALUT4     B        In      0.000      7.442       -         
OLED12832_uut.un112_char_reg_cnst_23_16_.m134_bm     ORCALUT4     Z        Out     1.017      8.459       -         
m134_bm                                              Net          -        -       -          -           1         
OLED12832_uut.un112_char_reg_cnst_23_16_.m134        PFUMX        ALUT     In      0.000      8.459       -         
OLED12832_uut.un112_char_reg_cnst_23_16_.m134        PFUMX        Z        Out     -0.064     8.395       -         
N_135_0                                              Net          -        -       -          -           1         
OLED12832_uut.un112_char_reg_cnst_23_16_.m135        L6MUX21      D1       In      0.000      8.395       -         
OLED12832_uut.un112_char_reg_cnst_23_16_.m135        L6MUX21      Z        Out     0.732      9.127       -         
N_136                                                Net          -        -       -          -           1         
OLED12832_uut.char_reg_RNO_6[6]                      ORCALUT4     D        In      0.000      9.127       -         
OLED12832_uut.char_reg_RNO_6[6]                      ORCALUT4     Z        Out     1.017      10.144      -         
d_m4_1_bm_1                                          Net          -        -       -          -           1         
OLED12832_uut.char_reg_RNO_4[6]                      ORCALUT4     D        In      0.000      10.144      -         
OLED12832_uut.char_reg_RNO_4[6]                      ORCALUT4     Z        Out     1.017      11.161      -         
char_reg_RNO_4[6]                                    Net          -        -       -          -           1         
OLED12832_uut.char_reg_RNO_2[6]                      PFUMX        ALUT     In      0.000      11.161      -         
OLED12832_uut.char_reg_RNO_2[6]                      PFUMX        Z        Out     0.214      11.375      -         
char_reg_RNO_2[6]                                    Net          -        -       -          -           1         
OLED12832_uut.char_reg_RNO_0[6]                      ORCALUT4     C        In      0.000      11.375      -         
OLED12832_uut.char_reg_RNO_0[6]                      ORCALUT4     Z        Out     1.017      12.392      -         
N_599                                                Net          -        -       -          -           1         
OLED12832_uut.char_reg_RNO[6]                        ORCALUT4     A        In      0.000      12.392      -         
OLED12832_uut.char_reg_RNO[6]                        ORCALUT4     Z        Out     0.617      13.009      -         
N_584                                                Net          -        -       -          -           1         
OLED12832_uut.char_reg[6]                            FD1P3AX      D        In      0.000      13.009      -         
====================================================================================================================


Path information for path number 3: 
      Requested Period:                      5.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.089

    - Propagation time:                      12.997
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -7.908

    Number of logic level(s):                13
    Starting point:                          OLED12832_uut.num[0] / Q
    Ending point:                            OLED12832_uut.char_reg[6] / D
    The start point is clocked by            step_project01|clk [rising] on pin CK
    The end   point is clocked by            step_project01|clk [rising] on pin CK

Instance / Net                                                    Pin      Pin                Arrival     No. of    
Name                                                 Type         Name     Dir     Delay      Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------
OLED12832_uut.num[0]                                 FD1P3AX      Q        Out     1.296      1.296       -         
num[0]                                               Net          -        -       -          -           24        
OLED12832_uut.un23_char_reg_0_0_a2_i_a2[5]           ORCALUT4     A        In      0.000      1.296       -         
OLED12832_uut.un23_char_reg_0_0_a2_i_a2[5]           ORCALUT4     Z        Out     1.225      2.521       -         
N_511                                                Net          -        -       -          -           5         
OLED12832_uut.un23_char_reg_1_iv_N_2L1_0_RNO         ORCALUT4     A        In      0.000      2.521       -         
OLED12832_uut.un23_char_reg_1_iv_N_2L1_0_RNO         ORCALUT4     Z        Out     1.017      3.537       -         
char_m[0]                                            Net          -        -       -          -           1         
OLED12832_uut.un23_char_reg_1_iv_N_2L1_0             ORCALUT4     D        In      0.000      3.537       -         
OLED12832_uut.un23_char_reg_1_iv_N_2L1_0             ORCALUT4     Z        Out     1.225      4.762       -         
un23_char_reg_1_iv_N_2L1_0                           Net          -        -       -          -           5         
OLED12832_uut.un23_char_reg_1_iv[0]                  ORCALUT4     D        In      0.000      4.762       -         
OLED12832_uut.un23_char_reg_1_iv[0]                  ORCALUT4     Z        Out     1.651      6.413       -         
N_1_i                                                Net          -        -       -          -           208       
OLED12832_uut.un112_char_reg_cnst_23_16_.m132        ORCALUT4     B        In      0.000      6.413       -         
OLED12832_uut.un112_char_reg_cnst_23_16_.m132        ORCALUT4     Z        Out     1.017      7.430       -         
N_133_0                                              Net          -        -       -          -           1         
OLED12832_uut.un112_char_reg_cnst_23_16_.m134_bm     ORCALUT4     B        In      0.000      7.430       -         
OLED12832_uut.un112_char_reg_cnst_23_16_.m134_bm     ORCALUT4     Z        Out     1.017      8.447       -         
m134_bm                                              Net          -        -       -          -           1         
OLED12832_uut.un112_char_reg_cnst_23_16_.m134        PFUMX        ALUT     In      0.000      8.447       -         
OLED12832_uut.un112_char_reg_cnst_23_16_.m134        PFUMX        Z        Out     -0.064     8.383       -         
N_135_0                                              Net          -        -       -          -           1         
OLED12832_uut.un112_char_reg_cnst_23_16_.m135        L6MUX21      D1       In      0.000      8.383       -         
OLED12832_uut.un112_char_reg_cnst_23_16_.m135        L6MUX21      Z        Out     0.732      9.115       -         
N_136                                                Net          -        -       -          -           1         
OLED12832_uut.char_reg_RNO_6[6]                      ORCALUT4     D        In      0.000      9.115       -         
OLED12832_uut.char_reg_RNO_6[6]                      ORCALUT4     Z        Out     1.017      10.132      -         
d_m4_1_bm_1                                          Net          -        -       -          -           1         
OLED12832_uut.char_reg_RNO_4[6]                      ORCALUT4     D        In      0.000      10.132      -         
OLED12832_uut.char_reg_RNO_4[6]                      ORCALUT4     Z        Out     1.017      11.149      -         
char_reg_RNO_4[6]                                    Net          -        -       -          -           1         
OLED12832_uut.char_reg_RNO_2[6]                      PFUMX        ALUT     In      0.000      11.149      -         
OLED12832_uut.char_reg_RNO_2[6]                      PFUMX        Z        Out     0.214      11.363      -         
char_reg_RNO_2[6]                                    Net          -        -       -          -           1         
OLED12832_uut.char_reg_RNO_0[6]                      ORCALUT4     C        In      0.000      11.363      -         
OLED12832_uut.char_reg_RNO_0[6]                      ORCALUT4     Z        Out     1.017      12.380      -         
N_599                                                Net          -        -       -          -           1         
OLED12832_uut.char_reg_RNO[6]                        ORCALUT4     A        In      0.000      12.380      -         
OLED12832_uut.char_reg_RNO[6]                        ORCALUT4     Z        Out     0.617      12.997      -         
N_584                                                Net          -        -       -          -           1         
OLED12832_uut.char_reg[6]                            FD1P3AX      D        In      0.000      12.997      -         
====================================================================================================================



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:04m:59s; CPU Time elapsed 0h:04m:59s; Memory used current: 220MB peak: 245MB)


Finished timing report (Real Time elapsed 0h:04m:59s; CPU Time elapsed 0h:04m:59s; Memory used current: 220MB peak: 245MB)

---------------------------------------
Resource Usage Report
Part: lcmxo2_4000hc-4

Register bits: 349 of 4320 (8%)
PIC Latch:       0
I/O cells:       10


Details:
BB:             1
CCU2D:          119
FD1P3AX:        240
FD1P3AY:        1
FD1S3AX:        96
FD1S3AY:        4
GSR:            1
IB:             3
IFS1P3DX:       2
INV:            5
L6MUX21:        27
OB:             6
OFS1P3BX:       4
OFS1P3DX:       2
ORCALUT4:       1321
PFUMX:          117
PUR:            1
VHI:            7
VLO:            9
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:04m:59s; CPU Time elapsed 0h:04m:59s; Memory used current: 38MB peak: 245MB)

Process took 0h:04m:59s realtime, 0h:04m:59s cputime
# Mon Feb 15 12:47:45 2021

###########################################################]