Map TRACE Report
Loading design for application trce from file step_project01_impl1_map.ncd.
Design name: step_project01
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-4000HC
Package: CSBGA132
Performance: 4
Loading device for application trce from file 'xo2c4000.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.11.0.396.4
Thu Feb 18 17:27:50 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o step_project01_impl1.tw1 -gui -msgset C:/Users/CROFY/Documents/Diamond/Project/step_project01/promote.xml step_project01_impl1_map.ncd step_project01_impl1.prf
Design file: step_project01_impl1_map.ncd
Preference file: step_project01_impl1.prf
Device,speed: LCMXO2-4000HC,4
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "clk_c" 23.368000 MHz (4096 errors)
4096 items scored, 4096 timing errors detected.
Warning: 0.835MHz is the maximum frequency for this preference.
FREQUENCY NET "clk_c_generated_8" 399.840000 MHz (4 errors)
4 items scored, 4 timing errors detected.
Warning: 170.155MHz is the maximum frequency for this preference.
28 potential circuit loops found in timing analysis.
28 potential circuit loops found in timing analysis.
28 potential circuit loops found in timing analysis.
Report Type: based on TRACE automatically generated preferences
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "clk_c" 23.368000 MHz ;
4096 items scored, 4096 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 7.479ns (weighted slack = -1155.438ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q control_module_uut/i23195 (from clk_c_generated_8 +)
Destination: FF Data in OLED12832_uut/char_i8 (to clk_c +)
Delay: 7.590ns (38.6% logic, 61.4% route), 6 logic levels.
Constraint Details:
7.590ns physical path delay control_module_uut/SLICE_608 to OLED12832_uut/SLICE_275 exceeds
(delay constraint based on source clock period of 2.501ns and destination clock period of 42.794ns)
0.277ns delay constraint less
0.166ns DIN_SET requirement (totaling 0.111ns) by 7.479ns
Physical Path Details:
Data path control_module_uut/SLICE_608 to OLED12832_uut/SLICE_275:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 *SLICE_608.CLK to */SLICE_608.Q0 control_module_uut/SLICE_608 (from clk_c_generated_8)
ROUTE 2 e 1.234 */SLICE_608.Q0 to *SLICE_1184.C1 n35352
CTOF_DEL --- 0.495 *SLICE_1184.C1 to *SLICE_1184.F1 OLED12832_uut/SLICE_1184
ROUTE 2 e 0.480 *SLICE_1184.F1 to *SLICE_1184.B0 n61061
CTOF_DEL --- 0.495 *SLICE_1184.B0 to *SLICE_1184.F0 OLED12832_uut/SLICE_1184
ROUTE 1 e 1.234 *SLICE_1184.F0 to *SLICE_1011.C1 OLED12832_uut/n1_adj_3158
CTOF_DEL --- 0.495 *SLICE_1011.C1 to *SLICE_1011.F1 OLED12832_uut/SLICE_1011
ROUTE 1 e 0.480 *SLICE_1011.F1 to *SLICE_1011.B0 OLED12832_uut/char_167_N_1235_8
CTOF_DEL --- 0.495 *SLICE_1011.B0 to *SLICE_1011.F0 OLED12832_uut/SLICE_1011
ROUTE 1 e 1.234 *SLICE_1011.F0 to */SLICE_275.C1 OLED12832_uut/n16_adj_3157
CTOF_DEL --- 0.495 */SLICE_275.C1 to */SLICE_275.F1 OLED12832_uut/SLICE_275
ROUTE 1 e 0.001 */SLICE_275.F1 to *SLICE_275.DI1 OLED12832_uut/char_167_N_904_8 (to clk_c)
--------
7.590 (38.6% logic, 61.4% route), 6 logic levels.
Warning: 0.835MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "clk_c_generated_8" 399.840000 MHz ;
4 items scored, 4 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 3.376ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q control_module_uut/temp_out_i8_23196_23197_reset (from clk_c +)
Destination: FF Data in control_module_uut/i23195 (to clk_c_generated_8 +)
Delay: 5.144ns (28.0% logic, 72.0% route), 3 logic levels.
Constraint Details:
5.144ns physical path delay SLICE_1506 to control_module_uut/SLICE_608 exceeds
(delay constraint based on source clock period of 42.794ns and destination clock period of 2.501ns)
2.501ns delay constraint less
0.733ns LSRREC_SET requirement (totaling 1.768ns) by 3.376ns
Physical Path Details:
Data path SLICE_1506 to control_module_uut/SLICE_608:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 SLICE_1506.CLK to SLICE_1506.Q0 SLICE_1506 (from clk_c)
ROUTE 2 e 1.234 SLICE_1506.Q0 to *SLICE_1184.A1 n35354
CTOF_DEL --- 0.495 *SLICE_1184.A1 to *SLICE_1184.F1 OLED12832_uut/SLICE_1184
ROUTE 2 e 1.234 *SLICE_1184.F1 to *SLICE_1488.C1 n61061
CTOF_DEL --- 0.495 *SLICE_1488.C1 to *SLICE_1488.F1 control_module_uut/SLICE_1488
ROUTE 2 e 1.234 *SLICE_1488.F1 to *SLICE_608.LSR control_module_uut/temp_out_31__N_1883 (to clk_c_generated_8)
--------
5.144 (28.0% logic, 72.0% route), 3 logic levels.
Warning: 170.155MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_c" 23.368000 MHz ; | 23.368 MHz| 0.835 MHz| 6 *
| | |
FREQUENCY NET "clk_c_generated_8" | | |
399.840000 MHz ; | 399.840 MHz| 170.155 MHz| 3 *
| | |
----------------------------------------------------------------------------
2 preferences(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
bin_to_bcd_uut/n60844 | 3| 4093| 99.83%
| | |
bin_to_bcd_uut/n60834 | 3| 4093| 99.83%
| | |
bin_to_bcd_uut/bcd_code_24__N_380 | 11| 4093| 99.83%
| | |
bin_to_bcd_uut/bcd_code_24__N_636 | 3| 4093| 99.83%
| | |
bin_to_bcd_uut/n60653 | 3| 4093| 99.83%
| | |
bin_to_bcd_uut/n60756 | 3| 4093| 99.83%
| | |
bin_to_bcd_uut/n60640 | 3| 4093| 99.83%
| | |
bin_to_bcd_uut/n60738 | 3| 4093| 99.83%
| | |
bin_to_bcd_uut/n8120 | 4| 4093| 99.83%
| | |
bin_to_bcd_uut/n60628 | 3| 4093| 99.83%
| | |
bin_to_bcd_uut/n60701 | 4| 4093| 99.83%
| | |
bin_to_bcd_uut/n59905 | 2| 4093| 99.83%
| | |
control_module_uut/tx_data_out_7_N_2749_| | |
6 | 1| 4093| 99.83%
| | |
n60622 | 1| 4093| 99.83%
| | |
bcd_code_24__N_344 | 9| 4093| 99.83%
| | |
n8116 | 9| 4093| 99.83%
| | |
n54690 | 1| 4093| 99.83%
| | |
n54709 | 1| 4093| 99.83%
| | |
temperature_code_4 | 2| 4093| 99.83%
| | |
n8 | 7| 4093| 99.83%
| | |
temperature_flag_N_23 | 38| 4093| 99.83%
| | |
bin_code_20 | 15| 4093| 99.83%
| | |
n54708 | 1| 4091| 99.78%
| | |
bin_to_bcd_uut/n60772 | 3| 4090| 99.76%
| | |
bin_to_bcd_uut/n60788 | 3| 4061| 99.05%
| | |
n54707 | 1| 4056| 98.93%
| | |
bin_to_bcd_uut/n60800 | 3| 3890| 94.88%
| | |
n54712 | 1| 3862| 94.20%
| | |
n54706 | 1| 3804| 92.78%
| | |
bin_to_bcd_uut/bcd_code_24__N_362 | 10| 3187| 77.73%
| | |
bin_to_bcd_uut/bcd_code_24__N_407 | 9| 3176| 77.46%
| | |
bin_to_bcd_uut/n60816 | 5| 3103| 75.68%
| | |
bin_to_bcd_uut/n60811 | 3| 3103| 75.68%
| | |
bin_to_bcd_uut/bcd_code_24__N_402 | 5| 3103| 75.68%
| | |
bin_to_bcd_uut/n60794 | 5| 3103| 75.68%
| | |
bin_to_bcd_uut/n60780 | 5| 3103| 75.68%
| | |
bin_to_bcd_uut/n60763 | 5| 3102| 75.66%
| | |
bin_to_bcd_uut/n60674 | 5| 3097| 75.54%
| | |
bin_to_bcd_uut/n60668 | 2| 3097| 75.54%
| | |
bin_to_bcd_uut/bcd_code_24__N_641 | 4| 3097| 75.54%
| | |
bin_to_bcd_uut/bcd_code_24__N_590 | 9| 3097| 75.54%
| | |
bin_to_bcd_uut/bcd_code_24__N_674 | 9| 3097| 75.54%
| | |
bin_to_bcd_uut/bcd_code_24__N_725 | 8| 3096| 75.51%
| | |
bin_to_bcd_uut/bcd_code_24__N_767 | 6| 3096| 75.51%
| | |
n12048 | 1| 2985| 72.80%
| | |
n54711 | 1| 2985| 72.80%
| | |
n54705 | 1| 2785| 67.93%
| | |
n12102 | 1| 2785| 67.93%
| | |
bin_to_bcd_uut/bcd_code_24__N_425 | 9| 2316| 56.49%
| | |
data_out_15 | 1| 1686| 41.12%
| | |
data_out_13 | 1| 1686| 41.12%
| | |
bin_to_bcd_uut/n60805 | 4| 1574| 38.39%
| | |
n54713 | 1| 1277| 31.15%
| | |
n54691 | 1| 1108| 27.02%
| | |
n12100 | 1| 1019| 24.85%
| | |
bin_to_bcd_uut/n60645 | 4| 997| 24.32%
| | |
bin_to_bcd_uut/n60633 | 5| 997| 24.32%
| | |
bin_to_bcd_uut/n60666 | 2| 996| 24.29%
| | |
bin_to_bcd_uut/n60657 | 4| 996| 24.29%
| | |
bin_to_bcd_uut/n60679 | 3| 996| 24.29%
| | |
bin_to_bcd_uut/n60746 | 5| 996| 24.29%
| | |
bin_to_bcd_uut/n60728 | 3| 996| 24.29%
| | |
bin_to_bcd_uut/bcd_code_24__N_541 | 10| 991| 24.17%
| | |
bin_to_bcd_uut/n60827 | 3| 990| 24.15%
| | |
bin_to_bcd_uut/bcd_code_24__N_434 | 9| 990| 24.15%
| | |
bin_to_bcd_uut/bcd_code_24__N_499 | 10| 987| 24.07%
| | |
bin_to_bcd_uut/bcd_code_24__N_463 | 10| 958| 23.37%
| | |
bin_to_bcd_uut/n60830 | 4| 917| 22.37%
| | |
bin_to_bcd_uut/n60847 | 5| 906| 22.10%
| | |
n12046 | 1| 877| 21.39%
| | |
bin_to_bcd_uut/bcd_code_24__N_429 | 5| 787| 19.20%
| | |
data_out_11 | 1| 721| 17.59%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 30 clocks:
Clock Domain: control_module_uut/clk_c_generated_9 Source: SLICE_1525.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_7 Source: control_module_uut/SLICE_1440.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_6 Source: control_module_uut/SLICE_1444.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_5 Source: control_module_uut/SLICE_1441.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_4 Source: control_module_uut/SLICE_1442.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_3 Source: control_module_uut/SLICE_1445.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_28 Source: control_module_uut/SLICE_1446.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_27 Source: control_module_uut/SLICE_1447.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_26 Source: control_module_uut/SLICE_1434.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_25 Source: control_module_uut/SLICE_1532.F0 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_24 Source: control_module_uut/SLICE_1533.F0 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_23 Source: control_module_uut/SLICE_1534.F0 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_22 Source: control_module_uut/SLICE_1534.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_21 Source: control_module_uut/SLICE_1435.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_20 Source: control_module_uut/SLICE_1436.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_19 Source: control_module_uut/SLICE_1437.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_18 Source: control_module_uut/SLICE_1533.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_17 Source: control_module_uut/SLICE_1532.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_16 Source: control_module_uut/SLICE_1531.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_15 Source: control_module_uut/SLICE_1530.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_14 Source: control_module_uut/SLICE_1438.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_13 Source: control_module_uut/SLICE_1439.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_12 Source: control_module_uut/SLICE_1443.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_11 Source: control_module_uut/SLICE_1527.F0 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_10 Source: control_module_uut/SLICE_1527.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_1 Source: control_module_uut/SLICE_1433.F0 Loads: 2
No transfer within this clock domain is found
Clock Domain: clk_c_generated_8 Source: SLICE_1525.F0 Loads: 2
Covered under: FREQUENCY NET "clk_c_generated_8" 399.840000 MHz ;
Data transfers from:
Clock Domain: clk_c Source: clk.PAD
Covered under: FREQUENCY NET "clk_c_generated_8" 399.840000 MHz ; Transfers: 3
Clock Domain: clk_c_generated_2 Source: SLICE_1431.F0 Loads: 2
No transfer within this clock domain is found
Clock Domain: clk_c Source: clk.PAD Loads: 531
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ;
Data transfers from:
Clock Domain: control_module_uut/clk_c_generated_9 Source: SLICE_1525.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_7 Source: control_module_uut/SLICE_1440.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_6 Source: control_module_uut/SLICE_1444.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_5 Source: control_module_uut/SLICE_1441.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_4 Source: control_module_uut/SLICE_1442.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_3 Source: control_module_uut/SLICE_1445.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_28 Source: control_module_uut/SLICE_1446.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_27 Source: control_module_uut/SLICE_1447.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_26 Source: control_module_uut/SLICE_1434.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_25 Source: control_module_uut/SLICE_1532.F0
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_24 Source: control_module_uut/SLICE_1533.F0
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_23 Source: control_module_uut/SLICE_1534.F0
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_22 Source: control_module_uut/SLICE_1534.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_21 Source: control_module_uut/SLICE_1435.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_20 Source: control_module_uut/SLICE_1436.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_19 Source: control_module_uut/SLICE_1437.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_18 Source: control_module_uut/SLICE_1533.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_17 Source: control_module_uut/SLICE_1532.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_16 Source: control_module_uut/SLICE_1531.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_15 Source: control_module_uut/SLICE_1530.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_14 Source: control_module_uut/SLICE_1438.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_13 Source: control_module_uut/SLICE_1439.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_12 Source: control_module_uut/SLICE_1443.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_11 Source: control_module_uut/SLICE_1527.F0
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_10 Source: control_module_uut/SLICE_1527.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_1 Source: control_module_uut/SLICE_1433.F0
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: clk_c_generated_8 Source: SLICE_1525.F0
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: clk_c_generated_2 Source: SLICE_1431.F0
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: DS18B20Z_uut/clk_1mhz Source: DS18B20Z_uut/SLICE_228.Q0 Loads: 11
No transfer within this clock domain is found
Timing summary (Setup):
---------------
Timing errors: 4100 Score: 133774210
Cumulative negative slack: 133774210
Constraints cover 2147483647 paths, 2 nets, and 11499 connections (93.59% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.11.0.396.4
Thu Feb 18 17:27:51 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o step_project01_impl1.tw1 -gui -msgset C:/Users/CROFY/Documents/Diamond/Project/step_project01/promote.xml step_project01_impl1_map.ncd step_project01_impl1.prf
Design file: step_project01_impl1_map.ncd
Preference file: step_project01_impl1.prf
Device,speed: LCMXO2-4000HC,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "clk_c" 23.368000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
FREQUENCY NET "clk_c_generated_8" 399.840000 MHz (0 errors) 4 items scored, 0 timing errors detected.
28 potential circuit loops found in timing analysis.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "clk_c" 23.368000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.351ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q u1/Uart_Rx_uut/uart_rx0_46 (from clk_c +)
Destination: FF Data in u1/Uart_Rx_uut/uart_rx1_47 (to clk_c +)
Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
Constraint Details:
0.332ns physical path delay SLICE_656 to SLICE_656 meets
-0.019ns M_HLD and
0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
Physical Path Details:
Data path SLICE_656 to SLICE_656:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 SLICE_656.CLK to SLICE_656.Q0 SLICE_656 (from clk_c)
ROUTE 1 e 0.199 SLICE_656.Q0 to SLICE_656.M1 u1/Uart_Rx_uut/uart_rx0 (to clk_c)
--------
0.332 (40.1% logic, 59.9% route), 1 logic levels.
================================================================================
Preference: FREQUENCY NET "clk_c_generated_8" 399.840000 MHz ;
4 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.264ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q control_module_uut/tone_flag_330_rep_938 (from clk_c +)
Destination: FF Data in control_module_uut/i23195 (to clk_c_generated_8 +)
Delay: 1.264ns (18.5% logic, 81.5% route), 2 logic levels.
Constraint Details:
1.264ns physical path delay SLICE_1207 to control_module_uut/SLICE_608 meets
(delay constraint based on source clock period of 42.794ns and destination clock period of 2.501ns)
0.000ns LSRREC_HLD and
0.000ns delay constraint requirement (totaling 0.000ns) by 1.264ns
Physical Path Details:
Data path SLICE_1207 to control_module_uut/SLICE_608:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 SLICE_1207.CLK to SLICE_1207.Q0 SLICE_1207 (from clk_c)
ROUTE 68 e 0.515 SLICE_1207.Q0 to *SLICE_1488.B1 n62436
CTOF_DEL --- 0.101 *SLICE_1488.B1 to *SLICE_1488.F1 control_module_uut/SLICE_1488
ROUTE 2 e 0.515 *SLICE_1488.F1 to *SLICE_608.LSR control_module_uut/temp_out_31__N_1883 (to clk_c_generated_8)
--------
1.264 (18.5% logic, 81.5% route), 2 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_c" 23.368000 MHz ; | 0.000 ns| 0.351 ns| 1
| | |
FREQUENCY NET "clk_c_generated_8" | | |
399.840000 MHz ; | 0.000 ns| 1.264 ns| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 30 clocks:
Clock Domain: control_module_uut/clk_c_generated_9 Source: SLICE_1525.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_7 Source: control_module_uut/SLICE_1440.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_6 Source: control_module_uut/SLICE_1444.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_5 Source: control_module_uut/SLICE_1441.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_4 Source: control_module_uut/SLICE_1442.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_3 Source: control_module_uut/SLICE_1445.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_28 Source: control_module_uut/SLICE_1446.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_27 Source: control_module_uut/SLICE_1447.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_26 Source: control_module_uut/SLICE_1434.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_25 Source: control_module_uut/SLICE_1532.F0 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_24 Source: control_module_uut/SLICE_1533.F0 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_23 Source: control_module_uut/SLICE_1534.F0 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_22 Source: control_module_uut/SLICE_1534.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_21 Source: control_module_uut/SLICE_1435.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_20 Source: control_module_uut/SLICE_1436.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_19 Source: control_module_uut/SLICE_1437.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_18 Source: control_module_uut/SLICE_1533.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_17 Source: control_module_uut/SLICE_1532.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_16 Source: control_module_uut/SLICE_1531.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_15 Source: control_module_uut/SLICE_1530.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_14 Source: control_module_uut/SLICE_1438.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_13 Source: control_module_uut/SLICE_1439.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_12 Source: control_module_uut/SLICE_1443.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_11 Source: control_module_uut/SLICE_1527.F0 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_10 Source: control_module_uut/SLICE_1527.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: control_module_uut/clk_c_generated_1 Source: control_module_uut/SLICE_1433.F0 Loads: 2
No transfer within this clock domain is found
Clock Domain: clk_c_generated_8 Source: SLICE_1525.F0 Loads: 2
Covered under: FREQUENCY NET "clk_c_generated_8" 399.840000 MHz ;
Data transfers from:
Clock Domain: clk_c Source: clk.PAD
Covered under: FREQUENCY NET "clk_c_generated_8" 399.840000 MHz ; Transfers: 3
Clock Domain: clk_c_generated_2 Source: SLICE_1431.F0 Loads: 2
No transfer within this clock domain is found
Clock Domain: clk_c Source: clk.PAD Loads: 531
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ;
Data transfers from:
Clock Domain: control_module_uut/clk_c_generated_9 Source: SLICE_1525.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_7 Source: control_module_uut/SLICE_1440.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_6 Source: control_module_uut/SLICE_1444.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_5 Source: control_module_uut/SLICE_1441.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_4 Source: control_module_uut/SLICE_1442.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_3 Source: control_module_uut/SLICE_1445.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_28 Source: control_module_uut/SLICE_1446.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_27 Source: control_module_uut/SLICE_1447.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_26 Source: control_module_uut/SLICE_1434.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_25 Source: control_module_uut/SLICE_1532.F0
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_24 Source: control_module_uut/SLICE_1533.F0
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_23 Source: control_module_uut/SLICE_1534.F0
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_22 Source: control_module_uut/SLICE_1534.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_21 Source: control_module_uut/SLICE_1435.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_20 Source: control_module_uut/SLICE_1436.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_19 Source: control_module_uut/SLICE_1437.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_18 Source: control_module_uut/SLICE_1533.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_17 Source: control_module_uut/SLICE_1532.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_16 Source: control_module_uut/SLICE_1531.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_15 Source: control_module_uut/SLICE_1530.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_14 Source: control_module_uut/SLICE_1438.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_13 Source: control_module_uut/SLICE_1439.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_12 Source: control_module_uut/SLICE_1443.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_11 Source: control_module_uut/SLICE_1527.F0
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_10 Source: control_module_uut/SLICE_1527.F1
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: control_module_uut/clk_c_generated_1 Source: control_module_uut/SLICE_1433.F0
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: clk_c_generated_8 Source: SLICE_1525.F0
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: clk_c_generated_2 Source: SLICE_1431.F0
Covered under: FREQUENCY NET "clk_c" 23.368000 MHz ; Transfers: 1
Clock Domain: DS18B20Z_uut/clk_1mhz Source: DS18B20Z_uut/SLICE_228.Q0 Loads: 11
No transfer within this clock domain is found
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 2147483647 paths, 2 nets, and 12007 connections (97.73% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 4100 (setup), 0 (hold)
Score: 133774210 (setup), 0 (hold)
Cumulative negative slack: 133774210 (133774210+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------