PAR: Place And Route Diamond (64-bit) 3.11.0.396.4. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. Thu Feb 18 17:27:52 2021 C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f step_project01_impl1.p2t step_project01_impl1_map.ncd step_project01_impl1.dir step_project01_impl1.prf -gui -msgset C:/Users/CROFY/Documents/Diamond/Project/step_project01/promote.xml Preference file: step_project01_impl1.prf. Cost Table Summary Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ 5_1 * 0 -2095.516 154691890 -1.944 5297 29 Completed * : Design saved. Total (real) run time for 1-seed: 29 secs par done! Note: user must run 'Trace' for timing closure signoff. Lattice Place and Route Report for Design "step_project01_impl1_map.ncd" Thu Feb 18 17:27:52 2021 Best Par Run PAR: Place And Route Diamond (64-bit) 3.11.0.396.4. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/CROFY/Documents/Diamond/Project/step_project01/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF step_project01_impl1_map.ncd step_project01_impl1.dir/5_1.ncd step_project01_impl1.prf Preference file: step_project01_impl1.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file step_project01_impl1_map.ncd. Design name: step_project01 NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-4000HC Package: CSBGA132 Performance: 4 Loading device for application par from file 'xo2c4000.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga. Package Status: Final Version 1.44. Performance Hardware Data Status: Final Version 34.4. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 14+4(JTAG)/280 6% used 14+4(JTAG)/105 17% bonded SLICE 1451/2160 67% used GSR 1/1 100% used 28 potential circuit loops found in timing analysis. Number of Signals: 3729 Number of Connections: 12286 WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors. Pin Constraint Summary: 14 out of 14 pins locked (100% locked). The following 1 signal is selected to use the primary clock routing resources: clk_c (driver: clk, clk load #: 531) WARNING - par: Signal "clk_c" is selected to use Primary clock resources. However, its driver comp "clk" is located at "C1", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. The following 8 signals are selected to use the secondary clock routing resources: control_module_uut/clk_c_enable_463 (driver: control_module_uut/SLICE_1492, clk load #: 0, sr load #: 0, ce load #: 140) control_module_uut/cnt_1m_29__N_2443 (driver: control_module_uut/SLICE_108, clk load #: 0, sr load #: 16, ce load #: 0) control_module_uut/tone_flag (driver: SLICE_579, clk load #: 0, sr load #: 1, ce load #: 14) control_module_uut/pwm_flag (driver: control_module_uut/SLICE_438, clk load #: 0, sr load #: 0, ce load #: 15) cnt_uart_23__N_2748 (driver: SLICE_1126, clk load #: 0, sr load #: 13, ce load #: 0) clk_c_enable_112 (driver: SLICE_1126, clk load #: 0, sr load #: 0, ce load #: 13) DS18B20Z_uut/clk_c_enable_545 (driver: DS18B20Z_uut/SLICE_1081, clk load #: 0, sr load #: 0, ce load #: 11) key_debounce_uut/cnt_17__N_1737 (driver: SLICE_1214, clk load #: 0, sr load #: 10, ce load #: 0) Signal rst_n_c is selected as Global Set/Reset. Starting Placer Phase 0. ........... Finished Placer Phase 0. REAL time: 6 secs Starting Placer Phase 1. .................... Placer score = 1402353. Finished Placer Phase 1. REAL time: 16 secs Starting Placer Phase 2. . Placer score = 1337056 Finished Placer Phase 2. REAL time: 16 secs Clock Report Global Clock Resources: CLK_PIN : 0 out of 8 (0%) General PIO: 1 out of 280 (0%) PLL : 0 out of 2 (0%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Global Clocks: PRIMARY "clk_c" from comp "clk" on PIO site "C1 (PL4A)", clk load = 531 SECONDARY "control_module_uut/clk_c_enable_463" from F0 on comp "control_module_uut/SLICE_1492" on site "R12C17C", clk load = 0, ce load = 140, sr load = 0 SECONDARY "control_module_uut/cnt_1m_29__N_2443" from F1 on comp "control_module_uut/SLICE_108" on site "R2C14C", clk load = 0, ce load = 0, sr load = 16 SECONDARY "control_module_uut/tone_flag" from Q0 on comp "SLICE_579" on site "R12C15D", clk load = 0, ce load = 14, sr load = 1 SECONDARY "control_module_uut/pwm_flag" from Q0 on comp "control_module_uut/SLICE_438" on site "R20C10B", clk load = 0, ce load = 15, sr load = 0 SECONDARY "cnt_uart_23__N_2748" from F1 on comp "SLICE_1126" on site "R9C31D", clk load = 0, ce load = 0, sr load = 13 SECONDARY "clk_c_enable_112" from F0 on comp "SLICE_1126" on site "R9C31D", clk load = 0, ce load = 13, sr load = 0 SECONDARY "DS18B20Z_uut/clk_c_enable_545" from F0 on comp "DS18B20Z_uut/SLICE_1081" on site "R12C17B", clk load = 0, ce load = 11, sr load = 0 SECONDARY "key_debounce_uut/cnt_17__N_1737" from F0 on comp "SLICE_1214" on site "R12C17A", clk load = 0, ce load = 0, sr load = 10 PRIMARY : 1 out of 8 (12%) SECONDARY: 8 out of 8 (100%) Edge Clocks: No edge clock selected. I/O Usage Summary (final): 14 + 4(JTAG) out of 280 (6.4%) PIO sites used. 14 + 4(JTAG) out of 105 (17.1%) bonded PIO sites used. Number of PIO comps: 14; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+---------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+---------------+------------+-----------+ | 0 | 2 / 26 ( 7%) | 3.3V | - | | 1 | 9 / 26 ( 34%) | 3.3V | - | | 2 | 2 / 28 ( 7%) | 3.3V | - | | 3 | 0 / 7 ( 0%) | - | - | | 4 | 0 / 8 ( 0%) | - | - | | 5 | 1 / 10 ( 10%) | 3.3V | - | +----------+---------------+------------+-----------+ Total placer CPU time: 16 secs Dumping design to file step_project01_impl1.dir/5_1.ncd. 28 potential circuit loops found in timing analysis. 0 connections routed; 12286 unrouted. Starting router resource preassignment WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Signal=clk_c_generated_8 loads=2 clock_loads=1 Signal=clk_c_generated_2 loads=2 clock_loads=1 Signal=DS18B20Z_uut/clk_1mhz loads=11 clock_loads=2 Signal=control_module_uut/clk_c_generated_1 loads=2 clock_loads=1 Signal=control_module_uut/clk_c_generated_11 loads=2 clock_loads=1 Signal=control_module_uut/c .... _26 loads=2 clock_loads=1 Signal=control_module_uut/clk_c_generated_27 loads=2 clock_loads=1 Signal=control_module_uut/clk_c_generated_28 loads=2 clock_loads=1 Completed router resource preassignment. Real time: 20 secs Start NBR router at 17:28:13 02/18/21 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** 28 potential circuit loops found in timing analysis. Start NBR special constraint process at 17:28:13 02/18/21 Start NBR section for initial routing at 17:28:13 02/18/21 Level 1, iteration 1 0(0.00%) conflict; 10145(82.57%) untouched conns; 52003470 (nbr) score; Estimated worst slack/total negative slack<setup>: -3056.374ns/-52003.471ns; real time: 22 secs Level 2, iteration 1 0(0.00%) conflict; 10145(82.57%) untouched conns; 52003470 (nbr) score; Estimated worst slack/total negative slack<setup>: -3056.374ns/-52003.471ns; real time: 22 secs Level 3, iteration 1 0(0.00%) conflict; 10145(82.57%) untouched conns; 52003470 (nbr) score; Estimated worst slack/total negative slack<setup>: -3056.374ns/-52003.471ns; real time: 22 secs Level 4, iteration 1 351(0.15%) conflicts; 0(0.00%) untouched conn; 64003236 (nbr) score; Estimated worst slack/total negative slack<setup>: -2776.796ns/-64003.237ns; real time: 23 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) Start NBR section for normal routing at 17:28:15 02/18/21 Level 4, iteration 1 184(0.08%) conflicts; 0(0.00%) untouched conn; 63166694 (nbr) score; Estimated worst slack/total negative slack<setup>: -2753.314ns/-63166.694ns; real time: 24 secs Level 4, iteration 2 89(0.04%) conflicts; 0(0.00%) untouched conn; 72999616 (nbr) score; Estimated worst slack/total negative slack<setup>: -4186.680ns/-72999.616ns; real time: 24 secs Level 4, iteration 3 44(0.02%) conflicts; 0(0.00%) untouched conn; 73008851 (nbr) score; Estimated worst slack/total negative slack<setup>: -4186.680ns/-73008.851ns; real time: 24 secs Level 4, iteration 4 24(0.01%) conflicts; 0(0.00%) untouched conn; 73008851 (nbr) score; Estimated worst slack/total negative slack<setup>: -4186.680ns/-73008.851ns; real time: 24 secs Level 4, iteration 5 18(0.01%) conflicts; 0(0.00%) untouched conn; 73179029 (nbr) score; Estimated worst slack/total negative slack<setup>: -4193.456ns/-73179.029ns; real time: 25 secs Level 4, iteration 6 15(0.01%) conflicts; 0(0.00%) untouched conn; 73179029 (nbr) score; Estimated worst slack/total negative slack<setup>: -4193.456ns/-73179.029ns; real time: 25 secs Level 4, iteration 7 13(0.01%) conflicts; 0(0.00%) untouched conn; 73168026 (nbr) score; Estimated worst slack/total negative slack<setup>: -4191.602ns/-73168.026ns; real time: 25 secs Level 4, iteration 8 9(0.00%) conflicts; 0(0.00%) untouched conn; 73168026 (nbr) score; Estimated worst slack/total negative slack<setup>: -4191.602ns/-73168.026ns; real time: 25 secs Level 4, iteration 9 6(0.00%) conflicts; 0(0.00%) untouched conn; 73167593 (nbr) score; Estimated worst slack/total negative slack<setup>: -4191.602ns/-73167.593ns; real time: 25 secs Level 4, iteration 10 6(0.00%) conflicts; 0(0.00%) untouched conn; 73167593 (nbr) score; Estimated worst slack/total negative slack<setup>: -4191.602ns/-73167.593ns; real time: 25 secs Level 4, iteration 11 5(0.00%) conflicts; 0(0.00%) untouched conn; 73167593 (nbr) score; Estimated worst slack/total negative slack<setup>: -4191.602ns/-73167.593ns; real time: 25 secs Level 4, iteration 12 4(0.00%) conflicts; 0(0.00%) untouched conn; 73167593 (nbr) score; Estimated worst slack/total negative slack<setup>: -4191.602ns/-73167.593ns; real time: 25 secs Level 4, iteration 13 3(0.00%) conflicts; 0(0.00%) untouched conn; 73167593 (nbr) score; Estimated worst slack/total negative slack<setup>: -4191.602ns/-73167.593ns; real time: 25 secs Level 4, iteration 14 3(0.00%) conflicts; 0(0.00%) untouched conn; 73167593 (nbr) score; Estimated worst slack/total negative slack<setup>: -4191.602ns/-73167.593ns; real time: 25 secs Level 4, iteration 15 2(0.00%) conflicts; 0(0.00%) untouched conn; 73167593 (nbr) score; Estimated worst slack/total negative slack<setup>: -4191.602ns/-73167.593ns; real time: 26 secs Level 4, iteration 16 1(0.00%) conflict; 0(0.00%) untouched conn; 73167593 (nbr) score; Estimated worst slack/total negative slack<setup>: -4191.602ns/-73167.593ns; real time: 26 secs Level 4, iteration 17 0(0.00%) conflict; 0(0.00%) untouched conn; 73171848 (nbr) score; Estimated worst slack/total negative slack<setup>: -4191.602ns/-73171.848ns; real time: 26 secs Start NBR section for performance tuning (iteration 1) at 17:28:18 02/18/21 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 73171848 (nbr) score; Estimated worst slack/total negative slack<setup>: -4191.602ns/-73171.848ns; real time: 26 secs Start NBR section for re-routing at 17:28:18 02/18/21 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 73175690 (nbr) score; Estimated worst slack/total negative slack<setup>: -4191.602ns/-73175.691ns; real time: 26 secs Start NBR section for post-routing at 17:28:18 02/18/21 28 potential circuit loops found in timing analysis. End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 1558 (12.68%) Estimated worst slack<setup> : -4191.602ns Timing score<setup> : 154691890 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Signal=clk_c_generated_8 loads=2 clock_loads=1 Signal=clk_c_generated_2 loads=2 clock_loads=1 Signal=DS18B20Z_uut/clk_1mhz loads=11 clock_loads=2 Signal=control_module_uut/clk_c_generated_1 loads=2 clock_loads=1 Signal=control_module_uut/clk_c_generated_11 loads=2 clock_loads=1 Signal=control_module_uut/c .... _26 loads=2 clock_loads=1 Signal=control_module_uut/clk_c_generated_27 loads=2 clock_loads=1 Signal=control_module_uut/clk_c_generated_28 loads=2 clock_loads=1 28 potential circuit loops found in timing analysis. 28 potential circuit loops found in timing analysis. 28 potential circuit loops found in timing analysis. Total CPU time 28 secs Total REAL time: 29 secs Completely routed. End of route. 12286 routed (100.00%); 0 unrouted. Hold time timing score: 5, hold timing errors: 3 Timing score: 154691890 Dumping design to file step_project01_impl1.dir/5_1.ncd. All signals are completely routed. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack<setup/<ns>> = -2095.516 PAR_SUMMARY::Timing score<setup/<ns>> = 154691.890 PAR_SUMMARY::Worst slack<hold /<ns>> = -1.944 PAR_SUMMARY::Timing score<hold /<ns>> = 5.297 PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 29 secs Total REAL time to completion: 29 secs par done! Note: user must run 'Trace' for timing closure signoff. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.