Project Settings |
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Project Name | proj_1 | Device Name | impl_1: Lattice iCE40UP : iCE40UP5K |
Implementation Name | impl_1 | Top Module | ADC_top |
Pipelining | 1 | Retiming | 0 |
Resource Sharing | 1 | Fanout Guide | 1000 |
Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
Clock Conversion | 0 | FSM Compiler | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
(compiler) | Complete |
42 |
7 |
0 |
- |
00m:02s |
- |
9/24/2018 3:06:07 PM |
(premap) | Complete |
3 |
1 |
0 |
0m:00s |
0m:00s |
134MB |
9/24/2018 3:06:10 PM |
(fpga_mapper) | Complete |
7 |
2 |
0 |
0m:01s |
0m:01s |
134MB |
9/24/2018 3:06:12 PM |
Multi-srs Generator |
Complete | | | | 00m:01s | | | 9/24/2018 3:06:09 PM |
Area Summary |
|
PADS | 13 |
FLOPS | 63 |
RAMS
(v_ram) | 0 |
CARRYS | 18 |
LUTS
(total_luts) | 36 |
| |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
ADC_top|i_clk_in | 300.5 MHz | NA | NA |
System | 174.3 MHz | 148.1 MHz | -1.013 |
Optimizations Summary |
Combined Clock Conversion | 1 / 0 |
| |
|