Synthesis Report #Build: Synplify Pro (R) M-2017.03LR-SP1-1, Build 229R, Nov 10 2017 #install: C:\lscc\radiant\1.0\synpbase #OS: Windows 7 6.1 #Hostname: L-8QVD562 # Mon Sep 24 15:06:05 2018 #Implementation: impl_1 Synopsys HDL Compiler, version comp2017q2p1, Build 338R, built Nov 10 2017 @N|Running in 64-bit mode Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Synopsys VHDL Compiler, version comp2017q2p1, Build 338R, built Nov 10 2017 @N|Running in 64-bit mode Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @N: CD720 :"C:\lscc\radiant\1.0\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ps Pre Loading Built-In Library pmi ... @N:Can't find top module! Top entity isn't set yet! VHDL syntax check successful! At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) Process completed successfully. # Mon Sep 24 15:06:06 2018 ###########################################################] Synopsys Verilog Compiler, version comp2017q2p1, Build 338R, built Nov 10 2017 @N|Running in 64-bit mode Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @I::"C:\lscc\radiant\1.0\synpbase\lib\generic\ice40up.v" (library work) @I::"C:\lscc\radiant\1.0\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\lscc\radiant\1.0\synpbase\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\lscc\radiant\1.0\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\lscc\radiant\1.0\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\lscc\radiant\1.0\ip\pmi\pmi.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_add.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi_add.v":"C:\lscc\radiant\1.0\ip\pmi\../common/adder/rtl\lscc_adder.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_complex_mult.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi_complex_mult.v":"C:\lscc\radiant\1.0\ip\pmi\../common/complex_mult/rtl\lscc_complex_mult.v" (library work) @N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_complex_mult.v":89:11:89:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_complex_mult.v":98:11:98:22|Read directive translate_on. @I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_dsp.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_mac.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi_mac.v":"C:\lscc\radiant\1.0\ip\pmi\../common/mult_accumulate/rtl\lscc_mult_accumulate.v" (library work) @N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_mac.v":91:11:91:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_mac.v":106:11:106:22|Read directive translate_on. @I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_multaddsub.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi_multaddsub.v":"C:\lscc\radiant\1.0\ip\pmi\../common/mult_add_sub/rtl\lscc_mult_add_sub.v" (library work) @N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_multaddsub.v":88:11:88:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_multaddsub.v":97:11:97:22|Read directive translate_on. @I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_mult.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi_mult.v":"C:\lscc\radiant\1.0\ip\pmi\../common/multiplier/rtl\lscc_multiplier.v" (library work) @N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_mult.v":84:11:84:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_mult.v":93:11:93:22|Read directive translate_on. @I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dp.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\1.0\ip\pmi\../common/ram_dp/rtl\lscc_ram_dp.v" (library work) @N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dp.v":95:11:95:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dp.v":150:11:150:22|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dp.v":194:11:194:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dp.v":201:11:201:22|Read directive translate_on. @I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dq.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\1.0\ip\pmi\../common/ram_dq/rtl\lscc_ram_dq.v" (library work) @N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dq.v":82:11:82:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dq.v":91:11:91:22|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dq.v":129:11:129:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dq.v":136:11:136:22|Read directive translate_on. @I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_sub.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi_sub.v":"C:\lscc\radiant\1.0\ip\pmi\../common/subtractor/rtl\lscc_subtractor.v" (library work) @I::"D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\source\verilog\radiant\adc_top.v" (library work) @W: CG1337 :"D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\source\verilog\radiant\adc_top.v":138:10:138:14|Net rst_i is not declared. @I::"D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\source\verilog\radiant\sigmadelta_adc_ice40.v" (library work) @I::"D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\source\verilog\radiant\box_ave.v" (library work) Verilog syntax check successful! At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) Process completed successfully. # Mon Sep 24 15:06:06 2018 ###########################################################] @I::"C:\lscc\radiant\1.0\synpbase\lib\generic\ice40up.v" (library work) @I::"C:\lscc\radiant\1.0\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\lscc\radiant\1.0\synpbase\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\lscc\radiant\1.0\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\lscc\radiant\1.0\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\lscc\radiant\1.0\ip\pmi\pmi.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_add.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi_add.v":"C:\lscc\radiant\1.0\ip\pmi\../common/adder/rtl\lscc_adder.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_complex_mult.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi_complex_mult.v":"C:\lscc\radiant\1.0\ip\pmi\../common/complex_mult/rtl\lscc_complex_mult.v" (library work) @N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_complex_mult.v":89:11:89:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_complex_mult.v":98:11:98:22|Read directive translate_on. @I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_dsp.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_mac.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi_mac.v":"C:\lscc\radiant\1.0\ip\pmi\../common/mult_accumulate/rtl\lscc_mult_accumulate.v" (library work) @N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_mac.v":91:11:91:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_mac.v":106:11:106:22|Read directive translate_on. @I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_multaddsub.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi_multaddsub.v":"C:\lscc\radiant\1.0\ip\pmi\../common/mult_add_sub/rtl\lscc_mult_add_sub.v" (library work) @N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_multaddsub.v":88:11:88:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_multaddsub.v":97:11:97:22|Read directive translate_on. @I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_mult.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi_mult.v":"C:\lscc\radiant\1.0\ip\pmi\../common/multiplier/rtl\lscc_multiplier.v" (library work) @N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_mult.v":84:11:84:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_mult.v":93:11:93:22|Read directive translate_on. @I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dp.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\1.0\ip\pmi\../common/ram_dp/rtl\lscc_ram_dp.v" (library work) @N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dp.v":95:11:95:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dp.v":150:11:150:22|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dp.v":194:11:194:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dp.v":201:11:201:22|Read directive translate_on. @I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dq.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\1.0\ip\pmi\../common/ram_dq/rtl\lscc_ram_dq.v" (library work) @N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dq.v":82:11:82:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dq.v":91:11:91:22|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dq.v":129:11:129:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dq.v":136:11:136:22|Read directive translate_on. @I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_sub.v" (library work) @I:"C:\lscc\radiant\1.0\ip\pmi\pmi_sub.v":"C:\lscc\radiant\1.0\ip\pmi\../common/subtractor/rtl\lscc_subtractor.v" (library work) @I::"D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\source\verilog\radiant\adc_top.v" (library work) @W: CG1337 :"D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\source\verilog\radiant\adc_top.v":138:10:138:14|Net rst_i is not declared. @I::"D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\source\verilog\radiant\sigmadelta_adc_ice40.v" (library work) @I::"D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\source\verilog\radiant\box_ave.v" (library work) Verilog syntax check successful! @N: CG364 :"C:\lscc\radiant\1.0\synpbase\lib\generic\ice40up.v":348:7:348:11|Synthesizing module IOL_B in library work. @N: CG364 :"D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\source\verilog\radiant\box_ave.v":62:7:62:13|Synthesizing module box_ave in library work. ADC_WIDTH=32'b00000000000000000000000000001000 LPF_DEPTH_BITS=32'b00000000000000000000000000000011 Generated name = box_ave_8s_3s @N: CG364 :"D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\source\verilog\radiant\sigmadelta_adc_ice40.v":62:7:62:20|Synthesizing module sigmadelta_adc in library work. ADC_WIDTH=32'b00000000000000000000000000001000 ACCUM_BITS=32'b00000000000000000000000000001010 LPF_DEPTH_BITS=32'b00000000000000000000000000000011 Generated name = sigmadelta_adc_8s_10s_3s @W: CG781 :"D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\source\verilog\radiant\sigmadelta_adc_ice40.v":124:10:124:10|Input DO1 on instance DDRInst0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\source\verilog\radiant\sigmadelta_adc_ice40.v":125:10:125:10|Input DO0 on instance DDRInst0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\source\verilog\radiant\sigmadelta_adc_ice40.v":127:10:127:10|Input IOLTO on instance DDRInst0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\source\verilog\radiant\sigmadelta_adc_ice40.v":128:10:128:10|Input HOLD on instance DDRInst0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\source\verilog\radiant\sigmadelta_adc_ice40.v":130:10:130:10|Input OUTCLK on instance DDRInst0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @N: CG364 :"D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\source\verilog\radiant\adc_top.v":58:7:58:13|Synthesizing module ADC_top in library work. At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 77MB) Process completed successfully. # Mon Sep 24 15:06:07 2018 ###########################################################] Synopsys Netlist Linker, version comp2017q2p1, Build 338R, built Nov 10 2017 @N|Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon Sep 24 15:06:07 2018 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon Sep 24 15:06:07 2018 ###########################################################] Synopsys Netlist Linker, version comp2017q2p1, Build 338R, built Nov 10 2017 @N|Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon Sep 24 15:06:09 2018 ###########################################################] Pre-mapping Report # Mon Sep 24 15:06:09 2018 Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1868R, Built Nov 13 2017 02:40:05 Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version M-2017.03LR-SP1-1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @A: MF827 |No constraint file specified. @L: D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\project\ice40up\verilog\impl_1\ice40up_simple_adc_impl_1_scck.rpt Printing clock summary report in "D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\project\ice40up\verilog\impl_1\ice40up_simple_adc_impl_1_scck.rpt" file @N: MF248 |Running in 64-bit mode. @N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB) syn_allowed_resources : blockrams=30 set on top level netlist ADC_top Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ------------------------------------------------------------------------------------------------------- 0 - System 1.0 MHz 1000.000 system system_clkgroup 0 0 - ADC_top|i_clk_in 146.0 MHz 6.849 inferred Autoconstr_clkgroup_0 63 ======================================================================================================= @W: MT530 :"d:\radiant_porting\adc_deltasigma\simplesigmadeltaadcsourcecode\source\verilog\radiant\box_ave.v":162:0:162:5|Found inferred clock ADC_top|i_clk_in which controls 63 sequential elements including SSD_ADC.box_ave.ave_data_out[7:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N: BN225 |Writing default property annotation file D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\project\ice40up\verilog\impl_1\ice40up_simple_adc_impl_1.sap. Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) None None Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 134MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Sep 24 15:06:10 2018 ###########################################################] Map & Optimize Report # Mon Sep 24 15:06:10 2018 Synopsys Lattice Technology Mapper, Version maplat, Build 1868R, Built Nov 13 2017 02:40:05 Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version M-2017.03LR-SP1-1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N: MF248 |Running in 64-bit mode. @N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) Available hyper_sources - for debug and ip models None Found @N: MT206 |Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) @N: MO231 :"d:\radiant_porting\adc_deltasigma\simplesigmadeltaadcsourcecode\source\verilog\radiant\sigmadelta_adc_ice40.v":149:0:149:5|Found counter in view:work.sigmadelta_adc_8s_10s_3s(verilog) instance sigma[9:0] @N: MO231 :"d:\radiant_porting\adc_deltasigma\simplesigmadeltaadcsourcecode\source\verilog\radiant\sigmadelta_adc_ice40.v":197:0:197:5|Found counter in view:work.sigmadelta_adc_8s_10s_3s(verilog) instance counter[9:0] Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s -1.79ns 64 / 63 2 0h:00m:00s -1.79ns 64 / 63 3 0h:00m:00s -0.39ns 64 / 63 4 0h:00m:00s -0.39ns 64 / 63 5 0h:00m:00s -0.39ns 65 / 63 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 63 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks ============================ Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ---------------------------------------------------------------------------------------- @K:CKID0001 i_clk_in port 63 SSD_ADC.accum[0] ======================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 134MB) Writing Analyst data base D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\project\ice40up\verilog\impl_1\synwork\ice40up_simple_adc_impl_1_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 132MB peak: 134MB) Writing constraint files Finished Writing constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 132MB peak: 134MB) Writing Verilog Simulation files Writing XDC file D:\Radiant_porting\ADC_deltaSigma\SimpleSigmaDeltaADCSourceCode\project\ice40up\verilog\impl_1\ice40up_simple_adc_impl_1.xdc Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 132MB peak: 134MB) Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 134MB) @W: MT246 :"d:\radiant_porting\adc_deltasigma\simplesigmadeltaadcsourcecode\source\verilog\radiant\sigmadelta_adc_ice40.v":122:3:122:10|Blackbox IOL_B is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT420 |Found inferred clock ADC_top|i_clk_in with period 3.33ns. Please declare a user-defined clock on object "p:i_clk_in" ##### START OF TIMING REPORT #####[ # Timing Report written on Mon Sep 24 15:06:12 2018 # Top view: ADC_top Requested Frequency: 300.5 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -1.013 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------------- ADC_top|i_clk_in 300.5 MHz NA 3.328 NA NA inferred Autoconstr_clkgroup_0 System 174.3 MHz 148.1 MHz 5.738 6.751 -1.013 system system_clkgroup ========================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------- System System | 5.738 -1.013 | No paths - | No paths - | No paths - ========================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------- SSD_ADC.box_ave.count[1] System FD1P3DZ Q count[1] 0.796 -1.013 SSD_ADC.box_ave.sample_d1 System FD1P3DZ Q sample_d1 0.796 -1.013 SSD_ADC.box_ave.count[0] System FD1P3DZ Q count[0] 0.796 -0.940 SSD_ADC.box_ave.count[2] System FD1P3DZ Q count[2] 0.796 -0.940 SSD_ADC.box_ave.sample_d2 System FD1P3DZ Q sample_d2 0.796 -0.940 SSD_ADC.rollover System FD1P3DZ Q rollover 0.796 -0.920 SSD_ADC.counter[2] System FD1P3DZ Q counter[2] 0.796 -0.909 SSD_ADC.sigma[0] System FD1P3DZ Q sigma[0] 0.796 -0.909 SSD_ADC.sigma[2] System FD1P3DZ Q sigma[2] 0.796 -0.909 SSD_ADC.sigma[1] System FD1P3DZ Q sigma[1] 0.796 -0.868 ================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------- SSD_ADC.box_ave.accum[0] System FD1P3DZ D accum_4[0] 5.583 -1.013 SSD_ADC.box_ave.accum[1] System FD1P3DZ D accum_4[1] 5.583 -1.013 SSD_ADC.box_ave.accum[2] System FD1P3DZ D accum_4[2] 5.583 -1.013 SSD_ADC.box_ave.accum[3] System FD1P3DZ D accum_4[3] 5.583 -1.013 SSD_ADC.box_ave.accum[4] System FD1P3DZ D accum_4[4] 5.583 -1.013 SSD_ADC.box_ave.accum[5] System FD1P3DZ D accum_4[5] 5.583 -1.013 SSD_ADC.box_ave.accum[6] System FD1P3DZ D accum_4[6] 5.583 -1.013 SSD_ADC.box_ave.accum[7] System FD1P3DZ D accum_4[7] 5.583 -1.013 SSD_ADC.box_ave.count[2] System FD1P3DZ D count_3[2] 5.583 -1.013 SSD_ADC.box_ave.ave_data_out[0] System FD1P3DZ SP latch_result 5.583 -0.940 ========================================================================================================== Worst Path Information *********************** Path information for path number 1: Requested Period: 5.738 - Setup time: 0.155 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 5.583 - Propagation time: 6.596 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (critical) : -1.013 Number of logic level(s): 2 Starting point: SSD_ADC.box_ave.count[1] / Q Ending point: SSD_ADC.box_ave.accum[0] / D The start point is clocked by System [rising] on pin CK The end point is clocked by System [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------- SSD_ADC.box_ave.count[1] FD1P3DZ Q Out 0.796 0.796 - count[1] Net - - 1.599 - 7 SSD_ADC.box_ave.count_RNI7N7D[2] LUT4 A In - 2.395 - SSD_ADC.box_ave.count_RNI7N7D[2] LUT4 Z Out 0.661 3.056 - accum10_0 Net - - 1.371 - 8 SSD_ADC.box_ave.accum_RNO[0] LUT4 A In - 4.427 - SSD_ADC.box_ave.accum_RNO[0] LUT4 Z Out 0.661 5.089 - accum_4[0] Net - - 1.507 - 1 SSD_ADC.box_ave.accum[0] FD1P3DZ D In - 6.596 - ================================================================================================== Total path delay (propagation time + setup) of 6.751 is 2.274(33.7%) logic and 4.477(66.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 5.738 - Setup time: 0.155 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 5.583 - Propagation time: 6.596 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (critical) : -1.013 Number of logic level(s): 2 Starting point: SSD_ADC.box_ave.sample_d1 / Q Ending point: SSD_ADC.box_ave.count[2] / D The start point is clocked by System [rising] on pin CK The end point is clocked by System [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- SSD_ADC.box_ave.sample_d1 FD1P3DZ Q Out 0.796 0.796 - sample_d1 Net - - 1.599 - 5 SSD_ADC.box_ave.sample_d2_RNIFK72 LUT4 A In - 2.395 - SSD_ADC.box_ave.sample_d2_RNIFK72 LUT4 Z Out 0.661 3.056 - accumulate Net - - 1.371 - 12 SSD_ADC.box_ave.count_RNO[2] LUT4 A In - 4.427 - SSD_ADC.box_ave.count_RNO[2] LUT4 Z Out 0.661 5.089 - count_3[2] Net - - 1.507 - 1 SSD_ADC.box_ave.count[2] FD1P3DZ D In - 6.596 - =================================================================================================== Total path delay (propagation time + setup) of 6.751 is 2.274(33.7%) logic and 4.477(66.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 5.738 - Setup time: 0.155 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 5.583 - Propagation time: 6.596 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (critical) : -1.013 Number of logic level(s): 2 Starting point: SSD_ADC.box_ave.count[1] / Q Ending point: SSD_ADC.box_ave.accum[7] / D The start point is clocked by System [rising] on pin CK The end point is clocked by System [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------- SSD_ADC.box_ave.count[1] FD1P3DZ Q Out 0.796 0.796 - count[1] Net - - 1.599 - 7 SSD_ADC.box_ave.count_RNI7N7D[2] LUT4 A In - 2.395 - SSD_ADC.box_ave.count_RNI7N7D[2] LUT4 Z Out 0.661 3.056 - accum10_0 Net - - 1.371 - 8 SSD_ADC.box_ave.accum_RNO[7] LUT4 A In - 4.427 - SSD_ADC.box_ave.accum_RNO[7] LUT4 Z Out 0.661 5.089 - accum_4[7] Net - - 1.507 - 1 SSD_ADC.box_ave.accum[7] FD1P3DZ D In - 6.596 - ================================================================================================== Total path delay (propagation time + setup) of 6.751 is 2.274(33.7%) logic and 4.477(66.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 5.738 - Setup time: 0.155 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 5.583 - Propagation time: 6.596 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (critical) : -1.013 Number of logic level(s): 2 Starting point: SSD_ADC.box_ave.count[1] / Q Ending point: SSD_ADC.box_ave.accum[6] / D The start point is clocked by System [rising] on pin CK The end point is clocked by System [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------- SSD_ADC.box_ave.count[1] FD1P3DZ Q Out 0.796 0.796 - count[1] Net - - 1.599 - 7 SSD_ADC.box_ave.count_RNI7N7D[2] LUT4 A In - 2.395 - SSD_ADC.box_ave.count_RNI7N7D[2] LUT4 Z Out 0.661 3.056 - accum10_0 Net - - 1.371 - 8 SSD_ADC.box_ave.accum_RNO[6] LUT4 A In - 4.427 - SSD_ADC.box_ave.accum_RNO[6] LUT4 Z Out 0.661 5.089 - accum_4[6] Net - - 1.507 - 1 SSD_ADC.box_ave.accum[6] FD1P3DZ D In - 6.596 - ================================================================================================== Total path delay (propagation time + setup) of 6.751 is 2.274(33.7%) logic and 4.477(66.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 5.738 - Setup time: 0.155 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 5.583 - Propagation time: 6.596 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (critical) : -1.013 Number of logic level(s): 2 Starting point: SSD_ADC.box_ave.count[1] / Q Ending point: SSD_ADC.box_ave.accum[5] / D The start point is clocked by System [rising] on pin CK The end point is clocked by System [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------- SSD_ADC.box_ave.count[1] FD1P3DZ Q Out 0.796 0.796 - count[1] Net - - 1.599 - 7 SSD_ADC.box_ave.count_RNI7N7D[2] LUT4 A In - 2.395 - SSD_ADC.box_ave.count_RNI7N7D[2] LUT4 Z Out 0.661 3.056 - accum10_0 Net - - 1.371 - 8 SSD_ADC.box_ave.accum_RNO[5] LUT4 A In - 4.427 - SSD_ADC.box_ave.accum_RNO[5] LUT4 Z Out 0.661 5.089 - accum_4[5] Net - - 1.507 - 1 SSD_ADC.box_ave.accum[5] FD1P3DZ D In - 6.596 - ================================================================================================== Total path delay (propagation time + setup) of 6.751 is 2.274(33.7%) logic and 4.477(66.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 134MB) Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 134MB) --------------------------------------- Resource Usage Report for ADC_top Mapping to part: ice40up5ksg48high-performance_1.2v Cell usage: CCU2_B 18 uses FD1P3DZ 63 uses GND 2 uses IOL_B 1 use VCC 2 uses LUT4 36 uses I/O ports: 13 I/O primitives: 13 IB 3 uses OB 10 uses I/O Register bits: 0 Register bits not including I/Os: 63 of 5280 (1%) Total load per clock: ADC_top|i_clk_in: 1 @S |Mapping Summary: Total LUTs: 36 (0%) Distribution of All Consumed LUTs = LUT4 Distribution of All Consumed Luts 36 = 36 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 28MB peak: 134MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Sep 24 15:06:12 2018 ###########################################################]