POSTSYN: Post Synthesis Process Radiant (64-bit) 1.0.0.350.6
Command Line: postsyn -a iCE40UP -p iCE40UP5K -t SG48 -sp High-Performance_1.2V -oc Industrial -top -w -o ice40up_simple_adc_impl_1.udb -gui -msgset D:/Radiant_porting/ADC_deltaSigma/SimpleSigmaDeltaADCSourceCode/project/ice40up/verilog/promote.xml ice40up_simple_adc_impl_1.vm 
   Architecture:     iCE40UP
   Device:           iCE40UP5K
   Package:          SG48
   Performance:      High-Performance_1.2V
Reading input file 'ice40up_simple_adc_impl_1.vm' ...

Loading device for application udb from file 'itpa08.nph' in environment: C:/lscc/radiant/1.0/ispfpga.
Starting design annotation....


Writing output file 'ice40up_simple_adc_impl_1.udb'.
POSTSYN finished successfully.
Total CPU Time: 0 secs 
Total REAL Time: 0 secs 
Peak Memory Usage: 64 MB