Ice40up_simple_adc Project Summary
Implementation Name: impl_1 Performance Grade: High-Performance_1.2V
Strategy Name: Strategy1 Operating conditions: IND
Part Name: iCE40UP5K-SG48I Last Milestone: Gate-Level Simulation File (Passed)
Device Family: iCE40UP Timing Errors: Place & Route, 0 (setup), 0 (hold)
Device Type: iCE40UP5K Project Created: 2018/09/24 18:07:52
Package Type: SG48 Project Updated: 2018/09/24 18:07:52
Project File: D:/Radiant_porting/ADC_deltaSigma/SimpleSigmaDeltaADCSourceCode/project/ice40up/verilog/ice40up_verilog.rdf
Implement Location: D:/Radiant_porting/ADC_deltaSigma/SimpleSigmaDeltaADCSourceCode/project/ice40up/verilog/impl_1
Resource Usage
LUT4: 101 IO Buffers: 0
PFU Register: 63 EBR: 0