Setting log file to 'D:/Radiant_porting/ADC_deltaSigma/SimpleSigmaDeltaADCSourceCode/project/ice40up/verilog/impl_1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file C:/lscc/radiant/1.0/cae_library/synthesis/verilog/iCE40UP.v
(VERI-1482) Analyzing Verilog file D:/Radiant_porting/ADC_deltaSigma/SimpleSigmaDeltaADCSourceCode/source/verilog/radiant/adc_top.v
(VERI-1482) Analyzing Verilog file D:/Radiant_porting/ADC_deltaSigma/SimpleSigmaDeltaADCSourceCode/source/verilog/radiant/sigmadelta_adc_ice40.v
(VERI-1482) Analyzing Verilog file D:/Radiant_porting/ADC_deltaSigma/SimpleSigmaDeltaADCSourceCode/source/verilog/radiant/box_ave.v
INFO - D:/Radiant_porting/ADC_deltaSigma/SimpleSigmaDeltaADCSourceCode/source/verilog/radiant/adc_top.v(58,8-58,15) (VERI-1018) compiling module ADC_top
INFO - D:/Radiant_porting/ADC_deltaSigma/SimpleSigmaDeltaADCSourceCode/source/verilog/radiant/adc_top.v(58,1-174,10) (VERI-9000) elaborating module 'ADC_top'
INFO - D:/Radiant_porting/ADC_deltaSigma/SimpleSigmaDeltaADCSourceCode/source/verilog/radiant/sigmadelta_adc_ice40.v(62,1-209,10) (VERI-9000) elaborating module 'sigmadelta_adc_uniq_1'
INFO - C:/lscc/radiant/1.0/cae_library/synthesis/verilog/iCE40UP.v(339,1-359,10) (VERI-9000) elaborating module 'IOL_B_uniq_1'
INFO - D:/Radiant_porting/ADC_deltaSigma/SimpleSigmaDeltaADCSourceCode/source/verilog/radiant/box_ave.v(62,1-173,10) (VERI-9000) elaborating module 'box_ave_uniq_1'
Done: design load finished with (0) errors, and (0) warnings