Copyright 2015 Lattice Semiconductor Corporation, All Rights Reserved
Mon Sep 24 15:06:17 2018

Command Line: par -w -n 1 -t 1 -s 1 -exp parPathBased=ON \
	ice40up_simple_adc_impl_1_map.udb ice40up_simple_adc_impl_1.udb 


Cost Table Summary
Level/       Number       Worst        Timing       Worst        Timing       Run          Run
Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
----------   --------     -----        ------       -----------  -----------  ----         ------
5_1   *      0            -            -            -            -            10           Success

* : Design saved.

Total (real) run time for 1-seed: 9 secs 

par done!

Lattice Place and Route Report for Design "ice40up_simple_adc_impl_1_map.udb"
Mon Sep 24 15:06:17 2018


Best Par Run
PAR: Place And Route Radiant (64-bit) 1.0.0.350.6.
Command Line: par -w -t 1 -exp parPathBased=ON \
	ice40up_simple_adc_impl_1_map.udb ice40up_simple_adc_impl_1_par.dir/5_1.udb 

Loading ice40up_simple_adc_impl_1_map.udb ...
Loading device for application udb from file 'itpa08.nph' in environment: C:/lscc/radiant/1.0/ispfpga.
Design:  ADC_top
Family:  iCE40UP
Device:  iCE40UP5K
Package: SG48
Performance Grade:   High-Performance_1.2V
Number of Signals: 196
Number of Connections: 483

Device utilization summary:

   SLICE (est.)      55/2640          2% used
     LUT            101/5280          1% used
     REG             63/5280          1% used
   PIO               14/56           25% used
                     14/36           38% bonded
   IOLOGIC            1/56            1% used
   DSP                0/8             0% used
   I2C                0/2             0% used
   HFOSC              0/1             0% used
   LFOSC              0/1             0% used
   LEDDA_IP           0/1             0% used
   RGBA_DRV           0/1             0% used
   FILTER             0/2             0% used
   SRAM               0/4             0% used
   WARMBOOT           0/1             0% used
   SPI                0/2             0% used
   EBR                0/30            0% used
   PLL                0/1             0% used
   RGBOUTBUF          0/3             0% used
   I3C                0/2             0% used
   OPENDRAIN          0/3             0% used

Pin Constraint Summary:
   2 out of 13 pins locked (15% locked).
.
................Finished Placer Phase 0 (HIER).  CPU time: 0 secs , REAL time: 0 secs 


................
Finished Placer Phase 0 (AP).  CPU time: 0 secs , REAL time: 2 secs 

Starting Placer Phase 1. REAL time: 2 secs 
..  ..
....................

Placer score = 12736.

Device SLICE utilization summary after final SLICE packing:
   SLICE             54/2640          2% used

Finished Placer Phase 1.  CPU time: 8 secs , REAL time: 9 secs 

Starting Placer Phase 2.
.

Placer score =  32792
Finished Placer Phase 2.  CPU time: 8 secs , REAL time: 9 secs 



Clock Report

Global Clocks :
  PRIMARY "i_clk_in_c" from comp "i_clk_in" on CLK_PIN site "35 (PR13B)", clk load = 36, ce load = 0, sr load = 0

  PRIMARY  : 1 out of 8 (12%)




I/O Usage Summary (final):
   14 out of 56 (25.0%) PIO sites used.
   14 out of 36 (38.9%) bonded PIO sites used.
   Number of PIO comps: 13; differential: 1
   Number of Vref pins used: 0

I/O Bank Usage Summary:
+----------+---------------+------------+------------+------------+
| I/O Bank | Usage         | Bank Vccio | Bank Vref1 | Bank Vref2 |
+----------+---------------+------------+------------+------------+
| 0        | 3 / 14 ( 21%) | 2.5V       |            |            |
| 1        | 9 / 14 ( 64%) | 3.3V       |            |            |
| 2        | 2 / 8 ( 25%)  | 3.3V       |            |            |
+----------+---------------+------------+------------+------------+

Total Placer CPU time: 8 secs , REAL time: 10 secs 

Writing design to file ice40up_simple_adc_impl_1_par.dir/5_1.udb ...


-----------------------------------------------------------------
INFO - par: ASE feature is off due to non timing-driven settings.  
-----------------------------------------------------------------


Start NBR router at 15:06:26 09/24/18

*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
      in the earlier iterations. In each iteration, it tries to  
      solve the conflicts while keeping the critical connections 
      routed as short as possible. The routing process is said to
      be completed when no conflicts exist and all connections   
      are routed.                                                
Note: NBR uses a different method to calculate timing slacks. The
      worst slack and total negative slack may not be the same as
      that in timing report. You should always run the timing    
      tool to verify your design.                                
*****************************************************************

Starting routing resource preassignment
Preassignment Summary:
--------------------------------------------------------------------------------
94 connections routed with dedicated routing resources
1 global clock signals routed
130 connections routed (of 417 total) (31.18%)
---------------------------------------------------------
Clock routing summary:
Primary clocks (1 used out of 8 available):
#7  Signal "i_clk_in_c"
       Clock   loads: 36    out of    36 routed (100.00%)
---------------------------------------------------------
--------------------------------------------------------------------------------
Completed routing resource preassignment

Start NBR section for initial routing at 15:06:26 09/24/18
Level 4, iteration 1
13(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 

Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area  at 75% usage is 0 (0.00%)

Start NBR section for normal routing at 15:06:26 09/24/18
Level 4, iteration 1
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 
Level 4, iteration 2
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 
Level 4, iteration 3
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 
Level 4, iteration 4
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 

Start NBR section for re-routing at 15:06:26 09/24/18
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 

Start NBR section for post-routing at 15:06:26 09/24/18

End NBR router with 0 unrouted connection

NBR Summary
-----------
  Number of unrouted connections : 0 (0.00%)
  Number of connections with timing violations : 0 (0.00%)
  Estimated worst slack<setup> : <n/a>
  Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only.


---------------------------------------------------------
Clock routing summary:
Primary clocks (1 used out of 8 available):
#7  Signal "i_clk_in_c"
       Clock   loads: 36    out of    36 routed (100.00%)
---------------------------------------------------------
Total CPU time 0 secs 
Total REAL time: 0 secs 
Completely routed.
End of route.  417 routed (100.00%); 0 unrouted.

Writing design to file ice40up_simple_adc_impl_1_par.dir/5_1.udb ...


All signals are completely routed.


PAR_SUMMARY::Run status = Success
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack<setup/<ns>> = <n/a>
PAR_SUMMARY::Timing score<setup/<ns>> = <n/a>
PAR_SUMMARY::Worst  slack<hold /<ns>> = <n/a>
PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>
PAR_SUMMARY::Number of errors = 0

Total CPU  Time: 9 secs 
Total REAL Time: 10 secs 
Peak Memory Usage: 75 MB


par done!

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