Timing Report
Lattice Timing Report -  Setup  and Hold, Version Radiant (64-bit) 1.0.0.350.6

Mon Sep 24 15:06:16 2018

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2018 Lattice Semiconductor Corporation,  All rights reserved.

Command line:    timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -html -rpt ice40up_simple_adc_impl_1.tw1 ice40up_simple_adc_impl_1.udb -gui

-----------------------------------------
Design:          ADC_top
Family:          iCE40UP
Device:          iCE40UP5K
Package:         SG48
Performance:     High-Performance_1.2V
-----------------------------------------


=====================================================================
                    Table of Contents
=====================================================================
  • 1 DESIGN CHECKING
  • 1.1 SDC Constraints
  • 1.2 Combinational Loop
  • 2 CLOCK SUMMARY
  • 3 TIMING ANALYSIS SUMMARY
  • 3.1 Overall (Setup and Hold)
  • 3.1.1 Constraint Coverage
  • 3.1.2 Timing Errors
  • 3.1.3 Total Timing Score
  • 3.2 Setup Summary Report
  • 3.2.1 Setup Constraint Slack Summary
  • 3.2.2 Setup Critical Endpoint Summary
  • 3.3 Hold Summary Report
  • 3.3.1 Hold Constraint Slack Summary
  • 3.3.2 Hold Critical Endpoint Summary
  • 3.4 Unconstrained Report
  • 3.4.1 Unconstrained Start/End Points
  • 3.4.2 Start/End Points Without Timing Constraints
  • 4 DETAILED REPORT
  • 4.1 Setup Detailed Report
  • 4.2 Hold Detailed Report
  • ===================================================================== End of Table of Contents ===================================================================== 1 DESIGN CHECKING 1.1 SDC Constraints 1.2 Combinational Loop 2 CLOCK SUMMARY 3 TIMING ANALYSIS SUMMARY 3.1 Overall (Setup and Hold) 3.1.1 Constraint Coverage Constraint Coverage: 0% 3.1.2 Timing Errors Timing Errors: 0 endpoints (setup), 0 endpoints (hold) 3.1.3 Total Timing Score Total Negative Slack: 0.000 ns (setup), 0.000 ns (hold) 3.2 Setup Summary Report 3.2.1 Setup Constraint Slack Summary ------------------------------------------------------------------------------------------------------------------------------------------- | | | | Actual (flop to flop) | | SDC Constraint | Target | Slack | Levels | Period | Frequency | Items Scored | Timing Error ------------------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------- 3.2.2 Setup Critical Endpoint Summary -------------------------------------------------- There is no end point satisfying reporting criteria Total Negative Slack: 0 3.3 Hold Summary Report 3.3.1 Hold Constraint Slack Summary ------------------------------------------------------------------------------------------------------------------------------------------- | | | | Actual (flop to flop) | | SDC Constraint | Target | Slack | Levels | Period | Frequency | Items Scored | Timing Error ------------------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------- 3.3.2 Hold Critical Endpoint Summary -------------------------------------------------- There is no end point satisfying reporting criteria Total Negative Slack: 0 3.4 Unconstrained Report 3.4.1 Unconstrained Start/End Points Clocked but unconstrained timing start points ------------------------------------------------------------------- Listing 10 Start Points | Type ------------------------------------------------------------------- SSD_ADC/sigma_Z[2].ff_inst/Q | No arrival or required SSD_ADC/counter_Z[9].ff_inst/Q | No arrival or required SSD_ADC/counter_Z[8].ff_inst/Q | No arrival or required SSD_ADC/counter_Z[7].ff_inst/Q | No arrival or required SSD_ADC/counter_Z[6].ff_inst/Q | No arrival or required SSD_ADC/counter_Z[5].ff_inst/Q | No arrival or required SSD_ADC/counter_Z[4].ff_inst/Q | No arrival or required SSD_ADC/counter_Z[3].ff_inst/Q | No arrival or required SSD_ADC/counter_Z[2].ff_inst/Q | No arrival or required SSD_ADC/counter_Z[1].ff_inst/Q | No arrival or required ------------------------------------------------------------------- | Number of unconstrained timing start po | ints | 64 | ------------------------------------------------------------------- Clocked but unconstrained timing end points ------------------------------------------------------------------- Listing 10 End Points | Type ------------------------------------------------------------------- SSD_ADC/counter_Z[9].ff_inst/SR | No arrival or required {SSD_ADC/counter_Z[7].ff_inst/SR SSD_ADC/counter_Z[8].ff_inst/SR} | No arrival or required {SSD_ADC/counter_Z[5].ff_inst/SR SSD_ADC/counter_Z[6].ff_inst/SR} | No arrival or required {SSD_ADC/counter_Z[3].ff_inst/SR SSD_ADC/counter_Z[4].ff_inst/SR} | No arrival or required {SSD_ADC/counter_Z[1].ff_inst/SR SSD_ADC/counter_Z[2].ff_inst/SR} | No arrival or required SSD_ADC/counter_Z[0].ff_inst/SR | No arrival or required SSD_ADC/sigma_Z[2].ff_inst/SR | No arrival or required SSD_ADC/sigma_Z[9].ff_inst/SR | No arrival or required SSD_ADC/sigma_Z[8].ff_inst/SR | No arrival or required SSD_ADC/sigma_Z[7].ff_inst/SR | No arrival or required ------------------------------------------------------------------- | Number of unconstrained timing end poin | ts | 160 | ------------------------------------------------------------------- 3.4.2 Start/End Points Without Timing Constraints I/O ports without constraint ---------------------------- Possible constraints to use on I/O ports are: set_input_delay, set_output_delay, set_max_delay, create_clock, create_generated_clock, ... ------------------------------------------------------------------- Listing 10 Start or End Points | Type ------------------------------------------------------------------- i_analog_cmp | input i_rst_in | input i_clk_in | input o_sample_rdy | output o_analog_out | output o_digital_out[7] | output o_digital_out[6] | output o_digital_out[5] | output o_digital_out[4] | output o_digital_out[3] | output ------------------------------------------------------------------- | Number of I/O ports without constraint | 13 | ------------------------------------------------------------------- Registers without clock definition Define the clock for these registers. -------------------------------------------------- There is no instance satisfying reporting criteria 4 DETAILED REPORT 4.1 Setup Detailed Report 4.2 Hold Detailed Report

















































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