I/O Timing Report 28 potential circuit loops found in timing analysis. Loading design for application iotiming from file step_impl1.ncd. Design name: step NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-4000HC Package: CSBGA132 Performance: 5 Package Status: Final Version 1.44. Performance Hardware Data Status: Final Version 34.4. Loading design for application iotiming from file step_impl1.ncd. Design name: step NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-4000HC Package: CSBGA132 Performance: 6 Package Status: Final Version 1.44. Performance Hardware Data Status: Final Version 34.4. Loading design for application iotiming from file step_impl1.ncd. Design name: step NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-4000HC Package: CSBGA132 Performance: M Package Status: Final Version 1.44. Performance Hardware Data Status: Final Version 34.4. // Design: step // Package: CSBGA132 // ncd File: step_impl1.ncd // Version: Diamond (64-bit) 3.12.0.240.2 // Written on Sun Feb 28 14:14:49 2021 // M: Minimum Performance Grade // iotiming step_impl1.ncd step_impl1.prf -gui -msgset C:/Users/lzsh/Desktop/step/promote.xml I/O Timing Report (All units are in ns) Worst Case Results across Performance Grades (M, 6, 5, 4): // Input Setup and Hold Times Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- fpga_rx clk R 1.195 4 0.115 M key[0] clk R 1.183 4 0.951 4 key[1] clk R 1.635 4 0.430 6 key[2] clk R 2.601 4 0.157 6 one_wire clk R 4.905 4 0.410 6 rst_n clk R 9.484 4 1.275 4 // Clock to Output Delay Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ beeper clk R 9.263 4 2.990 M fpga_tx clk R 10.356 4 3.293 M oled_clk clk R 9.776 4 3.093 M oled_csn clk R 10.275 4 3.233 M oled_dat clk R 9.776 4 3.093 M oled_dcn clk R 9.776 4 3.093 M oled_rst clk R 10.093 4 3.220 M // Internal_Clock to Input Port Internal_Clock -------------------------------------------------------- one_wire DS18B20Z_uut/clk_1mhz rst_n clk_c_generated_28 rst_n clk_c_generated_7 rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener rst_n control_s/clk_c_gener // Internal_Clock to Output Port Internal_Clock -------------------------------------------------------- one_wire DS18B20Z_uut/clk_1mhz WARNING: you must also run trce with hold speed: 4 WARNING: you must also run trce with hold speed: 6