Lattice Synthesis Timing Report -------------------------------------------------------------------------------- Lattice Synthesis Timing Report, Version Sun Feb 28 14:10:33 2021 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design: step Constraint file: Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 5.000000 -name clk1 [get_nets \DS18B20Z_uut/clk_1mhz] 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 5.000000 -name clk0 [get_nets clk_c] 4096 items scored, 4096 timing errors detected. -------------------------------------------------------------------------------- Error: The following path violates requirements by 78.179ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3AX CK \DS18B20Z_uut/data_out_i0_i15 (from clk_c +) Destination: FD1P3AX D \control_s/tx_data_out__i2 (to clk_c +) Delay: 83.019ns (30.2% logic, 69.8% route), 54 logic levels. Constraint Details: 83.019ns data_path \DS18B20Z_uut/data_out_i0_i15 to \control_s/tx_data_out__i2 violates 5.000ns delay constraint less 0.160ns L_S requirement (totaling 4.840ns) by 78.179ns Path Details: \DS18B20Z_uut/data_out_i0_i15 to \control_s/tx_data_out__i2 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \DS18B20Z_uut/data_out_i0_i15 (from clk_c) Route 1 e 0.941 data_out[15] LUT4 --- 0.493 B to Z i2_3_lut Route 7 e 1.502 n8_adj_3274 LUT4 --- 0.493 C to Z i2_3_lut_adj_909 Route 38 e 2.049 temperature_flag_N_23 LUT4 --- 0.493 C to Z temperature_code_10__I_0_10_i5_3_lut Route 2 e 1.141 temperature_code[4] A1_TO_FCO --- 0.827 A[2] to COUT add_6828_1 Route 1 e 0.020 n67492 FCI_TO_F --- 0.598 CIN to S[2] add_6828_3 Route 1 e 0.020 n12275 A1_TO_FCO --- 0.827 A[2] to COUT add_6852_1 Route 1 e 0.020 n67510 FCI_TO_FCO --- 0.157 CIN to COUT add_6852_3 Route 1 e 0.020 n67511 FCI_TO_FCO --- 0.157 CIN to COUT add_6852_5 Route 1 e 0.020 n67512 FCI_TO_FCO --- 0.157 CIN to COUT add_6852_7 Route 1 e 0.020 n67513 FCI_TO_F --- 0.598 CIN to S[2] add_6852_9 Route 1 e 0.020 n12327 A1_TO_FCO --- 0.827 A[2] to COUT add_6848_5 Route 1 e 0.020 n67500 FCI_TO_FCO --- 0.157 CIN to COUT add_6848_7 Route 1 e 0.020 n67501 FCI_TO_FCO --- 0.157 CIN to COUT add_6848_9 Route 1 e 0.020 n67502 FCI_TO_FCO --- 0.157 CIN to COUT add_6848_11 Route 1 e 0.020 n67503 FCI_TO_F --- 0.598 CIN to S[2] add_6848_cout Route 11 e 1.977 bin_code[20] LUT4 --- 0.493 B to Z \bin_to_bcd_uut/bin_code[17]_bdd_3_lut_2_lut_2_lut Route 1 e 0.020 \bin_to_bcd_uut/n72939 MUXL5 --- 0.233 BLUT to Z \bin_to_bcd_uut/i60310 Route 9 e 1.574 n8366 LUT4 --- 0.493 C to Z i2_4_lut Route 8 e 1.540 bcd_code_24__N_344 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4173_3_lut_4_lut Route 6 e 1.457 \bin_to_bcd_uut/n8370 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4803_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_362 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4845_3_lut_rep_657_4_lut_3_lut_4_lut Route 9 e 1.574 n74081 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i1_4_lut_4_lut_adj_178 Route 1 e 0.941 \bin_to_bcd_uut/n35_adj_2946 LUT4 --- 0.493 B to Z \bin_to_bcd_uut/i1_4_lut_adj_177 Route 8 e 1.540 n23 LUT4 --- 0.493 A to Z i2_4_lut_adj_910 Route 7 e 1.502 bcd_code_24__N_371 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4162_3_lut_4_lut Route 7 e 1.502 \bin_to_bcd_uut/n8378 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i4915_3_lut_4_lut Route 11 e 1.632 \bin_to_bcd_uut/bcd_code_24__N_398 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4083_3_lut_rep_631_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n74055 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i4971_3_lut_4_lut Route 11 e 1.632 \bin_to_bcd_uut/bcd_code_24__N_425 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4115_3_lut_rep_615_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n74039 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5027_3_lut_4_lut Route 9 e 1.574 \bin_to_bcd_uut/bcd_code_24__N_463 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i5141_3_lut_4_lut_3_lut_4_lut Route 5 e 1.405 \bin_to_bcd_uut/bcd_code_24__N_458 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4286_2_lut_rep_589_3_lut Route 5 e 1.405 \bin_to_bcd_uut/n74013 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5253_3_lut_rep_569_4_lut_3_lut_4_lut Route 9 e 1.574 n73993 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i1_4_lut_4_lut Route 1 e 0.941 \bin_to_bcd_uut/n35 LUT4 --- 0.493 B to Z \bin_to_bcd_uut/i1_4_lut_adj_179 Route 8 e 1.540 n23_adj_3273 LUT4 --- 0.493 A to Z i2_4_lut_adj_911 Route 7 e 1.502 bcd_code_24__N_481 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4130_3_lut_4_lut Route 7 e 1.502 \bin_to_bcd_uut/n8405 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5435_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_523 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4134_3_lut_rep_515_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n73939 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5547_3_lut_4_lut Route 11 e 1.632 \bin_to_bcd_uut/bcd_code_24__N_572 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4138_3_lut_rep_500_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n73924 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5659_3_lut_4_lut Route 9 e 1.574 \bin_to_bcd_uut/bcd_code_24__N_623 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4143_3_lut_rep_487_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n73911 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5771_3_lut_4_lut Route 9 e 1.574 \bin_to_bcd_uut/bcd_code_24__N_674 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4147_3_lut_rep_474_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n73898 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5883_3_lut_4_lut Route 7 e 1.502 \bin_to_bcd_uut/bcd_code_24__N_725 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4151_3_lut_rep_460_4_lut Route 2 e 1.141 \bin_to_bcd_uut/n73884 LUT4 --- 0.493 B to Z \bin_to_bcd_uut/i4207_2_lut_3_lut Route 3 e 1.258 \bin_to_bcd_uut/n4 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i4153_3_lut_rep_448_4_lut Route 2 e 1.141 \bin_to_bcd_uut/n73872 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i33024_3_lut Route 3 e 1.258 bcd_code[13] MUXL5 --- 0.233 BLUT to Z \control_s/i60364 Route 1 e 0.941 \control_s/n73056 LUT4 --- 0.493 B to Z \control_s/n6783_bdd_3_lut_60794 Route 1 e 0.020 \control_s/n73057 MUXL5 --- 0.233 BLUT to Z \control_s/i60366 Route 1 e 0.941 \control_s/tx_data_out_7__N_2736[1] -------- 83.019 (30.2% logic, 69.8% route), 54 logic levels. Error: The following path violates requirements by 78.179ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3AX CK \DS18B20Z_uut/data_out_i0_i15 (from clk_c +) Destination: FD1P3AX D \control_s/tx_data_out__i2 (to clk_c +) Delay: 83.019ns (30.2% logic, 69.8% route), 54 logic levels. Constraint Details: 83.019ns data_path \DS18B20Z_uut/data_out_i0_i15 to \control_s/tx_data_out__i2 violates 5.000ns delay constraint less 0.160ns L_S requirement (totaling 4.840ns) by 78.179ns Path Details: \DS18B20Z_uut/data_out_i0_i15 to \control_s/tx_data_out__i2 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \DS18B20Z_uut/data_out_i0_i15 (from clk_c) Route 1 e 0.941 data_out[15] LUT4 --- 0.493 B to Z i2_3_lut Route 7 e 1.502 n8_adj_3274 LUT4 --- 0.493 C to Z i2_3_lut_adj_909 Route 38 e 2.049 temperature_flag_N_23 LUT4 --- 0.493 C to Z temperature_code_10__I_0_10_i5_3_lut Route 2 e 1.141 temperature_code[4] A1_TO_FCO --- 0.827 A[2] to COUT add_6828_1 Route 1 e 0.020 n67492 FCI_TO_FCO --- 0.157 CIN to COUT add_6828_3 Route 1 e 0.020 n67493 FCI_TO_FCO --- 0.157 CIN to COUT add_6828_5 Route 1 e 0.020 n67494 FCI_TO_FCO --- 0.157 CIN to COUT add_6828_7 Route 1 e 0.020 n67495 FCI_TO_FCO --- 0.157 CIN to COUT add_6828_9 Route 1 e 0.020 n67496 FCI_TO_F --- 0.598 CIN to S[2] add_6828_11 Route 1 e 0.020 n12267 A1_TO_FCO --- 0.827 A[2] to COUT add_6852_9 Route 1 e 0.020 n67514 FCI_TO_FCO --- 0.157 CIN to COUT add_6852_11 Route 1 e 0.020 n67515 FCI_TO_F --- 0.598 CIN to S[2] add_6852_13 Route 1 e 0.020 n12323 A1_TO_FCO --- 0.827 A[2] to COUT add_6848_9 Route 1 e 0.020 n67502 FCI_TO_FCO --- 0.157 CIN to COUT add_6848_11 Route 1 e 0.020 n67503 FCI_TO_F --- 0.598 CIN to S[2] add_6848_cout Route 11 e 1.977 bin_code[20] LUT4 --- 0.493 B to Z \bin_to_bcd_uut/bin_code[17]_bdd_3_lut_2_lut_2_lut Route 1 e 0.020 \bin_to_bcd_uut/n72939 MUXL5 --- 0.233 BLUT to Z \bin_to_bcd_uut/i60310 Route 9 e 1.574 n8366 LUT4 --- 0.493 C to Z i2_4_lut Route 8 e 1.540 bcd_code_24__N_344 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4173_3_lut_4_lut Route 6 e 1.457 \bin_to_bcd_uut/n8370 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4803_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_362 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4845_3_lut_rep_657_4_lut_3_lut_4_lut Route 9 e 1.574 n74081 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i1_2_lut_3_lut_4_lut_4_lut_adj_175 Route 1 e 0.941 \bin_to_bcd_uut/n29_adj_2943 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i1_4_lut_adj_177 Route 8 e 1.540 n23 LUT4 --- 0.493 A to Z i2_4_lut_adj_910 Route 7 e 1.502 bcd_code_24__N_371 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4162_3_lut_4_lut Route 7 e 1.502 \bin_to_bcd_uut/n8378 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i4915_3_lut_4_lut Route 11 e 1.632 \bin_to_bcd_uut/bcd_code_24__N_398 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4083_3_lut_rep_631_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n74055 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i4971_3_lut_4_lut Route 11 e 1.632 \bin_to_bcd_uut/bcd_code_24__N_425 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4115_3_lut_rep_615_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n74039 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5027_3_lut_4_lut Route 9 e 1.574 \bin_to_bcd_uut/bcd_code_24__N_463 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i5141_3_lut_4_lut_3_lut_4_lut Route 5 e 1.405 \bin_to_bcd_uut/bcd_code_24__N_458 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4286_2_lut_rep_589_3_lut Route 5 e 1.405 \bin_to_bcd_uut/n74013 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5253_3_lut_rep_569_4_lut_3_lut_4_lut Route 9 e 1.574 n73993 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i1_2_lut_3_lut_4_lut_4_lut Route 1 e 0.941 \bin_to_bcd_uut/n29 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i1_4_lut_adj_179 Route 8 e 1.540 n23_adj_3273 LUT4 --- 0.493 A to Z i2_4_lut_adj_911 Route 7 e 1.502 bcd_code_24__N_481 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4130_3_lut_4_lut Route 7 e 1.502 \bin_to_bcd_uut/n8405 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5435_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_523 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4134_3_lut_rep_515_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n73939 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5547_3_lut_4_lut Route 11 e 1.632 \bin_to_bcd_uut/bcd_code_24__N_572 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4138_3_lut_rep_500_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n73924 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5659_3_lut_4_lut Route 9 e 1.574 \bin_to_bcd_uut/bcd_code_24__N_623 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4143_3_lut_rep_487_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n73911 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5771_3_lut_4_lut Route 9 e 1.574 \bin_to_bcd_uut/bcd_code_24__N_674 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4147_3_lut_rep_474_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n73898 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5883_3_lut_4_lut Route 7 e 1.502 \bin_to_bcd_uut/bcd_code_24__N_725 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4151_3_lut_rep_460_4_lut Route 2 e 1.141 \bin_to_bcd_uut/n73884 LUT4 --- 0.493 B to Z \bin_to_bcd_uut/i4207_2_lut_3_lut Route 3 e 1.258 \bin_to_bcd_uut/n4 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i4153_3_lut_rep_448_4_lut Route 2 e 1.141 \bin_to_bcd_uut/n73872 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i33024_3_lut Route 3 e 1.258 bcd_code[13] MUXL5 --- 0.233 BLUT to Z \control_s/i60364 Route 1 e 0.941 \control_s/n73056 LUT4 --- 0.493 B to Z \control_s/n6783_bdd_3_lut_60794 Route 1 e 0.020 \control_s/n73057 MUXL5 --- 0.233 BLUT to Z \control_s/i60366 Route 1 e 0.941 \control_s/tx_data_out_7__N_2736[1] -------- 83.019 (30.2% logic, 69.8% route), 54 logic levels. Error: The following path violates requirements by 78.179ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3AX CK \DS18B20Z_uut/data_out_i0_i15 (from clk_c +) Destination: FD1P3AX D \control_s/tx_data_out__i2 (to clk_c +) Delay: 83.019ns (30.2% logic, 69.8% route), 54 logic levels. Constraint Details: 83.019ns data_path \DS18B20Z_uut/data_out_i0_i15 to \control_s/tx_data_out__i2 violates 5.000ns delay constraint less 0.160ns L_S requirement (totaling 4.840ns) by 78.179ns Path Details: \DS18B20Z_uut/data_out_i0_i15 to \control_s/tx_data_out__i2 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \DS18B20Z_uut/data_out_i0_i15 (from clk_c) Route 1 e 0.941 data_out[15] LUT4 --- 0.493 B to Z i2_3_lut Route 7 e 1.502 n8_adj_3274 LUT4 --- 0.493 C to Z i2_3_lut_adj_909 Route 38 e 2.049 temperature_flag_N_23 LUT4 --- 0.493 C to Z temperature_code_10__I_0_10_i5_3_lut Route 2 e 1.141 temperature_code[4] A1_TO_FCO --- 0.827 A[2] to COUT add_6828_1 Route 1 e 0.020 n67492 FCI_TO_FCO --- 0.157 CIN to COUT add_6828_3 Route 1 e 0.020 n67493 FCI_TO_FCO --- 0.157 CIN to COUT add_6828_5 Route 1 e 0.020 n67494 FCI_TO_F --- 0.598 CIN to S[2] add_6828_7 Route 1 e 0.020 n12271 A1_TO_FCO --- 0.827 A[2] to COUT add_6852_5 Route 1 e 0.020 n67512 FCI_TO_FCO --- 0.157 CIN to COUT add_6852_7 Route 1 e 0.020 n67513 FCI_TO_FCO --- 0.157 CIN to COUT add_6852_9 Route 1 e 0.020 n67514 FCI_TO_FCO --- 0.157 CIN to COUT add_6852_11 Route 1 e 0.020 n67515 FCI_TO_F --- 0.598 CIN to S[2] add_6852_13 Route 1 e 0.020 n12322 A1_TO_FCO --- 0.827 A[2] to COUT add_6848_9 Route 1 e 0.020 n67502 FCI_TO_FCO --- 0.157 CIN to COUT add_6848_11 Route 1 e 0.020 n67503 FCI_TO_F --- 0.598 CIN to S[2] add_6848_cout Route 11 e 1.977 bin_code[20] LUT4 --- 0.493 B to Z \bin_to_bcd_uut/bin_code[17]_bdd_3_lut_2_lut_2_lut Route 1 e 0.020 \bin_to_bcd_uut/n72939 MUXL5 --- 0.233 BLUT to Z \bin_to_bcd_uut/i60310 Route 9 e 1.574 n8366 LUT4 --- 0.493 C to Z i2_4_lut Route 8 e 1.540 bcd_code_24__N_344 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4173_3_lut_4_lut Route 6 e 1.457 \bin_to_bcd_uut/n8370 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4803_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_362 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4845_3_lut_rep_657_4_lut_3_lut_4_lut Route 9 e 1.574 n74081 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i1_4_lut_4_lut_adj_178 Route 1 e 0.941 \bin_to_bcd_uut/n35_adj_2946 LUT4 --- 0.493 B to Z \bin_to_bcd_uut/i1_4_lut_adj_177 Route 8 e 1.540 n23 LUT4 --- 0.493 A to Z i2_4_lut_adj_910 Route 7 e 1.502 bcd_code_24__N_371 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4162_3_lut_4_lut Route 7 e 1.502 \bin_to_bcd_uut/n8378 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i4915_3_lut_4_lut Route 11 e 1.632 \bin_to_bcd_uut/bcd_code_24__N_398 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4083_3_lut_rep_631_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n74055 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i4971_3_lut_4_lut Route 11 e 1.632 \bin_to_bcd_uut/bcd_code_24__N_425 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4115_3_lut_rep_615_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n74039 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5027_3_lut_4_lut Route 9 e 1.574 \bin_to_bcd_uut/bcd_code_24__N_463 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i5141_3_lut_4_lut_3_lut_4_lut Route 5 e 1.405 \bin_to_bcd_uut/bcd_code_24__N_458 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4286_2_lut_rep_589_3_lut Route 5 e 1.405 \bin_to_bcd_uut/n74013 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5253_3_lut_rep_569_4_lut_3_lut_4_lut Route 9 e 1.574 n73993 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i1_4_lut_4_lut Route 1 e 0.941 \bin_to_bcd_uut/n35 LUT4 --- 0.493 B to Z \bin_to_bcd_uut/i1_4_lut_adj_179 Route 8 e 1.540 n23_adj_3273 LUT4 --- 0.493 A to Z i2_4_lut_adj_911 Route 7 e 1.502 bcd_code_24__N_481 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4130_3_lut_4_lut Route 7 e 1.502 \bin_to_bcd_uut/n8405 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5435_3_lut_4_lut Route 10 e 1.604 \bin_to_bcd_uut/bcd_code_24__N_523 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4134_3_lut_rep_515_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n73939 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5547_3_lut_4_lut Route 11 e 1.632 \bin_to_bcd_uut/bcd_code_24__N_572 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4138_3_lut_rep_500_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n73924 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5659_3_lut_4_lut Route 9 e 1.574 \bin_to_bcd_uut/bcd_code_24__N_623 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4143_3_lut_rep_487_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n73911 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5771_3_lut_4_lut Route 9 e 1.574 \bin_to_bcd_uut/bcd_code_24__N_674 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4147_3_lut_rep_474_4_lut Route 3 e 1.258 \bin_to_bcd_uut/n73898 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i5883_3_lut_4_lut Route 7 e 1.502 \bin_to_bcd_uut/bcd_code_24__N_725 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i4151_3_lut_rep_460_4_lut Route 2 e 1.141 \bin_to_bcd_uut/n73884 LUT4 --- 0.493 B to Z \bin_to_bcd_uut/i4207_2_lut_3_lut Route 3 e 1.258 \bin_to_bcd_uut/n4 LUT4 --- 0.493 D to Z \bin_to_bcd_uut/i4153_3_lut_rep_448_4_lut Route 2 e 1.141 \bin_to_bcd_uut/n73872 LUT4 --- 0.493 C to Z \bin_to_bcd_uut/i33024_3_lut Route 3 e 1.258 bcd_code[13] MUXL5 --- 0.233 BLUT to Z \control_s/i60364 Route 1 e 0.941 \control_s/n73056 LUT4 --- 0.493 B to Z \control_s/n6783_bdd_3_lut_60794 Route 1 e 0.020 \control_s/n73057 MUXL5 --- 0.233 BLUT to Z \control_s/i60366 Route 1 e 0.941 \control_s/tx_data_out_7__N_2736[1] -------- 83.019 (30.2% logic, 69.8% route), 54 logic levels. Warning: 83.179 ns is the maximum delay for this constraint. Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk1 [get_nets \DS18B20Z_uut/clk_1mhz] | -| -| 0 | | | create_clock -period 5.000000 -name | | | clk0 [get_nets clk_c] | 5.000 ns| 83.179 ns| 54 * | | | -------------------------------------------------------------------------------- 1 constraints not met. -------------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total -------------------------------------------------------------------------------- \bin_to_bcd_uut/bcd_code_24__N_362 | 10| 4096| 99.00% | | | \bin_to_bcd_uut/bcd_code_24__N_398 | 11| 4096| 99.00% | | | \bin_to_bcd_uut/bcd_code_24__N_425 | 11| 4096| 99.00% | | | \bin_to_bcd_uut/bcd_code_24__N_458 | 5| 4096| 99.00% | | | \bin_to_bcd_uut/bcd_code_24__N_463 | 9| 4096| 99.00% | | | \bin_to_bcd_uut/bcd_code_24__N_523 | 10| 4096| 99.00% | | | \bin_to_bcd_uut/bcd_code_24__N_572 | 11| 4096| 99.00% | | | \bin_to_bcd_uut/bcd_code_24__N_623 | 9| 4096| 99.00% | | | \bin_to_bcd_uut/bcd_code_24__N_674 | 9| 4096| 99.00% | | | \bin_to_bcd_uut/bcd_code_24__N_725 | 7| 4096| 99.00% | | | \bin_to_bcd_uut/n8370 | 6| 4096| 99.00% | | | \bin_to_bcd_uut/n8378 | 7| 4096| 99.00% | | | \bin_to_bcd_uut/n8405 | 7| 4096| 99.00% | | | \bin_to_bcd_uut/n73872 | 2| 4096| 99.00% | | | \bin_to_bcd_uut/n73884 | 2| 4096| 99.00% | | | \bin_to_bcd_uut/n73898 | 3| 4096| 99.00% | | | \bin_to_bcd_uut/n73911 | 3| 4096| 99.00% | | | \bin_to_bcd_uut/n73924 | 3| 4096| 99.00% | | | \bin_to_bcd_uut/n73939 | 3| 4096| 99.00% | | | \bin_to_bcd_uut/n74013 | 5| 4096| 99.00% | | | \bin_to_bcd_uut/n74039 | 3| 4096| 99.00% | | | \bin_to_bcd_uut/n74055 | 3| 4096| 99.00% | | | bcd_code_24__N_344 | 8| 4096| 99.00% | | | bcd_code_24__N_371 | 7| 4096| 99.00% | | | bcd_code_24__N_481 | 7| 4096| 99.00% | | | bin_code[20] | 11| 4096| 99.00% | | | n8_adj_3274 | 7| 4096| 99.00% | | | n23 | 8| 4096| 99.00% | | | n23_adj_3273 | 8| 4096| 99.00% | | | n8366 | 9| 4096| 99.00% | | | n67492 | 1| 4096| 99.00% | | | n67503 | 1| 4096| 99.00% | | | n73993 | 9| 4096| 99.00% | | | n74081 | 9| 4096| 99.00% | | | temperature_code[4] | 2| 4096| 99.00% | | | temperature_flag_N_23 | 38| 4096| 99.00% | | | n67502 | 1| 3520| 85.94% | | | n67493 | 1| 3148| 76.86% | | | n67513 | 1| 2598| 63.43% | | | n67512 | 1| 2510| 61.28% | | | n67501 | 1| 2408| 58.79% | | | n67514 | 1| 2322| 56.69% | | | n67494 | 1| 2222| 54.25% | | | \bin_to_bcd_uut/n4 | 3| 2100| 51.27% | | | \control_s/n73056 | 1| 2100| 51.27% | | | \control_s/n73057 | 1| 2100| 51.27% | | | \control_s/tx_data_out_7__N_2736[1] | 1| 2100| 51.27% | | | bcd_code[13] | 3| 2100| 51.27% | | | \bin_to_bcd_uut/n29_adj_2943 | 1| 2099| 51.25% | | | \bin_to_bcd_uut/n35 | 1| 2099| 51.25% | | | \bin_to_bcd_uut/n72938 | 1| 2099| 51.25% | | | \bin_to_bcd_uut/n29 | 1| 1997| 48.75% | | | \bin_to_bcd_uut/n35_adj_2946 | 1| 1997| 48.75% | | | \bin_to_bcd_uut/n72939 | 1| 1997| 48.75% | | | \bin_to_bcd_uut/bcd_code_24__N_767 | 3| 1996| 48.73% | | | \control_s/n73061 | 1| 1996| 48.73% | | | \control_s/n73062 | 1| 1996| 48.73% | | | \control_s/tx_data_out_7__N_2736[2] | 1| 1996| 48.73% | | | bcd_code[14] | 3| 1996| 48.73% | | | n67511 | 1| 1874| 45.75% | | | n67515 | 1| 1688| 41.21% | | | n67500 | 1| 1487| 36.30% | | | n67495 | 1| 1394| 34.03% | | | data_out[11] | 1| 1391| 33.96% | | | data_out[13] | 1| 1391| 33.96% | | | data_out[15] | 1| 1314| 32.08% | | | n12275 | 1| 948| 23.14% | | | n67510 | 1| 948| 23.14% | | | n12273 | 1| 926| 22.61% | | | n12271 | 1| 828| 20.21% | | | n67496 | 1| 749| 18.29% | | | n67499 | 1| 749| 18.29% | | | n12269 | 1| 645| 15.75% | | | n12340 | 1| 576| 14.06% | | | n67516 | 1| 576| 14.06% | | | n12323 | 1| 572| 13.96% | | | n12322 | 1| 540| 13.18% | | | n12325 | 1| 476| 11.62% | | | n12267 | 1| 462| 11.28% | | | n12324 | 1| 445| 10.86% | | | -------------------------------------------------------------------------------- Timing summary: --------------- Timing errors: 4096 Score: 320221184 Constraints cover >4294967295 paths, 3909 nets, and 12276 connections (98.2% coverage) Peak memory: 185716736 bytes, TRCE: 0 bytes, DLYMAN: 0 bytes CPU_TIME_REPORT: 0 secs