Setting log file to 'C:/Users/lzsh/Desktop/step/impl1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file 'D:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
(VERI-1482) Analyzing Verilog file 'C:/Users/lzsh/Desktop/step/OLED.v'
(VERI-1482) Analyzing Verilog file 'C:/Users/lzsh/Desktop/step/tempreture.v'
(VERI-1482) Analyzing Verilog file 'C:/Users/lzsh/Desktop/step/buzzer.v'
(VERI-1482) Analyzing Verilog file 'C:/Users/lzsh/Desktop/step/uart_r.v'
(VERI-1482) Analyzing Verilog file 'C:/Users/lzsh/Desktop/step/uart_s.v'
(VERI-1482) Analyzing Verilog file 'C:/Users/lzsh/Desktop/step/Baud.v'
(VERI-1482) Analyzing Verilog file 'C:/Users/lzsh/Desktop/step/uart_bus.v'
(VERI-1482) Analyzing Verilog file 'C:/Users/lzsh/Desktop/step/key.v'
(VERI-1482) Analyzing Verilog file 'C:/Users/lzsh/Desktop/step/step.v'
(VERI-1482) Analyzing Verilog file 'C:/Users/lzsh/Desktop/step/center_control.v'
(VERI-1482) Analyzing Verilog file 'C:/Users/lzsh/Desktop/step/bin_to_bcd.v'
INFO - C:/Users/lzsh/Desktop/step/step.v(1,8-1,12) (VERI-1018) compiling module 'step'
INFO - C:/Users/lzsh/Desktop/step/step.v(1,1-143,10) (VERI-9000) elaborating module 'step'
INFO - C:/Users/lzsh/Desktop/step/tempreture.v(1,1-249,10) (VERI-9000) elaborating module 'DS18B20Z_uniq_1'
INFO - C:/Users/lzsh/Desktop/step/bin_to_bcd.v(1,1-30,10) (VERI-9000) elaborating module 'bin_to_bcd_uniq_1'
INFO - C:/Users/lzsh/Desktop/step/OLED.v(1,1-287,10) (VERI-9000) elaborating module 'OLED12832_uniq_1'
INFO - C:/Users/lzsh/Desktop/step/uart_bus.v(1,1-79,10) (VERI-9000) elaborating module 'Uart_Bus_uniq_1'
INFO - C:/Users/lzsh/Desktop/step/buzzer.v(1,1-26,10) (VERI-9000) elaborating module 'PWM_uniq_1'
INFO - C:/Users/lzsh/Desktop/step/key.v(1,1-60,10) (VERI-9000) elaborating module 'key_uniq_1'
INFO - C:/Users/lzsh/Desktop/step/center_control.v(1,1-470,10) (VERI-9000) elaborating module 'control_uniq_1'
INFO - C:/Users/lzsh/Desktop/step/Baud.v(1,1-33,10) (VERI-9000) elaborating module 'Baud_uniq_1'
INFO - C:/Users/lzsh/Desktop/step/Baud.v(1,1-33,10) (VERI-9000) elaborating module 'Baud_uniq_2'
INFO - C:/Users/lzsh/Desktop/step/uart_r.v(1,1-68,10) (VERI-9000) elaborating module 'Uart_Rx_uniq_1'
INFO - C:/Users/lzsh/Desktop/step/uart_s.v(1,1-44,10) (VERI-9000) elaborating module 'Uart_Tx_uniq_1'
Done: design load finished with (0) errors, and (0) warnings