Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version  
Sun Feb 28 13:48:49 2021

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design:     control
Constraint file:  
Report level:    verbose report, limited to 3 items per constraint
--------------------------------------------------------------------------------



================================================================================
Constraint: create_clock -period 5.000000 -name clk0 [get_nets clk_c]
            2858 items scored, 2858 timing errors detected.
--------------------------------------------------------------------------------


Error:  The following path violates requirements by 10.712ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3IX    CK             cnt_uart__i3  (from clk_c +)
   Destination:    FD1P3IX    SP             cnt_uart__i3  (to clk_c +)

   Delay:                  15.427ns  (28.4% logic, 71.6% route), 9 logic levels.

 Constraint Details:

     15.427ns data_path cnt_uart__i3 to cnt_uart__i3 violates
      5.000ns delay constraint less
      0.285ns LCE_S requirement (totaling 4.715ns) by 10.712ns

 Path Details: cnt_uart__i3 to cnt_uart__i3

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.444             CK to Q              cnt_uart__i3 (from clk_c)
Route         2   e 1.198                                  cnt_uart[3]
LUT4        ---     0.493              A to Z              i1_2_lut_adj_98
Route         1   e 0.941                                  n6_adj_99
LUT4        ---     0.493              D to Z              i4_4_lut_adj_90
Route         6   e 1.457                                  n18049
LUT4        ---     0.493              D to Z              i2_3_lut_4_lut_adj_306
Route         1   e 0.941                                  n22131
LUT4        ---     0.493              A to Z              i1084_4_lut
Route         1   e 0.941                                  n22
LUT4        ---     0.493              A to Z              i3_4_lut_adj_19
Route         1   e 0.941                                  n22219
LUT4        ---     0.493              C to Z              i1093_4_lut
Route         1   e 0.941                                  n40
LUT4        ---     0.493              A to Z              i1240_4_lut
Route        25   e 1.841                                  cnt_uart_23__N_997
LUT4        ---     0.493              B to Z              i1027_2_lut
Route        24   e 1.838                                  clk_c_enable_89
                  --------
                   15.427  (28.4% logic, 71.6% route), 9 logic levels.


Error:  The following path violates requirements by 10.712ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3IX    CK             cnt_uart__i3  (from clk_c +)
   Destination:    FD1P3IX    SP             cnt_uart__i4  (to clk_c +)

   Delay:                  15.427ns  (28.4% logic, 71.6% route), 9 logic levels.

 Constraint Details:

     15.427ns data_path cnt_uart__i3 to cnt_uart__i4 violates
      5.000ns delay constraint less
      0.285ns LCE_S requirement (totaling 4.715ns) by 10.712ns

 Path Details: cnt_uart__i3 to cnt_uart__i4

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.444             CK to Q              cnt_uart__i3 (from clk_c)
Route         2   e 1.198                                  cnt_uart[3]
LUT4        ---     0.493              A to Z              i1_2_lut_adj_98
Route         1   e 0.941                                  n6_adj_99
LUT4        ---     0.493              D to Z              i4_4_lut_adj_90
Route         6   e 1.457                                  n18049
LUT4        ---     0.493              D to Z              i2_3_lut_4_lut_adj_306
Route         1   e 0.941                                  n22131
LUT4        ---     0.493              A to Z              i1084_4_lut
Route         1   e 0.941                                  n22
LUT4        ---     0.493              A to Z              i3_4_lut_adj_19
Route         1   e 0.941                                  n22219
LUT4        ---     0.493              C to Z              i1093_4_lut
Route         1   e 0.941                                  n40
LUT4        ---     0.493              A to Z              i1240_4_lut
Route        25   e 1.841                                  cnt_uart_23__N_997
LUT4        ---     0.493              B to Z              i1027_2_lut
Route        24   e 1.838                                  clk_c_enable_89
                  --------
                   15.427  (28.4% logic, 71.6% route), 9 logic levels.


Error:  The following path violates requirements by 10.712ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3IX    CK             cnt_uart__i3  (from clk_c +)
   Destination:    FD1P3IX    SP             cnt_uart__i5  (to clk_c +)

   Delay:                  15.427ns  (28.4% logic, 71.6% route), 9 logic levels.

 Constraint Details:

     15.427ns data_path cnt_uart__i3 to cnt_uart__i5 violates
      5.000ns delay constraint less
      0.285ns LCE_S requirement (totaling 4.715ns) by 10.712ns

 Path Details: cnt_uart__i3 to cnt_uart__i5

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.444             CK to Q              cnt_uart__i3 (from clk_c)
Route         2   e 1.198                                  cnt_uart[3]
LUT4        ---     0.493              A to Z              i1_2_lut_adj_98
Route         1   e 0.941                                  n6_adj_99
LUT4        ---     0.493              D to Z              i4_4_lut_adj_90
Route         6   e 1.457                                  n18049
LUT4        ---     0.493              D to Z              i2_3_lut_4_lut_adj_306
Route         1   e 0.941                                  n22131
LUT4        ---     0.493              A to Z              i1084_4_lut
Route         1   e 0.941                                  n22
LUT4        ---     0.493              A to Z              i3_4_lut_adj_19
Route         1   e 0.941                                  n22219
LUT4        ---     0.493              C to Z              i1093_4_lut
Route         1   e 0.941                                  n40
LUT4        ---     0.493              A to Z              i1240_4_lut
Route        25   e 1.841                                  cnt_uart_23__N_997
LUT4        ---     0.493              B to Z              i1027_2_lut
Route        24   e 1.838                                  clk_c_enable_89
                  --------
                   15.427  (28.4% logic, 71.6% route), 9 logic levels.

Warning: 15.712 ns is the maximum delay for this constraint.


Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 5.000000 -name     |             |             |
clk0 [get_nets clk_c]                   |     5.000 ns|    15.712 ns|     9 *
                                        |             |             |
--------------------------------------------------------------------------------


1 constraints not met.

--------------------------------------------------------------------------------
Critical Nets                           |   Loads|  Errors| % of total
--------------------------------------------------------------------------------
clk_c_enable_68                         |       7|     644|     22.53%
                                        |        |        |
n23645                                  |       8|     640|     22.39%
                                        |        |        |
n17392                                  |       4|     576|     20.15%
                                        |        |        |
n23670                                  |       6|     576|     20.15%
                                        |        |        |
n16825                                  |       9|     512|     17.91%
                                        |        |        |
n3212                                   |       8|     497|     17.39%
                                        |        |        |
n23505                                  |       1|     497|     17.39%
                                        |        |        |
cnt_uart_23__N_997                      |      25|     480|     16.79%
                                        |        |        |
n40                                     |       1|     480|     16.79%
                                        |        |        |
n22219                                  |       1|     480|     16.79%
                                        |        |        |
n23503                                  |       1|     441|     15.43%
                                        |        |        |
n23504                                  |       1|     441|     15.43%
                                        |        |        |
n22                                     |       1|     384|     13.44%
                                        |        |        |
n23648                                  |       4|     384|     13.44%
                                        |        |        |
n23680                                  |       6|     384|     13.44%
                                        |        |        |
clk_c_enable_89                         |      24|     360|     12.60%
                                        |        |        |
n22131                                  |       1|     312|     10.92%
                                        |        |        |
n18049                                  |       6|     310|     10.85%
                                        |        |        |
--------------------------------------------------------------------------------


Timing summary:
---------------

Timing errors: 2858  Score: 20255648

Constraints cover  17060 paths, 1679 nets, and 4845 connections (90.3% coverage)


Peak memory: 116277248 bytes, TRCE: 0 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs