Map TRACE Report

Loading design for application trce from file step_impl1_map.ncd.
Design name: step
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-4000HC
Package:     CSBGA132
Performance: 4
Loading device for application trce from file 'xo2c4000.nph' in environment: D:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Sun Feb 28 14:14:12 2021

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o step_impl1.tw1 -gui -msgset C:/Users/lzsh/Desktop/step/promote.xml step_impl1_map.ncd step_impl1.prf 
Design file:     step_impl1_map.ncd
Preference file: step_impl1.prf
Device,speed:    LCMXO2-4000HC,4
Report level:    verbose report, limited to 1 item per preference
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Preference Summary

  • FREQUENCY NET "clk_c" 22.277000 MHz (4096 errors)
  • 4096 items scored, 4096 timing errors detected. Warning: 4.826MHz is the maximum frequency for this preference.
  • FREQUENCY NET "clk_c_generated_28" 399.840000 MHz (3 errors)
  • 3 items scored, 3 timing errors detected. Warning: 241.080MHz is the maximum frequency for this preference. 28 potential circuit loops found in timing analysis. 28 potential circuit loops found in timing analysis. 28 potential circuit loops found in timing analysis. Report Type: based on TRACE automatically generated preferences BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "clk_c" 22.277000 MHz ; 4096 items scored, 4096 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 5.312ns (weighted slack = -162.322ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_s/i23400 (from clk_c_generated_28 +) Destination: FF Data in OLED12832_uut/char_i0 (to clk_c +) Delay: 6.615ns (36.8% logic, 63.2% route), 5 logic levels. Constraint Details: 6.615ns physical path delay control_s/SLICE_599 to OLED12832_uut/SLICE_267 exceeds 1.469ns delay constraint less 0.166ns DIN_SET requirement (totaling 1.303ns) by 5.312ns Physical Path Details: Data path control_s/SLICE_599 to OLED12832_uut/SLICE_267: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 *SLICE_599.CLK to */SLICE_599.Q0 control_s/SLICE_599 (from clk_c_generated_28) ROUTE 3 e 1.234 */SLICE_599.Q0 to SLICE_1576.B0 n35742 CTOF_DEL --- 0.495 SLICE_1576.B0 to SLICE_1576.F0 SLICE_1576 ROUTE 1 e 1.234 SLICE_1576.F0 to */SLICE_988.C1 OLED12832_uut/n1 CTOF_DEL --- 0.495 */SLICE_988.C1 to */SLICE_988.F1 OLED12832_uut/SLICE_988 ROUTE 1 e 0.480 */SLICE_988.F1 to */SLICE_988.B0 OLED12832_uut/char_167_N_1235_0 CTOF_DEL --- 0.495 */SLICE_988.B0 to */SLICE_988.F0 OLED12832_uut/SLICE_988 ROUTE 1 e 1.234 */SLICE_988.F0 to */SLICE_267.C0 OLED12832_uut/n16_adj_3072 CTOF_DEL --- 0.495 */SLICE_267.C0 to */SLICE_267.F0 OLED12832_uut/SLICE_267 ROUTE 1 e 0.001 */SLICE_267.F0 to *SLICE_267.DI0 OLED12832_uut/char_167_N_904_0 (to clk_c) -------- 6.615 (36.8% logic, 63.2% route), 5 logic levels. Warning: 4.826MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "clk_c_generated_28" 399.840000 MHz ; 3 items scored, 3 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 1.647ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_s/tone_flag_378_rep_1018 (from clk_c +) Destination: FF Data in control_s/i23400 (to clk_c_generated_28 +) Delay: 3.415ns (27.7% logic, 72.3% route), 2 logic levels. Constraint Details: 3.415ns physical path delay SLICE_1555 to control_s/SLICE_599 exceeds 2.501ns delay constraint less 0.733ns LSRREC_SET requirement (totaling 1.768ns) by 1.647ns Physical Path Details: Data path SLICE_1555 to control_s/SLICE_599: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_1555.CLK to SLICE_1555.Q0 SLICE_1555 (from clk_c) ROUTE 68 e 1.234 SLICE_1555.Q0 to SLICE_1460.B1 n75906 CTOF_DEL --- 0.495 SLICE_1460.B1 to SLICE_1460.F1 SLICE_1460 ROUTE 1 e 1.234 SLICE_1460.F1 to *SLICE_599.LSR control_s/temp_out_31__N_1907 (to clk_c_generated_28) -------- 3.415 (27.7% logic, 72.3% route), 2 logic levels. Warning: 241.080MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "clk_c" 22.277000 MHz ; | 22.277 MHz| 4.826 MHz| 5 * | | | FREQUENCY NET "clk_c_generated_28" | | | 399.840000 MHz ; | 399.840 MHz| 241.080 MHz| 2 * | | | ---------------------------------------------------------------------------- 2 preferences(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- bin_to_bcd_uut/n73884 | 2| 4094| 99.88% | | | bin_to_bcd_uut/n73872 | 2| 4094| 99.88% | | | bin_to_bcd_uut/n73898 | 3| 4094| 99.88% | | | bin_to_bcd_uut/n73911 | 3| 4094| 99.88% | | | bin_to_bcd_uut/bcd_code_24__N_674 | 9| 4094| 99.88% | | | bin_to_bcd_uut/n8370 | 4| 4094| 99.88% | | | bin_to_bcd_uut/n72938 | 2| 4094| 99.88% | | | bin_to_bcd_uut/bcd_code_24__N_767 | 3| 4094| 99.88% | | | control_s/tx_data_out_7_N_2736_1 | 1| 4094| 99.88% | | | bcd_code_13 | 3| 4094| 99.88% | | | control_s/n73056 | 1| 4094| 99.88% | | | bcd_code_24__N_344 | 9| 4094| 99.88% | | | n8366 | 8| 4094| 99.88% | | | bin_code_20 | 12| 4094| 99.88% | | | n67503 | 1| 4094| 99.88% | | | temperature_code_4 | 2| 4094| 99.88% | | | n67492 | 1| 4094| 99.88% | | | temperature_flag_N_23 | 38| 4094| 99.88% | | | n8_adj_3274 | 7| 4094| 99.88% | | | n67502 | 1| 4093| 99.85% | | | n67501 | 1| 4073| 99.37% | | | bin_to_bcd_uut/n74039 | 3| 4068| 99.24% | | | n67512 | 1| 3937| 96.05% | | | n67500 | 1| 3903| 95.22% | | | bin_to_bcd_uut/n74055 | 3| 3892| 94.95% | | | bin_to_bcd_uut/n73924 | 3| 3776| 92.12% | | | bin_to_bcd_uut/bcd_code_24__N_362 | 10| 3352| 81.78% | | | bin_to_bcd_uut/bcd_code_24__N_463 | 9| 3235| 78.92% | | | n67511 | 1| 3212| 78.36% | | | n12274 | 1| 3212| 78.36% | | | bin_to_bcd_uut/bcd_code_24__N_725 | 7| 3184| 77.68% | | | n67499 | 1| 3073| 74.97% | | | n12329 | 1| 3073| 74.97% | | | bin_to_bcd_uut/n35_adj_2946 | 1| 3049| 74.38% | | | bin_to_bcd_uut/n8378 | 6| 3049| 74.38% | | | n74081 | 9| 3049| 74.38% | | | n23 | 8| 3049| 74.38% | | | bin_to_bcd_uut/bcd_code_24__N_425 | 11| 3012| 73.48% | | | bin_to_bcd_uut/bcd_code_24__N_623 | 9| 2920| 71.24% | | | bin_to_bcd_uut/n74013 | 5| 2402| 58.60% | | | bin_to_bcd_uut/bcd_code_24__N_458 | 5| 2402| 58.60% | | | data_out_13 | 1| 2337| 57.01% | | | bin_to_bcd_uut/n74072 | 2| 2325| 56.72% | | | bin_to_bcd_uut/bcd_code_24__N_398 | 11| 2325| 56.72% | | | bin_to_bcd_uut/n73939 | 3| 2269| 55.35% | | | bin_to_bcd_uut/bcd_code_24__N_572 | 11| 2269| 55.35% | | | bin_to_bcd_uut/n73989 | 3| 2085| 50.87% | | | bin_to_bcd_uut/n8405 | 6| 1715| 41.84% | | | bin_to_bcd_uut/n29 | 1| 1715| 41.84% | | | n73993 | 9| 1715| 41.84% | | | n23_adj_3273 | 8| 1715| 41.84% | | | bin_to_bcd_uut/bcd_code_24__N_532 | 9| 1711| 41.74% | | | bin_to_bcd_uut/n74026 | 3| 1690| 41.23% | | | bin_to_bcd_uut/n74060 | 6| 1567| 38.23% | | | bin_to_bcd_uut/n73996 | 5| 1538| 37.52% | | | bin_to_bcd_uut/n73929 | 6| 1507| 36.77% | | | bin_to_bcd_uut/bcd_code_24__N_576 | 5| 1507| 36.77% | | | bin_to_bcd_uut/n73976 | 2| 1463| 35.69% | | | bin_to_bcd_uut/bcd_code_24__N_581 | 8| 1463| 35.69% | | | bin_to_bcd_uut/bcd_code_24__N_494 | 5| 1398| 34.11% | | | bin_to_bcd_uut/bcd_code_24__N_499 | 9| 1364| 33.28% | | | bin_to_bcd_uut/n73973 | 2| 1272| 31.03% | | | bin_to_bcd_uut/n73915 | 4| 1174| 28.64% | | | data_out_15 | 1| 1125| 27.45% | | | bin_to_bcd_uut/n74046 | 6| 1056| 25.76% | | | bin_to_bcd_uut/n74090 | 3| 1045| 25.49% | | | bin_to_bcd_uut/n74079 | 3| 1045| 25.49% | | | n67513 | 1| 1003| 24.47% | | | bin_to_bcd_uut/n73956 | 4| 995| 24.27% | | | bin_to_bcd_uut/n73949 | 5| 914| 22.30% | | | bin_to_bcd_uut/n73890 | 5| 910| 22.20% | | | bin_to_bcd_uut/bcd_code_24__N_380 | 10| 905| 22.08% | | | n67493 | 1| 882| 21.52% | | | bin_to_bcd_uut/bcd_code_24__N_407 | 9| 872| 21.27% | | | bin_to_bcd_uut/n74033 | 4| 857| 20.91% | | | bin_to_bcd_uut/bcd_code_24__N_402 | 5| 843| 20.57% | | | n12327 | 1| 830| 20.25% | | | bin_to_bcd_uut/n74093 | 5| 742| 18.10% | | | n12272 | 1| 725| 17.69% | | | bcd_code_24__N_371 | 7| 724| 17.66% | | | bin_to_bcd_uut/n74007 | 3| 687| 16.76% | | | bin_to_bcd_uut/n73981 | 4| 668| 16.30% | | | data_out_11 | 1| 632| 15.42% | | | bin_to_bcd_uut/bcd_code_24__N_527 | 5| 554| 13.52% | | | bin_to_bcd_uut/bcd_code_24__N_490 | 10| 547| 13.34% | | | bcd_code_24__N_481 | 7| 443| 10.81% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 30 clocks: Clock Domain: control_s/clk_c_generated_9 Source: control_s/SLICE_1579.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_8 Source: SLICE_1577.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_6 Source: control_s/SLICE_1477.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_5 Source: control_s/SLICE_1472.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_4 Source: control_s/SLICE_1473.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_3 Source: control_s/SLICE_1474.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_27 Source: control_s/SLICE_1465.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_26 Source: control_s/SLICE_1466.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_25 Source: control_s/SLICE_1467.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_24 Source: control_s/SLICE_1590.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_23 Source: control_s/SLICE_1591.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_22 Source: control_s/SLICE_1603.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_21 Source: control_s/SLICE_1591.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_20 Source: control_s/SLICE_1476.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_2 Source: control_s/SLICE_1475.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_19 Source: control_s/SLICE_1468.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_18 Source: control_s/SLICE_1469.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_17 Source: control_s/SLICE_1590.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_16 Source: control_s/SLICE_1589.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_15 Source: control_s/SLICE_1587.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_14 Source: control_s/SLICE_1579.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_13 Source: control_s/SLICE_1470.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_12 Source: control_s/SLICE_1471.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_11 Source: control_s/SLICE_1462.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_10 Source: control_s/SLICE_1589.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_1 Source: control_s/SLICE_1464.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: clk_c_generated_7 Source: SLICE_1577.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: clk_c_generated_28 Source: SLICE_1460.F0 Loads: 2 Covered under: FREQUENCY NET "clk_c_generated_28" 399.840000 MHz ; Data transfers from: Clock Domain: clk_c Source: clk.PAD Covered under: FREQUENCY NET "clk_c_generated_28" 399.840000 MHz ; Transfers: 2 Clock Domain: clk_c Source: clk.PAD Loads: 525 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Data transfers from: Clock Domain: control_s/clk_c_generated_9 Source: control_s/SLICE_1579.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_8 Source: SLICE_1577.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_6 Source: control_s/SLICE_1477.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_5 Source: control_s/SLICE_1472.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_4 Source: control_s/SLICE_1473.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_3 Source: control_s/SLICE_1474.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_27 Source: control_s/SLICE_1465.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_26 Source: control_s/SLICE_1466.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_25 Source: control_s/SLICE_1467.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_24 Source: control_s/SLICE_1590.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_23 Source: control_s/SLICE_1591.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_22 Source: control_s/SLICE_1603.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_21 Source: control_s/SLICE_1591.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_20 Source: control_s/SLICE_1476.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_2 Source: control_s/SLICE_1475.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_19 Source: control_s/SLICE_1468.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_18 Source: control_s/SLICE_1469.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_17 Source: control_s/SLICE_1590.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_16 Source: control_s/SLICE_1589.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_15 Source: control_s/SLICE_1587.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_14 Source: control_s/SLICE_1579.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_13 Source: control_s/SLICE_1470.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_12 Source: control_s/SLICE_1471.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_11 Source: control_s/SLICE_1462.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_10 Source: control_s/SLICE_1589.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_1 Source: control_s/SLICE_1464.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: clk_c_generated_7 Source: SLICE_1577.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: clk_c_generated_28 Source: SLICE_1460.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: DS18B20Z_uut/clk_1mhz Source: DS18B20Z_uut/SLICE_223.Q0 Loads: 20 No transfer within this clock domain is found Timing summary (Setup): --------------- Timing errors: 4099 Score: 137930347 Cumulative negative slack: 137930347 Constraints cover 2147483647 paths, 2 nets, and 11890 connections (93.87% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 Sun Feb 28 14:14:12 2021 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o step_impl1.tw1 -gui -msgset C:/Users/lzsh/Desktop/step/promote.xml step_impl1_map.ncd step_impl1.prf Design file: step_impl1_map.ncd Preference file: step_impl1.prf Device,speed: LCMXO2-4000HC,M Report level: verbose report, limited to 1 item per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "clk_c" 22.277000 MHz (0 errors)
  • 4096 items scored, 0 timing errors detected.
  • FREQUENCY NET "clk_c_generated_28" 399.840000 MHz (0 errors)
  • 3 items scored, 0 timing errors detected. 28 potential circuit loops found in timing analysis. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "clk_c" 22.277000 MHz ; 4096 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.351ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q u1/Uart_Rx_uut/uart_rx0_46 (from clk_c +) Destination: FF Data in u1/Uart_Rx_uut/uart_rx1_47 (to clk_c +) Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels. Constraint Details: 0.332ns physical path delay SLICE_644 to SLICE_644 meets -0.019ns M_HLD and 0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns Physical Path Details: Data path SLICE_644 to SLICE_644: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_644.CLK to SLICE_644.Q0 SLICE_644 (from clk_c) ROUTE 1 e 0.199 SLICE_644.Q0 to SLICE_644.M1 u1/Uart_Rx_uut/uart_rx0 (to clk_c) -------- 0.332 (40.1% logic, 59.9% route), 1 logic levels. ================================================================================ Preference: FREQUENCY NET "clk_c_generated_28" 399.840000 MHz ; 3 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 1.264ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_s/tone_flag_378_rep_1018 (from clk_c +) Destination: FF Data in control_s/i23400 (to clk_c_generated_28 +) Delay: 1.264ns (18.5% logic, 81.5% route), 2 logic levels. Constraint Details: 1.264ns physical path delay SLICE_1555 to control_s/SLICE_599 meets 0.000ns LSRREC_HLD and 0.000ns delay constraint requirement (totaling 0.000ns) by 1.264ns Physical Path Details: Data path SLICE_1555 to control_s/SLICE_599: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_1555.CLK to SLICE_1555.Q0 SLICE_1555 (from clk_c) ROUTE 68 e 0.515 SLICE_1555.Q0 to SLICE_1460.B1 n75906 CTOF_DEL --- 0.101 SLICE_1460.B1 to SLICE_1460.F1 SLICE_1460 ROUTE 1 e 0.515 SLICE_1460.F1 to *SLICE_599.LSR control_s/temp_out_31__N_1907 (to clk_c_generated_28) -------- 1.264 (18.5% logic, 81.5% route), 2 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "clk_c" 22.277000 MHz ; | 0.000 ns| 0.351 ns| 1 | | | FREQUENCY NET "clk_c_generated_28" | | | 399.840000 MHz ; | 0.000 ns| 1.264 ns| 2 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 30 clocks: Clock Domain: control_s/clk_c_generated_9 Source: control_s/SLICE_1579.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_8 Source: SLICE_1577.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_6 Source: control_s/SLICE_1477.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_5 Source: control_s/SLICE_1472.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_4 Source: control_s/SLICE_1473.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_3 Source: control_s/SLICE_1474.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_27 Source: control_s/SLICE_1465.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_26 Source: control_s/SLICE_1466.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_25 Source: control_s/SLICE_1467.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_24 Source: control_s/SLICE_1590.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_23 Source: control_s/SLICE_1591.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_22 Source: control_s/SLICE_1603.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_21 Source: control_s/SLICE_1591.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_20 Source: control_s/SLICE_1476.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_2 Source: control_s/SLICE_1475.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_19 Source: control_s/SLICE_1468.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_18 Source: control_s/SLICE_1469.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_17 Source: control_s/SLICE_1590.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_16 Source: control_s/SLICE_1589.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_15 Source: control_s/SLICE_1587.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_14 Source: control_s/SLICE_1579.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_13 Source: control_s/SLICE_1470.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_12 Source: control_s/SLICE_1471.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_11 Source: control_s/SLICE_1462.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_10 Source: control_s/SLICE_1589.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_1 Source: control_s/SLICE_1464.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: clk_c_generated_7 Source: SLICE_1577.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: clk_c_generated_28 Source: SLICE_1460.F0 Loads: 2 Covered under: FREQUENCY NET "clk_c_generated_28" 399.840000 MHz ; Data transfers from: Clock Domain: clk_c Source: clk.PAD Covered under: FREQUENCY NET "clk_c_generated_28" 399.840000 MHz ; Transfers: 2 Clock Domain: clk_c Source: clk.PAD Loads: 525 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Data transfers from: Clock Domain: control_s/clk_c_generated_9 Source: control_s/SLICE_1579.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_8 Source: SLICE_1577.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_6 Source: control_s/SLICE_1477.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_5 Source: control_s/SLICE_1472.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_4 Source: control_s/SLICE_1473.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_3 Source: control_s/SLICE_1474.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_27 Source: control_s/SLICE_1465.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_26 Source: control_s/SLICE_1466.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_25 Source: control_s/SLICE_1467.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_24 Source: control_s/SLICE_1590.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_23 Source: control_s/SLICE_1591.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_22 Source: control_s/SLICE_1603.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_21 Source: control_s/SLICE_1591.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_20 Source: control_s/SLICE_1476.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_2 Source: control_s/SLICE_1475.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_19 Source: control_s/SLICE_1468.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_18 Source: control_s/SLICE_1469.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_17 Source: control_s/SLICE_1590.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_16 Source: control_s/SLICE_1589.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_15 Source: control_s/SLICE_1587.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_14 Source: control_s/SLICE_1579.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_13 Source: control_s/SLICE_1470.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_12 Source: control_s/SLICE_1471.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_11 Source: control_s/SLICE_1462.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_10 Source: control_s/SLICE_1589.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_1 Source: control_s/SLICE_1464.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: clk_c_generated_7 Source: SLICE_1577.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: clk_c_generated_28 Source: SLICE_1460.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: DS18B20Z_uut/clk_1mhz Source: DS18B20Z_uut/SLICE_223.Q0 Loads: 20 No transfer within this clock domain is found Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 2147483647 paths, 2 nets, and 12390 connections (97.82% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 4099 (setup), 0 (hold) Score: 137930347 (setup), 0 (hold) Cumulative negative slack: 137930347 (137930347+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------