Place & Route TRACE Report

Loading design for application trce from file step_impl1.ncd.
Design name: step
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-4000HC
Package:     CSBGA132
Performance: 4
Loading device for application trce from file 'xo2c4000.nph' in environment: D:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Sun Feb 28 14:14:45 2021

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o step_impl1.twr -gui -msgset C:/Users/lzsh/Desktop/step/promote.xml step_impl1.ncd step_impl1.prf 
Design file:     step_impl1.ncd
Preference file: step_impl1.prf
Device,speed:    LCMXO2-4000HC,4
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY NET "clk_c" 22.277000 MHz (4096 errors)
  • 4096 items scored, 4096 timing errors detected. Warning: 4.113MHz is the maximum frequency for this preference.
  • FREQUENCY NET "clk_c_generated_28" 399.840000 MHz (1 errors)
  • 3 items scored, 1 timing error detected. Warning: 322.373MHz is the maximum frequency for this preference. 28 potential circuit loops found in timing analysis. Report Type: based on TRACE automatically generated preferences BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "clk_c" 22.277000 MHz ; 4096 items scored, 4096 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 6.487ns (weighted slack = -198.227ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_s/i23400 (from clk_c_generated_28 +) Destination: FF Data in OLED12832_uut/char_i0 (to clk_c +) Delay: 4.649ns (52.3% logic, 47.7% route), 5 logic levels. Constraint Details: 4.649ns physical path delay control_s/SLICE_599 to OLED12832_uut/SLICE_267 exceeds 1.469ns delay constraint less 3.141ns skew and 0.166ns DIN_SET requirement (totaling -1.838ns) by 6.487ns Physical Path Details: Data path control_s/SLICE_599 to OLED12832_uut/SLICE_267: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R14C19A.CLK to R14C19A.Q0 control_s/SLICE_599 (from clk_c_generated_28) ROUTE 3 0.652 R14C19A.Q0 to R15C19D.D0 n35742 CTOF_DEL --- 0.495 R15C19D.D0 to R15C19D.F0 SLICE_1576 ROUTE 1 0.693 R15C19D.F0 to R15C19B.B1 OLED12832_uut/n1 CTOF_DEL --- 0.495 R15C19B.B1 to R15C19B.F1 OLED12832_uut/SLICE_988 ROUTE 1 0.436 R15C19B.F1 to R15C19B.C0 OLED12832_uut/char_167_N_1235_0 CTOF_DEL --- 0.495 R15C19B.C0 to R15C19B.F0 OLED12832_uut/SLICE_988 ROUTE 1 0.436 R15C19B.F0 to R15C19A.C0 OLED12832_uut/n16_adj_3072 CTOF_DEL --- 0.495 R15C19A.C0 to R15C19A.F0 OLED12832_uut/SLICE_267 ROUTE 1 0.000 R15C19A.F0 to R15C19A.DI0 OLED12832_uut/char_167_N_904_0 (to clk_c) -------- 4.649 (52.3% logic, 47.7% route), 5 logic levels. Clock Skew Details: Source Clock Path clk to control_s/SLICE_599: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 525 3.044 C1.PADDI to R12C19D.CLK clk_c REG_DEL --- 0.452 R12C19D.CLK to R12C19D.Q0 SLICE_1555 ROUTE 68 1.569 R12C19D.Q0 to R14C19C.D0 n75906 CTOF_DEL --- 0.495 R14C19C.D0 to R14C19C.F0 SLICE_1460 ROUTE 2 0.625 R14C19C.F0 to R14C19A.CLK clk_c_generated_28 -------- 7.317 (28.4% logic, 71.6% route), 3 logic levels. Destination Clock Path clk to OLED12832_uut/SLICE_267: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 525 3.044 C1.PADDI to R15C19A.CLK clk_c -------- 4.176 (27.1% logic, 72.9% route), 1 logic levels. Error: The following path exceeds requirements by 4.789ns (weighted slack = -146.340ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_s/i23400 (from clk_c_generated_28 +) Destination: FF Data in control_s/temp_out_i0_23401_23402_set (to clk_c +) Delay: 2.384ns (39.7% logic, 60.3% route), 2 logic levels. Constraint Details: 2.384ns physical path delay control_s/SLICE_599 to control_s/SLICE_1301 exceeds 1.469ns delay constraint less 3.141ns skew and 0.733ns LSRREC_SET requirement (totaling -2.405ns) by 4.789ns Physical Path Details: Data path control_s/SLICE_599 to control_s/SLICE_1301: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R14C19A.CLK to R14C19A.Q0 control_s/SLICE_599 (from clk_c_generated_28) ROUTE 3 0.769 R14C19A.Q0 to R14C19C.C0 n35742 CTOF_DEL --- 0.495 R14C19C.C0 to R14C19C.F0 SLICE_1460 ROUTE 2 0.668 R14C19C.F0 to R14C19B.LSR clk_c_generated_28 (to clk_c) -------- 2.384 (39.7% logic, 60.3% route), 2 logic levels. Clock Skew Details: Source Clock Path clk to control_s/SLICE_599: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 525 3.044 C1.PADDI to R12C19D.CLK clk_c REG_DEL --- 0.452 R12C19D.CLK to R12C19D.Q0 SLICE_1555 ROUTE 68 1.569 R12C19D.Q0 to R14C19C.D0 n75906 CTOF_DEL --- 0.495 R14C19C.D0 to R14C19C.F0 SLICE_1460 ROUTE 2 0.625 R14C19C.F0 to R14C19A.CLK clk_c_generated_28 -------- 7.317 (28.4% logic, 71.6% route), 3 logic levels. Destination Clock Path clk to control_s/SLICE_1301: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 525 3.044 C1.PADDI to R14C19B.CLK clk_c -------- 4.176 (27.1% logic, 72.9% route), 1 logic levels. Error: The following path exceeds requirements by 34.182ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DS18B20Z_uut/data_out_i0_i1 (from clk_c +) Destination: FF Data in control_s/temp_out_i9_23433_23434_reset (to clk_c +) Delay: 78.723ns (31.4% logic, 68.6% route), 48 logic levels. Constraint Details: 78.723ns physical path delay DS18B20Z_uut/SLICE_1397 to SLICE_1447 exceeds 44.889ns delay constraint less 0.000ns skew and 0.348ns M_SET requirement (totaling 44.541ns) by 34.182ns Physical Path Details: Data path DS18B20Z_uut/SLICE_1397 to SLICE_1447: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R16C22D.CLK to R16C22D.Q1 DS18B20Z_uut/SLICE_1397 (from clk_c) ROUTE 5 1.313 R16C22D.Q1 to R14C22B.A0 data_out_1 C0TOFCO_DE --- 1.023 R14C22B.A0 to R14C22B.FCO SLICE_8 ROUTE 1 0.000 R14C22B.FCO to R14C22C.FCI n67399 FCITOFCO_D --- 0.162 R14C22C.FCI to R14C22C.FCO SLICE_4 ROUTE 1 0.000 R14C22C.FCO to R14C22D.FCI n67400 FCITOF0_DE --- 0.585 R14C22D.FCI to R14C22D.F0 SLICE_10 ROUTE 4 0.973 R14C22D.F0 to R14C23D.A1 temperature_code_10_N_1_5 CTOF_DEL --- 0.495 R14C23D.A1 to R14C23D.F1 SLICE_1559 ROUTE 2 2.786 R14C23D.F1 to R14C24B.A0 temperature_code_5 C0TOFCO_DE --- 1.023 R14C24B.A0 to R14C24B.FCO SLICE_5 ROUTE 1 0.000 R14C24B.FCO to R14C24C.FCI n67493 FCITOF1_DE --- 0.643 R14C24C.FCI to R14C24C.F1 SLICE_3 ROUTE 1 1.383 R14C24C.F1 to R16C24C.A0 n12272 C0TOFCO_DE --- 1.023 R16C24C.A0 to R16C24C.FCO SLICE_49 ROUTE 1 0.000 R16C24C.FCO to R16C24D.FCI n67512 FCITOF1_DE --- 0.643 R16C24D.FCI to R16C24D.F1 SLICE_48 ROUTE 1 1.925 R16C24D.F1 to R17C24B.A1 n12328 C1TOFCO_DE --- 0.889 R17C24B.A1 to R17C24B.FCO SLICE_88 ROUTE 1 0.000 R17C24B.FCO to R17C24C.FCI n67499 FCITOFCO_D --- 0.162 R17C24C.FCI to R17C24C.FCO SLICE_87 ROUTE 1 0.000 R17C24C.FCO to R17C24D.FCI n67500 FCITOFCO_D --- 0.162 R17C24D.FCI to R17C24D.FCO SLICE_86 ROUTE 1 0.000 R17C24D.FCO to R17C25A.FCI n67501 FCITOFCO_D --- 0.162 R17C25A.FCI to R17C25A.FCO SLICE_85 ROUTE 1 0.000 R17C25A.FCO to R17C25B.FCI n67502 FCITOF0_DE --- 0.585 R17C25B.FCI to R17C25B.F0 SLICE_70 ROUTE 11 1.454 R17C25B.F0 to R17C26D.A0 bin_code_18 CTOF_DEL --- 0.495 R17C26D.A0 to R17C26D.F0 bin_to_bcd_uut/SLICE_968 ROUTE 2 0.445 R17C26D.F0 to R17C26D.C1 bin_to_bcd_uut/n72938 CTOF_DEL --- 0.495 R17C26D.C1 to R17C26D.F1 bin_to_bcd_uut/SLICE_968 ROUTE 8 1.000 R17C26D.F1 to R17C26A.A0 n8366 CTOF_DEL --- 0.495 R17C26A.A0 to R17C26A.F0 SLICE_1076 ROUTE 9 1.000 R17C26A.F0 to R17C26C.A1 bcd_code_24__N_344 CTOF_DEL --- 0.495 R17C26C.A1 to R17C26C.F1 bin_to_bcd_uut/SLICE_1089 ROUTE 4 0.453 R17C26C.F1 to R17C26C.C0 bin_to_bcd_uut/n8370 CTOF_DEL --- 0.495 R17C26C.C0 to R17C26C.F0 bin_to_bcd_uut/SLICE_1089 ROUTE 4 1.466 R17C26C.F0 to R18C25D.B1 bin_to_bcd_uut/n74094 CTOF_DEL --- 0.495 R18C25D.B1 to R18C25D.F1 bin_to_bcd_uut/SLICE_1375 ROUTE 9 2.009 R18C25D.F1 to R18C22D.B1 n74081 CTOF_DEL --- 0.495 R18C22D.B1 to R18C22D.F1 bin_to_bcd_uut/SLICE_1487 ROUTE 1 0.645 R18C22D.F1 to R18C20B.D1 bin_to_bcd_uut/n35_adj_2946 CTOF_DEL --- 0.495 R18C20B.D1 to R18C20B.F1 bin_to_bcd_uut/SLICE_1114 ROUTE 8 1.426 R18C20B.F1 to R17C20B.M0 n23 MTOOFX_DEL --- 0.376 R17C20B.M0 to R17C20B.OFX0 i60382/SLICE_807 ROUTE 3 1.463 R17C20B.OFX0 to R18C22C.B1 bcd_code_24__N_367 CTOF_DEL --- 0.495 R18C22C.B1 to R18C22C.F1 bin_to_bcd_uut/SLICE_980 ROUTE 6 1.020 R18C22C.F1 to R18C23B.A1 bin_to_bcd_uut/n8378 CTOF_DEL --- 0.495 R18C23B.A1 to R18C23B.F1 bin_to_bcd_uut/SLICE_1371 ROUTE 6 1.840 R18C23B.F1 to R19C23B.A0 bin_to_bcd_uut/n74060 CTOF_DEL --- 0.495 R19C23B.A0 to R19C23B.F0 bin_to_bcd_uut/SLICE_1370 ROUTE 3 1.024 R19C23B.F0 to R19C24C.B1 bin_to_bcd_uut/n74055 CTOF_DEL --- 0.495 R19C24C.B1 to R19C24C.F1 bin_to_bcd_uut/SLICE_1343 ROUTE 11 1.550 R19C24C.F1 to R19C25B.D1 bin_to_bcd_uut/bcd_code_24__N_425 CTOF_DEL --- 0.495 R19C25B.D1 to R19C25B.F1 bin_to_bcd_uut/SLICE_1335 ROUTE 6 1.848 R19C25B.F1 to R18C28B.A1 bin_to_bcd_uut/n74030 CTOF_DEL --- 0.495 R18C28B.A1 to R18C28B.F1 bin_to_bcd_uut/SLICE_978 ROUTE 6 2.460 R18C28B.F1 to R18C25C.C1 bin_to_bcd_uut/n8391 CTOF_DEL --- 0.495 R18C25C.C1 to R18C25C.F1 bin_to_bcd_uut/SLICE_1331 ROUTE 4 1.949 R18C25C.F1 to R19C23D.A0 bin_to_bcd_uut/n74017 CTOF_DEL --- 0.495 R19C23D.A0 to R19C23D.F0 bin_to_bcd_uut/SLICE_1329 ROUTE 3 0.976 R19C23D.F0 to R19C23A.A0 bin_to_bcd_uut/n74007 CTOF_DEL --- 0.495 R19C23A.A0 to R19C23A.F0 bin_to_bcd_uut/SLICE_1319 ROUTE 5 1.059 R19C23A.F0 to R19C22A.D0 bin_to_bcd_uut/n73996 CTOF_DEL --- 0.495 R19C22A.D0 to R19C22A.F0 bin_to_bcd_uut/SLICE_1092 ROUTE 3 1.036 R19C22A.F0 to R20C22B.B0 bin_to_bcd_uut/n73989 CTOF_DEL --- 0.495 R20C22B.B0 to R20C22B.F0 bin_to_bcd_uut/SLICE_1602 ROUTE 4 1.029 R20C22B.F0 to R20C22D.B1 bin_to_bcd_uut/n73981 CTOF_DEL --- 0.495 R20C22D.B1 to R20C22D.F1 bin_to_bcd_uut/SLICE_1320 ROUTE 5 2.503 R20C22D.F1 to R20C27D.C0 bin_to_bcd_uut/bcd_code_24__N_527 CTOF_DEL --- 0.495 R20C27D.C0 to R20C27D.F0 bin_to_bcd_uut/SLICE_1547 ROUTE 5 0.445 R20C27D.F0 to R20C27C.C1 bin_to_bcd_uut/n73949 CTOF_DEL --- 0.495 R20C27C.C1 to R20C27C.F1 bin_to_bcd_uut/SLICE_1391 ROUTE 3 0.764 R20C27C.F1 to R20C27A.C1 bin_to_bcd_uut/n73939 CTOF_DEL --- 0.495 R20C27A.C1 to R20C27A.F1 bin_to_bcd_uut/SLICE_1361 ROUTE 11 1.954 R20C27A.F1 to R19C27B.D0 bin_to_bcd_uut/bcd_code_24__N_572 CTOF_DEL --- 0.495 R19C27B.D0 to R19C27B.F0 bin_to_bcd_uut/SLICE_1115 ROUTE 3 0.987 R19C27B.F0 to R19C26B.A1 bin_to_bcd_uut/n73924 CTOF_DEL --- 0.495 R19C26B.A1 to R19C26B.F1 bin_to_bcd_uut/SLICE_1310 ROUTE 9 1.067 R19C26B.F1 to R19C27D.B0 bin_to_bcd_uut/bcd_code_24__N_623 CTOF_DEL --- 0.495 R19C27D.B0 to R19C27D.F0 bin_to_bcd_uut/SLICE_1107 ROUTE 3 0.646 R19C27D.F0 to R19C28B.D0 bin_to_bcd_uut/n73911 CTOF_DEL --- 0.495 R19C28B.D0 to R19C28B.F0 bin_to_bcd_uut/SLICE_1368 ROUTE 9 1.000 R19C28B.F0 to R19C28D.A1 bin_to_bcd_uut/bcd_code_24__N_674 CTOF_DEL --- 0.495 R19C28D.A1 to R19C28D.F1 bin_to_bcd_uut/SLICE_1328 ROUTE 3 1.515 R19C28D.F1 to R19C20C.A1 bin_to_bcd_uut/n73898 CTOF_DEL --- 0.495 R19C20C.A1 to R19C20C.F1 bin_to_bcd_uut/SLICE_1593 ROUTE 5 1.764 R19C20C.F1 to R17C20D.A0 bin_to_bcd_uut/n73890 CTOF_DEL --- 0.495 R17C20D.A0 to R17C20D.F0 bin_to_bcd_uut/SLICE_1369 ROUTE 2 0.976 R17C20D.F0 to R17C20D.A1 bin_to_bcd_uut/n73884 CTOF_DEL --- 0.495 R17C20D.A1 to R17C20D.F1 bin_to_bcd_uut/SLICE_1369 ROUTE 3 0.991 R17C20D.F1 to R17C19B.A1 bin_to_bcd_uut/n4 CTOF_DEL --- 0.495 R17C19B.A1 to R17C19B.F1 SLICE_382 ROUTE 2 1.287 R17C19B.F1 to R17C27A.C0 bin_to_bcd_uut/n73872 CTOF_DEL --- 0.495 R17C27A.C0 to R17C27A.F0 SLICE_379 ROUTE 3 2.572 R17C27A.F0 to R12C18A.M0 bcd_code_13 (to clk_c) -------- 78.723 (31.4% logic, 68.6% route), 48 logic levels. Clock Skew Details: Source Clock Path clk to DS18B20Z_uut/SLICE_1397: Name Fanout Delay (ns) Site Resource ROUTE 525 3.044 C1.PADDI to R16C22D.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_1447: Name Fanout Delay (ns) Site Resource ROUTE 525 3.044 C1.PADDI to R12C18A.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 34.152ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DS18B20Z_uut/data_out_i0_i1 (from clk_c +) Destination: FF Data in control_s/temp_out_i9_23433_23434_reset (to clk_c +) Delay: 78.693ns (31.4% logic, 68.6% route), 49 logic levels. Constraint Details: 78.693ns physical path delay DS18B20Z_uut/SLICE_1397 to SLICE_1447 exceeds 44.889ns delay constraint less 0.000ns skew and 0.348ns M_SET requirement (totaling 44.541ns) by 34.152ns Physical Path Details: Data path DS18B20Z_uut/SLICE_1397 to SLICE_1447: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R16C22D.CLK to R16C22D.Q1 DS18B20Z_uut/SLICE_1397 (from clk_c) ROUTE 5 1.313 R16C22D.Q1 to R14C22B.A0 data_out_1 C0TOFCO_DE --- 1.023 R14C22B.A0 to R14C22B.FCO SLICE_8 ROUTE 1 0.000 R14C22B.FCO to R14C22C.FCI n67399 FCITOFCO_D --- 0.162 R14C22C.FCI to R14C22C.FCO SLICE_4 ROUTE 1 0.000 R14C22C.FCO to R14C22D.FCI n67400 FCITOF0_DE --- 0.585 R14C22D.FCI to R14C22D.F0 SLICE_10 ROUTE 4 0.973 R14C22D.F0 to R14C23D.A1 temperature_code_10_N_1_5 CTOF_DEL --- 0.495 R14C23D.A1 to R14C23D.F1 SLICE_1559 ROUTE 2 2.786 R14C23D.F1 to R14C24B.A0 temperature_code_5 C0TOFCO_DE --- 1.023 R14C24B.A0 to R14C24B.FCO SLICE_5 ROUTE 1 0.000 R14C24B.FCO to R14C24C.FCI n67493 FCITOF0_DE --- 0.585 R14C24C.FCI to R14C24C.F0 SLICE_3 ROUTE 1 1.383 R14C24C.F0 to R16C24B.A1 n12273 C1TOFCO_DE --- 0.889 R16C24B.A1 to R16C24B.FCO SLICE_50 ROUTE 1 0.000 R16C24B.FCO to R16C24C.FCI n67511 FCITOFCO_D --- 0.162 R16C24C.FCI to R16C24C.FCO SLICE_49 ROUTE 1 0.000 R16C24C.FCO to R16C24D.FCI n67512 FCITOF1_DE --- 0.643 R16C24D.FCI to R16C24D.F1 SLICE_48 ROUTE 1 1.925 R16C24D.F1 to R17C24B.A1 n12328 C1TOFCO_DE --- 0.889 R17C24B.A1 to R17C24B.FCO SLICE_88 ROUTE 1 0.000 R17C24B.FCO to R17C24C.FCI n67499 FCITOFCO_D --- 0.162 R17C24C.FCI to R17C24C.FCO SLICE_87 ROUTE 1 0.000 R17C24C.FCO to R17C24D.FCI n67500 FCITOFCO_D --- 0.162 R17C24D.FCI to R17C24D.FCO SLICE_86 ROUTE 1 0.000 R17C24D.FCO to R17C25A.FCI n67501 FCITOFCO_D --- 0.162 R17C25A.FCI to R17C25A.FCO SLICE_85 ROUTE 1 0.000 R17C25A.FCO to R17C25B.FCI n67502 FCITOF0_DE --- 0.585 R17C25B.FCI to R17C25B.F0 SLICE_70 ROUTE 11 1.454 R17C25B.F0 to R17C26D.A0 bin_code_18 CTOF_DEL --- 0.495 R17C26D.A0 to R17C26D.F0 bin_to_bcd_uut/SLICE_968 ROUTE 2 0.445 R17C26D.F0 to R17C26D.C1 bin_to_bcd_uut/n72938 CTOF_DEL --- 0.495 R17C26D.C1 to R17C26D.F1 bin_to_bcd_uut/SLICE_968 ROUTE 8 1.000 R17C26D.F1 to R17C26A.A0 n8366 CTOF_DEL --- 0.495 R17C26A.A0 to R17C26A.F0 SLICE_1076 ROUTE 9 1.000 R17C26A.F0 to R17C26C.A1 bcd_code_24__N_344 CTOF_DEL --- 0.495 R17C26C.A1 to R17C26C.F1 bin_to_bcd_uut/SLICE_1089 ROUTE 4 0.453 R17C26C.F1 to R17C26C.C0 bin_to_bcd_uut/n8370 CTOF_DEL --- 0.495 R17C26C.C0 to R17C26C.F0 bin_to_bcd_uut/SLICE_1089 ROUTE 4 1.466 R17C26C.F0 to R18C25D.B1 bin_to_bcd_uut/n74094 CTOF_DEL --- 0.495 R18C25D.B1 to R18C25D.F1 bin_to_bcd_uut/SLICE_1375 ROUTE 9 2.009 R18C25D.F1 to R18C22D.B1 n74081 CTOF_DEL --- 0.495 R18C22D.B1 to R18C22D.F1 bin_to_bcd_uut/SLICE_1487 ROUTE 1 0.645 R18C22D.F1 to R18C20B.D1 bin_to_bcd_uut/n35_adj_2946 CTOF_DEL --- 0.495 R18C20B.D1 to R18C20B.F1 bin_to_bcd_uut/SLICE_1114 ROUTE 8 1.426 R18C20B.F1 to R17C20B.M0 n23 MTOOFX_DEL --- 0.376 R17C20B.M0 to R17C20B.OFX0 i60382/SLICE_807 ROUTE 3 1.463 R17C20B.OFX0 to R18C22C.B1 bcd_code_24__N_367 CTOF_DEL --- 0.495 R18C22C.B1 to R18C22C.F1 bin_to_bcd_uut/SLICE_980 ROUTE 6 1.020 R18C22C.F1 to R18C23B.A1 bin_to_bcd_uut/n8378 CTOF_DEL --- 0.495 R18C23B.A1 to R18C23B.F1 bin_to_bcd_uut/SLICE_1371 ROUTE 6 1.840 R18C23B.F1 to R19C23B.A0 bin_to_bcd_uut/n74060 CTOF_DEL --- 0.495 R19C23B.A0 to R19C23B.F0 bin_to_bcd_uut/SLICE_1370 ROUTE 3 1.024 R19C23B.F0 to R19C24C.B1 bin_to_bcd_uut/n74055 CTOF_DEL --- 0.495 R19C24C.B1 to R19C24C.F1 bin_to_bcd_uut/SLICE_1343 ROUTE 11 1.550 R19C24C.F1 to R19C25B.D1 bin_to_bcd_uut/bcd_code_24__N_425 CTOF_DEL --- 0.495 R19C25B.D1 to R19C25B.F1 bin_to_bcd_uut/SLICE_1335 ROUTE 6 1.848 R19C25B.F1 to R18C28B.A1 bin_to_bcd_uut/n74030 CTOF_DEL --- 0.495 R18C28B.A1 to R18C28B.F1 bin_to_bcd_uut/SLICE_978 ROUTE 6 2.460 R18C28B.F1 to R18C25C.C1 bin_to_bcd_uut/n8391 CTOF_DEL --- 0.495 R18C25C.C1 to R18C25C.F1 bin_to_bcd_uut/SLICE_1331 ROUTE 4 1.949 R18C25C.F1 to R19C23D.A0 bin_to_bcd_uut/n74017 CTOF_DEL --- 0.495 R19C23D.A0 to R19C23D.F0 bin_to_bcd_uut/SLICE_1329 ROUTE 3 0.976 R19C23D.F0 to R19C23A.A0 bin_to_bcd_uut/n74007 CTOF_DEL --- 0.495 R19C23A.A0 to R19C23A.F0 bin_to_bcd_uut/SLICE_1319 ROUTE 5 1.059 R19C23A.F0 to R19C22A.D0 bin_to_bcd_uut/n73996 CTOF_DEL --- 0.495 R19C22A.D0 to R19C22A.F0 bin_to_bcd_uut/SLICE_1092 ROUTE 3 1.036 R19C22A.F0 to R20C22B.B0 bin_to_bcd_uut/n73989 CTOF_DEL --- 0.495 R20C22B.B0 to R20C22B.F0 bin_to_bcd_uut/SLICE_1602 ROUTE 4 1.029 R20C22B.F0 to R20C22D.B1 bin_to_bcd_uut/n73981 CTOF_DEL --- 0.495 R20C22D.B1 to R20C22D.F1 bin_to_bcd_uut/SLICE_1320 ROUTE 5 2.503 R20C22D.F1 to R20C27D.C0 bin_to_bcd_uut/bcd_code_24__N_527 CTOF_DEL --- 0.495 R20C27D.C0 to R20C27D.F0 bin_to_bcd_uut/SLICE_1547 ROUTE 5 0.445 R20C27D.F0 to R20C27C.C1 bin_to_bcd_uut/n73949 CTOF_DEL --- 0.495 R20C27C.C1 to R20C27C.F1 bin_to_bcd_uut/SLICE_1391 ROUTE 3 0.764 R20C27C.F1 to R20C27A.C1 bin_to_bcd_uut/n73939 CTOF_DEL --- 0.495 R20C27A.C1 to R20C27A.F1 bin_to_bcd_uut/SLICE_1361 ROUTE 11 1.954 R20C27A.F1 to R19C27B.D0 bin_to_bcd_uut/bcd_code_24__N_572 CTOF_DEL --- 0.495 R19C27B.D0 to R19C27B.F0 bin_to_bcd_uut/SLICE_1115 ROUTE 3 0.987 R19C27B.F0 to R19C26B.A1 bin_to_bcd_uut/n73924 CTOF_DEL --- 0.495 R19C26B.A1 to R19C26B.F1 bin_to_bcd_uut/SLICE_1310 ROUTE 9 1.067 R19C26B.F1 to R19C27D.B0 bin_to_bcd_uut/bcd_code_24__N_623 CTOF_DEL --- 0.495 R19C27D.B0 to R19C27D.F0 bin_to_bcd_uut/SLICE_1107 ROUTE 3 0.646 R19C27D.F0 to R19C28B.D0 bin_to_bcd_uut/n73911 CTOF_DEL --- 0.495 R19C28B.D0 to R19C28B.F0 bin_to_bcd_uut/SLICE_1368 ROUTE 9 1.000 R19C28B.F0 to R19C28D.A1 bin_to_bcd_uut/bcd_code_24__N_674 CTOF_DEL --- 0.495 R19C28D.A1 to R19C28D.F1 bin_to_bcd_uut/SLICE_1328 ROUTE 3 1.515 R19C28D.F1 to R19C20C.A1 bin_to_bcd_uut/n73898 CTOF_DEL --- 0.495 R19C20C.A1 to R19C20C.F1 bin_to_bcd_uut/SLICE_1593 ROUTE 5 1.764 R19C20C.F1 to R17C20D.A0 bin_to_bcd_uut/n73890 CTOF_DEL --- 0.495 R17C20D.A0 to R17C20D.F0 bin_to_bcd_uut/SLICE_1369 ROUTE 2 0.976 R17C20D.F0 to R17C20D.A1 bin_to_bcd_uut/n73884 CTOF_DEL --- 0.495 R17C20D.A1 to R17C20D.F1 bin_to_bcd_uut/SLICE_1369 ROUTE 3 0.991 R17C20D.F1 to R17C19B.A1 bin_to_bcd_uut/n4 CTOF_DEL --- 0.495 R17C19B.A1 to R17C19B.F1 SLICE_382 ROUTE 2 1.287 R17C19B.F1 to R17C27A.C0 bin_to_bcd_uut/n73872 CTOF_DEL --- 0.495 R17C27A.C0 to R17C27A.F0 SLICE_379 ROUTE 3 2.572 R17C27A.F0 to R12C18A.M0 bcd_code_13 (to clk_c) -------- 78.693 (31.4% logic, 68.6% route), 49 logic levels. Clock Skew Details: Source Clock Path clk to DS18B20Z_uut/SLICE_1397: Name Fanout Delay (ns) Site Resource ROUTE 525 3.044 C1.PADDI to R16C22D.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_1447: Name Fanout Delay (ns) Site Resource ROUTE 525 3.044 C1.PADDI to R12C18A.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 34.152ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DS18B20Z_uut/data_out_i0_i1 (from clk_c +) Destination: FF Data in control_s/temp_out_i9_23433_23434_reset (to clk_c +) Delay: 78.693ns (31.4% logic, 68.6% route), 49 logic levels. Constraint Details: 78.693ns physical path delay DS18B20Z_uut/SLICE_1397 to SLICE_1447 exceeds 44.889ns delay constraint less 0.000ns skew and 0.348ns M_SET requirement (totaling 44.541ns) by 34.152ns Physical Path Details: Data path DS18B20Z_uut/SLICE_1397 to SLICE_1447: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R16C22D.CLK to R16C22D.Q1 DS18B20Z_uut/SLICE_1397 (from clk_c) ROUTE 5 1.313 R16C22D.Q1 to R14C22B.A0 data_out_1 C0TOFCO_DE --- 1.023 R14C22B.A0 to R14C22B.FCO SLICE_8 ROUTE 1 0.000 R14C22B.FCO to R14C22C.FCI n67399 FCITOFCO_D --- 0.162 R14C22C.FCI to R14C22C.FCO SLICE_4 ROUTE 1 0.000 R14C22C.FCO to R14C22D.FCI n67400 FCITOF0_DE --- 0.585 R14C22D.FCI to R14C22D.F0 SLICE_10 ROUTE 4 0.973 R14C22D.F0 to R14C23D.A1 temperature_code_10_N_1_5 CTOF_DEL --- 0.495 R14C23D.A1 to R14C23D.F1 SLICE_1559 ROUTE 2 2.786 R14C23D.F1 to R14C24B.A0 temperature_code_5 C0TOFCO_DE --- 1.023 R14C24B.A0 to R14C24B.FCO SLICE_5 ROUTE 1 0.000 R14C24B.FCO to R14C24C.FCI n67493 FCITOFCO_D --- 0.162 R14C24C.FCI to R14C24C.FCO SLICE_3 ROUTE 1 0.000 R14C24C.FCO to R14C24D.FCI n67494 FCITOF0_DE --- 0.585 R14C24D.FCI to R14C24D.F0 SLICE_2 ROUTE 1 1.383 R14C24D.F0 to R16C24C.A1 n12271 C1TOFCO_DE --- 0.889 R16C24C.A1 to R16C24C.FCO SLICE_49 ROUTE 1 0.000 R16C24C.FCO to R16C24D.FCI n67512 FCITOF1_DE --- 0.643 R16C24D.FCI to R16C24D.F1 SLICE_48 ROUTE 1 1.925 R16C24D.F1 to R17C24B.A1 n12328 C1TOFCO_DE --- 0.889 R17C24B.A1 to R17C24B.FCO SLICE_88 ROUTE 1 0.000 R17C24B.FCO to R17C24C.FCI n67499 FCITOFCO_D --- 0.162 R17C24C.FCI to R17C24C.FCO SLICE_87 ROUTE 1 0.000 R17C24C.FCO to R17C24D.FCI n67500 FCITOFCO_D --- 0.162 R17C24D.FCI to R17C24D.FCO SLICE_86 ROUTE 1 0.000 R17C24D.FCO to R17C25A.FCI n67501 FCITOFCO_D --- 0.162 R17C25A.FCI to R17C25A.FCO SLICE_85 ROUTE 1 0.000 R17C25A.FCO to R17C25B.FCI n67502 FCITOF0_DE --- 0.585 R17C25B.FCI to R17C25B.F0 SLICE_70 ROUTE 11 1.454 R17C25B.F0 to R17C26D.A0 bin_code_18 CTOF_DEL --- 0.495 R17C26D.A0 to R17C26D.F0 bin_to_bcd_uut/SLICE_968 ROUTE 2 0.445 R17C26D.F0 to R17C26D.C1 bin_to_bcd_uut/n72938 CTOF_DEL --- 0.495 R17C26D.C1 to R17C26D.F1 bin_to_bcd_uut/SLICE_968 ROUTE 8 1.000 R17C26D.F1 to R17C26A.A0 n8366 CTOF_DEL --- 0.495 R17C26A.A0 to R17C26A.F0 SLICE_1076 ROUTE 9 1.000 R17C26A.F0 to R17C26C.A1 bcd_code_24__N_344 CTOF_DEL --- 0.495 R17C26C.A1 to R17C26C.F1 bin_to_bcd_uut/SLICE_1089 ROUTE 4 0.453 R17C26C.F1 to R17C26C.C0 bin_to_bcd_uut/n8370 CTOF_DEL --- 0.495 R17C26C.C0 to R17C26C.F0 bin_to_bcd_uut/SLICE_1089 ROUTE 4 1.466 R17C26C.F0 to R18C25D.B1 bin_to_bcd_uut/n74094 CTOF_DEL --- 0.495 R18C25D.B1 to R18C25D.F1 bin_to_bcd_uut/SLICE_1375 ROUTE 9 2.009 R18C25D.F1 to R18C22D.B1 n74081 CTOF_DEL --- 0.495 R18C22D.B1 to R18C22D.F1 bin_to_bcd_uut/SLICE_1487 ROUTE 1 0.645 R18C22D.F1 to R18C20B.D1 bin_to_bcd_uut/n35_adj_2946 CTOF_DEL --- 0.495 R18C20B.D1 to R18C20B.F1 bin_to_bcd_uut/SLICE_1114 ROUTE 8 1.426 R18C20B.F1 to R17C20B.M0 n23 MTOOFX_DEL --- 0.376 R17C20B.M0 to R17C20B.OFX0 i60382/SLICE_807 ROUTE 3 1.463 R17C20B.OFX0 to R18C22C.B1 bcd_code_24__N_367 CTOF_DEL --- 0.495 R18C22C.B1 to R18C22C.F1 bin_to_bcd_uut/SLICE_980 ROUTE 6 1.020 R18C22C.F1 to R18C23B.A1 bin_to_bcd_uut/n8378 CTOF_DEL --- 0.495 R18C23B.A1 to R18C23B.F1 bin_to_bcd_uut/SLICE_1371 ROUTE 6 1.840 R18C23B.F1 to R19C23B.A0 bin_to_bcd_uut/n74060 CTOF_DEL --- 0.495 R19C23B.A0 to R19C23B.F0 bin_to_bcd_uut/SLICE_1370 ROUTE 3 1.024 R19C23B.F0 to R19C24C.B1 bin_to_bcd_uut/n74055 CTOF_DEL --- 0.495 R19C24C.B1 to R19C24C.F1 bin_to_bcd_uut/SLICE_1343 ROUTE 11 1.550 R19C24C.F1 to R19C25B.D1 bin_to_bcd_uut/bcd_code_24__N_425 CTOF_DEL --- 0.495 R19C25B.D1 to R19C25B.F1 bin_to_bcd_uut/SLICE_1335 ROUTE 6 1.848 R19C25B.F1 to R18C28B.A1 bin_to_bcd_uut/n74030 CTOF_DEL --- 0.495 R18C28B.A1 to R18C28B.F1 bin_to_bcd_uut/SLICE_978 ROUTE 6 2.460 R18C28B.F1 to R18C25C.C1 bin_to_bcd_uut/n8391 CTOF_DEL --- 0.495 R18C25C.C1 to R18C25C.F1 bin_to_bcd_uut/SLICE_1331 ROUTE 4 1.949 R18C25C.F1 to R19C23D.A0 bin_to_bcd_uut/n74017 CTOF_DEL --- 0.495 R19C23D.A0 to R19C23D.F0 bin_to_bcd_uut/SLICE_1329 ROUTE 3 0.976 R19C23D.F0 to R19C23A.A0 bin_to_bcd_uut/n74007 CTOF_DEL --- 0.495 R19C23A.A0 to R19C23A.F0 bin_to_bcd_uut/SLICE_1319 ROUTE 5 1.059 R19C23A.F0 to R19C22A.D0 bin_to_bcd_uut/n73996 CTOF_DEL --- 0.495 R19C22A.D0 to R19C22A.F0 bin_to_bcd_uut/SLICE_1092 ROUTE 3 1.036 R19C22A.F0 to R20C22B.B0 bin_to_bcd_uut/n73989 CTOF_DEL --- 0.495 R20C22B.B0 to R20C22B.F0 bin_to_bcd_uut/SLICE_1602 ROUTE 4 1.029 R20C22B.F0 to R20C22D.B1 bin_to_bcd_uut/n73981 CTOF_DEL --- 0.495 R20C22D.B1 to R20C22D.F1 bin_to_bcd_uut/SLICE_1320 ROUTE 5 2.503 R20C22D.F1 to R20C27D.C0 bin_to_bcd_uut/bcd_code_24__N_527 CTOF_DEL --- 0.495 R20C27D.C0 to R20C27D.F0 bin_to_bcd_uut/SLICE_1547 ROUTE 5 0.445 R20C27D.F0 to R20C27C.C1 bin_to_bcd_uut/n73949 CTOF_DEL --- 0.495 R20C27C.C1 to R20C27C.F1 bin_to_bcd_uut/SLICE_1391 ROUTE 3 0.764 R20C27C.F1 to R20C27A.C1 bin_to_bcd_uut/n73939 CTOF_DEL --- 0.495 R20C27A.C1 to R20C27A.F1 bin_to_bcd_uut/SLICE_1361 ROUTE 11 1.954 R20C27A.F1 to R19C27B.D0 bin_to_bcd_uut/bcd_code_24__N_572 CTOF_DEL --- 0.495 R19C27B.D0 to R19C27B.F0 bin_to_bcd_uut/SLICE_1115 ROUTE 3 0.987 R19C27B.F0 to R19C26B.A1 bin_to_bcd_uut/n73924 CTOF_DEL --- 0.495 R19C26B.A1 to R19C26B.F1 bin_to_bcd_uut/SLICE_1310 ROUTE 9 1.067 R19C26B.F1 to R19C27D.B0 bin_to_bcd_uut/bcd_code_24__N_623 CTOF_DEL --- 0.495 R19C27D.B0 to R19C27D.F0 bin_to_bcd_uut/SLICE_1107 ROUTE 3 0.646 R19C27D.F0 to R19C28B.D0 bin_to_bcd_uut/n73911 CTOF_DEL --- 0.495 R19C28B.D0 to R19C28B.F0 bin_to_bcd_uut/SLICE_1368 ROUTE 9 1.000 R19C28B.F0 to R19C28D.A1 bin_to_bcd_uut/bcd_code_24__N_674 CTOF_DEL --- 0.495 R19C28D.A1 to R19C28D.F1 bin_to_bcd_uut/SLICE_1328 ROUTE 3 1.515 R19C28D.F1 to R19C20C.A1 bin_to_bcd_uut/n73898 CTOF_DEL --- 0.495 R19C20C.A1 to R19C20C.F1 bin_to_bcd_uut/SLICE_1593 ROUTE 5 1.764 R19C20C.F1 to R17C20D.A0 bin_to_bcd_uut/n73890 CTOF_DEL --- 0.495 R17C20D.A0 to R17C20D.F0 bin_to_bcd_uut/SLICE_1369 ROUTE 2 0.976 R17C20D.F0 to R17C20D.A1 bin_to_bcd_uut/n73884 CTOF_DEL --- 0.495 R17C20D.A1 to R17C20D.F1 bin_to_bcd_uut/SLICE_1369 ROUTE 3 0.991 R17C20D.F1 to R17C19B.A1 bin_to_bcd_uut/n4 CTOF_DEL --- 0.495 R17C19B.A1 to R17C19B.F1 SLICE_382 ROUTE 2 1.287 R17C19B.F1 to R17C27A.C0 bin_to_bcd_uut/n73872 CTOF_DEL --- 0.495 R17C27A.C0 to R17C27A.F0 SLICE_379 ROUTE 3 2.572 R17C27A.F0 to R12C18A.M0 bcd_code_13 (to clk_c) -------- 78.693 (31.4% logic, 68.6% route), 49 logic levels. Clock Skew Details: Source Clock Path clk to DS18B20Z_uut/SLICE_1397: Name Fanout Delay (ns) Site Resource ROUTE 525 3.044 C1.PADDI to R16C22D.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_1447: Name Fanout Delay (ns) Site Resource ROUTE 525 3.044 C1.PADDI to R12C18A.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 34.151ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DS18B20Z_uut/data_out_i0_i1 (from clk_c +) Destination: FF Data in control_s/temp_out_i9_23433_23434_reset (to clk_c +) Delay: 78.692ns (31.3% logic, 68.7% route), 48 logic levels. Constraint Details: 78.692ns physical path delay DS18B20Z_uut/SLICE_1397 to SLICE_1447 exceeds 44.889ns delay constraint less 0.000ns skew and 0.348ns M_SET requirement (totaling 44.541ns) by 34.151ns Physical Path Details: Data path DS18B20Z_uut/SLICE_1397 to SLICE_1447: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R16C22D.CLK to R16C22D.Q1 DS18B20Z_uut/SLICE_1397 (from clk_c) ROUTE 5 1.313 R16C22D.Q1 to R14C22B.A0 data_out_1 C0TOFCO_DE --- 1.023 R14C22B.A0 to R14C22B.FCO SLICE_8 ROUTE 1 0.000 R14C22B.FCO to R14C22C.FCI n67399 FCITOFCO_D --- 0.162 R14C22C.FCI to R14C22C.FCO SLICE_4 ROUTE 1 0.000 R14C22C.FCO to R14C22D.FCI n67400 FCITOF0_DE --- 0.585 R14C22D.FCI to R14C22D.F0 SLICE_10 ROUTE 4 0.973 R14C22D.F0 to R14C23D.A1 temperature_code_10_N_1_5 CTOF_DEL --- 0.495 R14C23D.A1 to R14C23D.F1 SLICE_1559 ROUTE 2 2.786 R14C23D.F1 to R14C24B.A0 temperature_code_5 C0TOFCO_DE --- 1.023 R14C24B.A0 to R14C24B.FCO SLICE_5 ROUTE 1 0.000 R14C24B.FCO to R14C24C.FCI n67493 FCITOF1_DE --- 0.643 R14C24C.FCI to R14C24C.F1 SLICE_3 ROUTE 1 1.383 R14C24C.F1 to R16C24C.A0 n12272 C0TOFCO_DE --- 1.023 R16C24C.A0 to R16C24C.FCO SLICE_49 ROUTE 1 0.000 R16C24C.FCO to R16C24D.FCI n67512 FCITOF1_DE --- 0.643 R16C24D.FCI to R16C24D.F1 SLICE_48 ROUTE 1 1.925 R16C24D.F1 to R17C24B.A1 n12328 C1TOFCO_DE --- 0.889 R17C24B.A1 to R17C24B.FCO SLICE_88 ROUTE 1 0.000 R17C24B.FCO to R17C24C.FCI n67499 FCITOFCO_D --- 0.162 R17C24C.FCI to R17C24C.FCO SLICE_87 ROUTE 1 0.000 R17C24C.FCO to R17C24D.FCI n67500 FCITOFCO_D --- 0.162 R17C24D.FCI to R17C24D.FCO SLICE_86 ROUTE 1 0.000 R17C24D.FCO to R17C25A.FCI n67501 FCITOFCO_D --- 0.162 R17C25A.FCI to R17C25A.FCO SLICE_85 ROUTE 1 0.000 R17C25A.FCO to R17C25B.FCI n67502 FCITOF0_DE --- 0.585 R17C25B.FCI to R17C25B.F0 SLICE_70 ROUTE 11 1.454 R17C25B.F0 to R17C26D.A0 bin_code_18 CTOF_DEL --- 0.495 R17C26D.A0 to R17C26D.F0 bin_to_bcd_uut/SLICE_968 ROUTE 2 0.445 R17C26D.F0 to R17C26D.C1 bin_to_bcd_uut/n72938 CTOF_DEL --- 0.495 R17C26D.C1 to R17C26D.F1 bin_to_bcd_uut/SLICE_968 ROUTE 8 1.032 R17C26D.F1 to R17C27C.M0 n8366 MTOOFX_DEL --- 0.376 R17C27C.M0 to R17C27C.OFX0 i60384/SLICE_806 ROUTE 5 1.056 R17C27C.OFX0 to R17C26C.B1 bcd_code_24__N_340 CTOF_DEL --- 0.495 R17C26C.B1 to R17C26C.F1 bin_to_bcd_uut/SLICE_1089 ROUTE 4 0.453 R17C26C.F1 to R17C26C.C0 bin_to_bcd_uut/n8370 CTOF_DEL --- 0.495 R17C26C.C0 to R17C26C.F0 bin_to_bcd_uut/SLICE_1089 ROUTE 4 1.466 R17C26C.F0 to R18C25D.B1 bin_to_bcd_uut/n74094 CTOF_DEL --- 0.495 R18C25D.B1 to R18C25D.F1 bin_to_bcd_uut/SLICE_1375 ROUTE 9 2.009 R18C25D.F1 to R18C22D.B1 n74081 CTOF_DEL --- 0.495 R18C22D.B1 to R18C22D.F1 bin_to_bcd_uut/SLICE_1487 ROUTE 1 0.645 R18C22D.F1 to R18C20B.D1 bin_to_bcd_uut/n35_adj_2946 CTOF_DEL --- 0.495 R18C20B.D1 to R18C20B.F1 bin_to_bcd_uut/SLICE_1114 ROUTE 8 1.426 R18C20B.F1 to R17C20B.M0 n23 MTOOFX_DEL --- 0.376 R17C20B.M0 to R17C20B.OFX0 i60382/SLICE_807 ROUTE 3 1.463 R17C20B.OFX0 to R18C22C.B1 bcd_code_24__N_367 CTOF_DEL --- 0.495 R18C22C.B1 to R18C22C.F1 bin_to_bcd_uut/SLICE_980 ROUTE 6 1.020 R18C22C.F1 to R18C23B.A1 bin_to_bcd_uut/n8378 CTOF_DEL --- 0.495 R18C23B.A1 to R18C23B.F1 bin_to_bcd_uut/SLICE_1371 ROUTE 6 1.840 R18C23B.F1 to R19C23B.A0 bin_to_bcd_uut/n74060 CTOF_DEL --- 0.495 R19C23B.A0 to R19C23B.F0 bin_to_bcd_uut/SLICE_1370 ROUTE 3 1.024 R19C23B.F0 to R19C24C.B1 bin_to_bcd_uut/n74055 CTOF_DEL --- 0.495 R19C24C.B1 to R19C24C.F1 bin_to_bcd_uut/SLICE_1343 ROUTE 11 1.550 R19C24C.F1 to R19C25B.D1 bin_to_bcd_uut/bcd_code_24__N_425 CTOF_DEL --- 0.495 R19C25B.D1 to R19C25B.F1 bin_to_bcd_uut/SLICE_1335 ROUTE 6 1.848 R19C25B.F1 to R18C28B.A1 bin_to_bcd_uut/n74030 CTOF_DEL --- 0.495 R18C28B.A1 to R18C28B.F1 bin_to_bcd_uut/SLICE_978 ROUTE 6 2.460 R18C28B.F1 to R18C25C.C1 bin_to_bcd_uut/n8391 CTOF_DEL --- 0.495 R18C25C.C1 to R18C25C.F1 bin_to_bcd_uut/SLICE_1331 ROUTE 4 1.949 R18C25C.F1 to R19C23D.A0 bin_to_bcd_uut/n74017 CTOF_DEL --- 0.495 R19C23D.A0 to R19C23D.F0 bin_to_bcd_uut/SLICE_1329 ROUTE 3 0.976 R19C23D.F0 to R19C23A.A0 bin_to_bcd_uut/n74007 CTOF_DEL --- 0.495 R19C23A.A0 to R19C23A.F0 bin_to_bcd_uut/SLICE_1319 ROUTE 5 1.059 R19C23A.F0 to R19C22A.D0 bin_to_bcd_uut/n73996 CTOF_DEL --- 0.495 R19C22A.D0 to R19C22A.F0 bin_to_bcd_uut/SLICE_1092 ROUTE 3 1.036 R19C22A.F0 to R20C22B.B0 bin_to_bcd_uut/n73989 CTOF_DEL --- 0.495 R20C22B.B0 to R20C22B.F0 bin_to_bcd_uut/SLICE_1602 ROUTE 4 1.029 R20C22B.F0 to R20C22D.B1 bin_to_bcd_uut/n73981 CTOF_DEL --- 0.495 R20C22D.B1 to R20C22D.F1 bin_to_bcd_uut/SLICE_1320 ROUTE 5 2.503 R20C22D.F1 to R20C27D.C0 bin_to_bcd_uut/bcd_code_24__N_527 CTOF_DEL --- 0.495 R20C27D.C0 to R20C27D.F0 bin_to_bcd_uut/SLICE_1547 ROUTE 5 0.445 R20C27D.F0 to R20C27C.C1 bin_to_bcd_uut/n73949 CTOF_DEL --- 0.495 R20C27C.C1 to R20C27C.F1 bin_to_bcd_uut/SLICE_1391 ROUTE 3 0.764 R20C27C.F1 to R20C27A.C1 bin_to_bcd_uut/n73939 CTOF_DEL --- 0.495 R20C27A.C1 to R20C27A.F1 bin_to_bcd_uut/SLICE_1361 ROUTE 11 1.954 R20C27A.F1 to R19C27B.D0 bin_to_bcd_uut/bcd_code_24__N_572 CTOF_DEL --- 0.495 R19C27B.D0 to R19C27B.F0 bin_to_bcd_uut/SLICE_1115 ROUTE 3 0.987 R19C27B.F0 to R19C26B.A1 bin_to_bcd_uut/n73924 CTOF_DEL --- 0.495 R19C26B.A1 to R19C26B.F1 bin_to_bcd_uut/SLICE_1310 ROUTE 9 1.067 R19C26B.F1 to R19C27D.B0 bin_to_bcd_uut/bcd_code_24__N_623 CTOF_DEL --- 0.495 R19C27D.B0 to R19C27D.F0 bin_to_bcd_uut/SLICE_1107 ROUTE 3 0.646 R19C27D.F0 to R19C28B.D0 bin_to_bcd_uut/n73911 CTOF_DEL --- 0.495 R19C28B.D0 to R19C28B.F0 bin_to_bcd_uut/SLICE_1368 ROUTE 9 1.000 R19C28B.F0 to R19C28D.A1 bin_to_bcd_uut/bcd_code_24__N_674 CTOF_DEL --- 0.495 R19C28D.A1 to R19C28D.F1 bin_to_bcd_uut/SLICE_1328 ROUTE 3 1.515 R19C28D.F1 to R19C20C.A1 bin_to_bcd_uut/n73898 CTOF_DEL --- 0.495 R19C20C.A1 to R19C20C.F1 bin_to_bcd_uut/SLICE_1593 ROUTE 5 1.764 R19C20C.F1 to R17C20D.A0 bin_to_bcd_uut/n73890 CTOF_DEL --- 0.495 R17C20D.A0 to R17C20D.F0 bin_to_bcd_uut/SLICE_1369 ROUTE 2 0.976 R17C20D.F0 to R17C20D.A1 bin_to_bcd_uut/n73884 CTOF_DEL --- 0.495 R17C20D.A1 to R17C20D.F1 bin_to_bcd_uut/SLICE_1369 ROUTE 3 0.991 R17C20D.F1 to R17C19B.A1 bin_to_bcd_uut/n4 CTOF_DEL --- 0.495 R17C19B.A1 to R17C19B.F1 SLICE_382 ROUTE 2 1.287 R17C19B.F1 to R17C27A.C0 bin_to_bcd_uut/n73872 CTOF_DEL --- 0.495 R17C27A.C0 to R17C27A.F0 SLICE_379 ROUTE 3 2.572 R17C27A.F0 to R12C18A.M0 bcd_code_13 (to clk_c) -------- 78.692 (31.3% logic, 68.7% route), 48 logic levels. Clock Skew Details: Source Clock Path clk to DS18B20Z_uut/SLICE_1397: Name Fanout Delay (ns) Site Resource ROUTE 525 3.044 C1.PADDI to R16C22D.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_1447: Name Fanout Delay (ns) Site Resource ROUTE 525 3.044 C1.PADDI to R12C18A.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 34.148ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DS18B20Z_uut/data_out_i0_i5 (from clk_c +) Destination: FF Data in control_s/temp_out_i9_23433_23434_reset (to clk_c +) Delay: 78.689ns (30.9% logic, 69.1% route), 47 logic levels. Constraint Details: 78.689ns physical path delay DS18B20Z_uut/SLICE_1490 to SLICE_1447 exceeds 44.889ns delay constraint less 0.000ns skew and 0.348ns M_SET requirement (totaling 44.541ns) by 34.148ns Physical Path Details: Data path DS18B20Z_uut/SLICE_1490 to SLICE_1447: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R13C24A.CLK to R13C24A.Q1 DS18B20Z_uut/SLICE_1490 (from clk_c) ROUTE 5 1.836 R13C24A.Q1 to R14C22D.A0 data_out_5 C0TOFCO_DE --- 1.023 R14C22D.A0 to R14C22D.FCO SLICE_10 ROUTE 1 0.000 R14C22D.FCO to R14C23A.FCI n67401 FCITOF1_DE --- 0.643 R14C23A.FCI to R14C23A.F1 SLICE_11 ROUTE 4 1.860 R14C23A.F1 to R15C24C.A1 temperature_code_10_N_1_8 CTOF_DEL --- 0.495 R15C24C.A1 to R15C24C.F1 SLICE_1600 ROUTE 2 1.772 R15C24C.F1 to R14C24C.B1 temperature_code_8 C1TOFCO_DE --- 0.889 R14C24C.B1 to R14C24C.FCO SLICE_3 ROUTE 1 0.000 R14C24C.FCO to R14C24D.FCI n67494 FCITOF0_DE --- 0.585 R14C24D.FCI to R14C24D.F0 SLICE_2 ROUTE 1 1.383 R14C24D.F0 to R16C24C.A1 n12271 C1TOFCO_DE --- 0.889 R16C24C.A1 to R16C24C.FCO SLICE_49 ROUTE 1 0.000 R16C24C.FCO to R16C24D.FCI n67512 FCITOF1_DE --- 0.643 R16C24D.FCI to R16C24D.F1 SLICE_48 ROUTE 1 1.925 R16C24D.F1 to R17C24B.A1 n12328 C1TOFCO_DE --- 0.889 R17C24B.A1 to R17C24B.FCO SLICE_88 ROUTE 1 0.000 R17C24B.FCO to R17C24C.FCI n67499 FCITOFCO_D --- 0.162 R17C24C.FCI to R17C24C.FCO SLICE_87 ROUTE 1 0.000 R17C24C.FCO to R17C24D.FCI n67500 FCITOFCO_D --- 0.162 R17C24D.FCI to R17C24D.FCO SLICE_86 ROUTE 1 0.000 R17C24D.FCO to R17C25A.FCI n67501 FCITOFCO_D --- 0.162 R17C25A.FCI to R17C25A.FCO SLICE_85 ROUTE 1 0.000 R17C25A.FCO to R17C25B.FCI n67502 FCITOF0_DE --- 0.585 R17C25B.FCI to R17C25B.F0 SLICE_70 ROUTE 11 1.454 R17C25B.F0 to R17C26D.A0 bin_code_18 CTOF_DEL --- 0.495 R17C26D.A0 to R17C26D.F0 bin_to_bcd_uut/SLICE_968 ROUTE 2 0.445 R17C26D.F0 to R17C26D.C1 bin_to_bcd_uut/n72938 CTOF_DEL --- 0.495 R17C26D.C1 to R17C26D.F1 bin_to_bcd_uut/SLICE_968 ROUTE 8 1.000 R17C26D.F1 to R17C26A.A0 n8366 CTOF_DEL --- 0.495 R17C26A.A0 to R17C26A.F0 SLICE_1076 ROUTE 9 1.000 R17C26A.F0 to R17C26C.A1 bcd_code_24__N_344 CTOF_DEL --- 0.495 R17C26C.A1 to R17C26C.F1 bin_to_bcd_uut/SLICE_1089 ROUTE 4 0.453 R17C26C.F1 to R17C26C.C0 bin_to_bcd_uut/n8370 CTOF_DEL --- 0.495 R17C26C.C0 to R17C26C.F0 bin_to_bcd_uut/SLICE_1089 ROUTE 4 1.466 R17C26C.F0 to R18C25D.B1 bin_to_bcd_uut/n74094 CTOF_DEL --- 0.495 R18C25D.B1 to R18C25D.F1 bin_to_bcd_uut/SLICE_1375 ROUTE 9 2.009 R18C25D.F1 to R18C22D.B1 n74081 CTOF_DEL --- 0.495 R18C22D.B1 to R18C22D.F1 bin_to_bcd_uut/SLICE_1487 ROUTE 1 0.645 R18C22D.F1 to R18C20B.D1 bin_to_bcd_uut/n35_adj_2946 CTOF_DEL --- 0.495 R18C20B.D1 to R18C20B.F1 bin_to_bcd_uut/SLICE_1114 ROUTE 8 1.426 R18C20B.F1 to R17C20B.M0 n23 MTOOFX_DEL --- 0.376 R17C20B.M0 to R17C20B.OFX0 i60382/SLICE_807 ROUTE 3 1.463 R17C20B.OFX0 to R18C22C.B1 bcd_code_24__N_367 CTOF_DEL --- 0.495 R18C22C.B1 to R18C22C.F1 bin_to_bcd_uut/SLICE_980 ROUTE 6 1.020 R18C22C.F1 to R18C23B.A1 bin_to_bcd_uut/n8378 CTOF_DEL --- 0.495 R18C23B.A1 to R18C23B.F1 bin_to_bcd_uut/SLICE_1371 ROUTE 6 1.840 R18C23B.F1 to R19C23B.A0 bin_to_bcd_uut/n74060 CTOF_DEL --- 0.495 R19C23B.A0 to R19C23B.F0 bin_to_bcd_uut/SLICE_1370 ROUTE 3 1.024 R19C23B.F0 to R19C24C.B1 bin_to_bcd_uut/n74055 CTOF_DEL --- 0.495 R19C24C.B1 to R19C24C.F1 bin_to_bcd_uut/SLICE_1343 ROUTE 11 1.550 R19C24C.F1 to R19C25B.D1 bin_to_bcd_uut/bcd_code_24__N_425 CTOF_DEL --- 0.495 R19C25B.D1 to R19C25B.F1 bin_to_bcd_uut/SLICE_1335 ROUTE 6 1.848 R19C25B.F1 to R18C28B.A1 bin_to_bcd_uut/n74030 CTOF_DEL --- 0.495 R18C28B.A1 to R18C28B.F1 bin_to_bcd_uut/SLICE_978 ROUTE 6 2.460 R18C28B.F1 to R18C25C.C1 bin_to_bcd_uut/n8391 CTOF_DEL --- 0.495 R18C25C.C1 to R18C25C.F1 bin_to_bcd_uut/SLICE_1331 ROUTE 4 1.949 R18C25C.F1 to R19C23D.A0 bin_to_bcd_uut/n74017 CTOF_DEL --- 0.495 R19C23D.A0 to R19C23D.F0 bin_to_bcd_uut/SLICE_1329 ROUTE 3 0.976 R19C23D.F0 to R19C23A.A0 bin_to_bcd_uut/n74007 CTOF_DEL --- 0.495 R19C23A.A0 to R19C23A.F0 bin_to_bcd_uut/SLICE_1319 ROUTE 5 1.059 R19C23A.F0 to R19C22A.D0 bin_to_bcd_uut/n73996 CTOF_DEL --- 0.495 R19C22A.D0 to R19C22A.F0 bin_to_bcd_uut/SLICE_1092 ROUTE 3 1.036 R19C22A.F0 to R20C22B.B0 bin_to_bcd_uut/n73989 CTOF_DEL --- 0.495 R20C22B.B0 to R20C22B.F0 bin_to_bcd_uut/SLICE_1602 ROUTE 4 1.029 R20C22B.F0 to R20C22D.B1 bin_to_bcd_uut/n73981 CTOF_DEL --- 0.495 R20C22D.B1 to R20C22D.F1 bin_to_bcd_uut/SLICE_1320 ROUTE 5 2.503 R20C22D.F1 to R20C27D.C0 bin_to_bcd_uut/bcd_code_24__N_527 CTOF_DEL --- 0.495 R20C27D.C0 to R20C27D.F0 bin_to_bcd_uut/SLICE_1547 ROUTE 5 0.445 R20C27D.F0 to R20C27C.C1 bin_to_bcd_uut/n73949 CTOF_DEL --- 0.495 R20C27C.C1 to R20C27C.F1 bin_to_bcd_uut/SLICE_1391 ROUTE 3 0.764 R20C27C.F1 to R20C27A.C1 bin_to_bcd_uut/n73939 CTOF_DEL --- 0.495 R20C27A.C1 to R20C27A.F1 bin_to_bcd_uut/SLICE_1361 ROUTE 11 1.954 R20C27A.F1 to R19C27B.D0 bin_to_bcd_uut/bcd_code_24__N_572 CTOF_DEL --- 0.495 R19C27B.D0 to R19C27B.F0 bin_to_bcd_uut/SLICE_1115 ROUTE 3 0.987 R19C27B.F0 to R19C26B.A1 bin_to_bcd_uut/n73924 CTOF_DEL --- 0.495 R19C26B.A1 to R19C26B.F1 bin_to_bcd_uut/SLICE_1310 ROUTE 9 1.067 R19C26B.F1 to R19C27D.B0 bin_to_bcd_uut/bcd_code_24__N_623 CTOF_DEL --- 0.495 R19C27D.B0 to R19C27D.F0 bin_to_bcd_uut/SLICE_1107 ROUTE 3 0.646 R19C27D.F0 to R19C28B.D0 bin_to_bcd_uut/n73911 CTOF_DEL --- 0.495 R19C28B.D0 to R19C28B.F0 bin_to_bcd_uut/SLICE_1368 ROUTE 9 1.000 R19C28B.F0 to R19C28D.A1 bin_to_bcd_uut/bcd_code_24__N_674 CTOF_DEL --- 0.495 R19C28D.A1 to R19C28D.F1 bin_to_bcd_uut/SLICE_1328 ROUTE 3 1.515 R19C28D.F1 to R19C20C.A1 bin_to_bcd_uut/n73898 CTOF_DEL --- 0.495 R19C20C.A1 to R19C20C.F1 bin_to_bcd_uut/SLICE_1593 ROUTE 5 1.764 R19C20C.F1 to R17C20D.A0 bin_to_bcd_uut/n73890 CTOF_DEL --- 0.495 R17C20D.A0 to R17C20D.F0 bin_to_bcd_uut/SLICE_1369 ROUTE 2 0.976 R17C20D.F0 to R17C20D.A1 bin_to_bcd_uut/n73884 CTOF_DEL --- 0.495 R17C20D.A1 to R17C20D.F1 bin_to_bcd_uut/SLICE_1369 ROUTE 3 0.991 R17C20D.F1 to R17C19B.A1 bin_to_bcd_uut/n4 CTOF_DEL --- 0.495 R17C19B.A1 to R17C19B.F1 SLICE_382 ROUTE 2 1.287 R17C19B.F1 to R17C27A.C0 bin_to_bcd_uut/n73872 CTOF_DEL --- 0.495 R17C27A.C0 to R17C27A.F0 SLICE_379 ROUTE 3 2.572 R17C27A.F0 to R12C18A.M0 bcd_code_13 (to clk_c) -------- 78.689 (30.9% logic, 69.1% route), 47 logic levels. Clock Skew Details: Source Clock Path clk to DS18B20Z_uut/SLICE_1490: Name Fanout Delay (ns) Site Resource ROUTE 525 3.044 C1.PADDI to R13C24A.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_1447: Name Fanout Delay (ns) Site Resource ROUTE 525 3.044 C1.PADDI to R12C18A.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 34.121ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DS18B20Z_uut/data_out_i0_i1 (from clk_c +) Destination: FF Data in control_s/temp_out_i9_23433_23434_reset (to clk_c +) Delay: 78.662ns (31.2% logic, 68.8% route), 49 logic levels. Constraint Details: 78.662ns physical path delay DS18B20Z_uut/SLICE_1397 to SLICE_1447 exceeds 44.889ns delay constraint less 0.000ns skew and 0.348ns M_SET requirement (totaling 44.541ns) by 34.121ns Physical Path Details: Data path DS18B20Z_uut/SLICE_1397 to SLICE_1447: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R16C22D.CLK to R16C22D.Q1 DS18B20Z_uut/SLICE_1397 (from clk_c) ROUTE 5 1.313 R16C22D.Q1 to R14C22B.A0 data_out_1 C0TOFCO_DE --- 1.023 R14C22B.A0 to R14C22B.FCO SLICE_8 ROUTE 1 0.000 R14C22B.FCO to R14C22C.FCI n67399 FCITOFCO_D --- 0.162 R14C22C.FCI to R14C22C.FCO SLICE_4 ROUTE 1 0.000 R14C22C.FCO to R14C22D.FCI n67400 FCITOF0_DE --- 0.585 R14C22D.FCI to R14C22D.F0 SLICE_10 ROUTE 4 0.973 R14C22D.F0 to R14C23D.A1 temperature_code_10_N_1_5 CTOF_DEL --- 0.495 R14C23D.A1 to R14C23D.F1 SLICE_1559 ROUTE 2 2.786 R14C23D.F1 to R14C24B.A0 temperature_code_5 C0TOFCO_DE --- 1.023 R14C24B.A0 to R14C24B.FCO SLICE_5 ROUTE 1 0.000 R14C24B.FCO to R14C24C.FCI n67493 FCITOF0_DE --- 0.585 R14C24C.FCI to R14C24C.F0 SLICE_3 ROUTE 1 1.383 R14C24C.F0 to R16C24B.A1 n12273 C1TOFCO_DE --- 0.889 R16C24B.A1 to R16C24B.FCO SLICE_50 ROUTE 1 0.000 R16C24B.FCO to R16C24C.FCI n67511 FCITOFCO_D --- 0.162 R16C24C.FCI to R16C24C.FCO SLICE_49 ROUTE 1 0.000 R16C24C.FCO to R16C24D.FCI n67512 FCITOF1_DE --- 0.643 R16C24D.FCI to R16C24D.F1 SLICE_48 ROUTE 1 1.925 R16C24D.F1 to R17C24B.A1 n12328 C1TOFCO_DE --- 0.889 R17C24B.A1 to R17C24B.FCO SLICE_88 ROUTE 1 0.000 R17C24B.FCO to R17C24C.FCI n67499 FCITOFCO_D --- 0.162 R17C24C.FCI to R17C24C.FCO SLICE_87 ROUTE 1 0.000 R17C24C.FCO to R17C24D.FCI n67500 FCITOFCO_D --- 0.162 R17C24D.FCI to R17C24D.FCO SLICE_86 ROUTE 1 0.000 R17C24D.FCO to R17C25A.FCI n67501 FCITOFCO_D --- 0.162 R17C25A.FCI to R17C25A.FCO SLICE_85 ROUTE 1 0.000 R17C25A.FCO to R17C25B.FCI n67502 FCITOF0_DE --- 0.585 R17C25B.FCI to R17C25B.F0 SLICE_70 ROUTE 11 1.454 R17C25B.F0 to R17C26D.A0 bin_code_18 CTOF_DEL --- 0.495 R17C26D.A0 to R17C26D.F0 bin_to_bcd_uut/SLICE_968 ROUTE 2 0.445 R17C26D.F0 to R17C26D.C1 bin_to_bcd_uut/n72938 CTOF_DEL --- 0.495 R17C26D.C1 to R17C26D.F1 bin_to_bcd_uut/SLICE_968 ROUTE 8 1.032 R17C26D.F1 to R17C27C.M0 n8366 MTOOFX_DEL --- 0.376 R17C27C.M0 to R17C27C.OFX0 i60384/SLICE_806 ROUTE 5 1.056 R17C27C.OFX0 to R17C26C.B1 bcd_code_24__N_340 CTOF_DEL --- 0.495 R17C26C.B1 to R17C26C.F1 bin_to_bcd_uut/SLICE_1089 ROUTE 4 0.453 R17C26C.F1 to R17C26C.C0 bin_to_bcd_uut/n8370 CTOF_DEL --- 0.495 R17C26C.C0 to R17C26C.F0 bin_to_bcd_uut/SLICE_1089 ROUTE 4 1.466 R17C26C.F0 to R18C25D.B1 bin_to_bcd_uut/n74094 CTOF_DEL --- 0.495 R18C25D.B1 to R18C25D.F1 bin_to_bcd_uut/SLICE_1375 ROUTE 9 2.009 R18C25D.F1 to R18C22D.B1 n74081 CTOF_DEL --- 0.495 R18C22D.B1 to R18C22D.F1 bin_to_bcd_uut/SLICE_1487 ROUTE 1 0.645 R18C22D.F1 to R18C20B.D1 bin_to_bcd_uut/n35_adj_2946 CTOF_DEL --- 0.495 R18C20B.D1 to R18C20B.F1 bin_to_bcd_uut/SLICE_1114 ROUTE 8 1.426 R18C20B.F1 to R17C20B.M0 n23 MTOOFX_DEL --- 0.376 R17C20B.M0 to R17C20B.OFX0 i60382/SLICE_807 ROUTE 3 1.463 R17C20B.OFX0 to R18C22C.B1 bcd_code_24__N_367 CTOF_DEL --- 0.495 R18C22C.B1 to R18C22C.F1 bin_to_bcd_uut/SLICE_980 ROUTE 6 1.020 R18C22C.F1 to R18C23B.A1 bin_to_bcd_uut/n8378 CTOF_DEL --- 0.495 R18C23B.A1 to R18C23B.F1 bin_to_bcd_uut/SLICE_1371 ROUTE 6 1.840 R18C23B.F1 to R19C23B.A0 bin_to_bcd_uut/n74060 CTOF_DEL --- 0.495 R19C23B.A0 to R19C23B.F0 bin_to_bcd_uut/SLICE_1370 ROUTE 3 1.024 R19C23B.F0 to R19C24C.B1 bin_to_bcd_uut/n74055 CTOF_DEL --- 0.495 R19C24C.B1 to R19C24C.F1 bin_to_bcd_uut/SLICE_1343 ROUTE 11 1.550 R19C24C.F1 to R19C25B.D1 bin_to_bcd_uut/bcd_code_24__N_425 CTOF_DEL --- 0.495 R19C25B.D1 to R19C25B.F1 bin_to_bcd_uut/SLICE_1335 ROUTE 6 1.848 R19C25B.F1 to R18C28B.A1 bin_to_bcd_uut/n74030 CTOF_DEL --- 0.495 R18C28B.A1 to R18C28B.F1 bin_to_bcd_uut/SLICE_978 ROUTE 6 2.460 R18C28B.F1 to R18C25C.C1 bin_to_bcd_uut/n8391 CTOF_DEL --- 0.495 R18C25C.C1 to R18C25C.F1 bin_to_bcd_uut/SLICE_1331 ROUTE 4 1.949 R18C25C.F1 to R19C23D.A0 bin_to_bcd_uut/n74017 CTOF_DEL --- 0.495 R19C23D.A0 to R19C23D.F0 bin_to_bcd_uut/SLICE_1329 ROUTE 3 0.976 R19C23D.F0 to R19C23A.A0 bin_to_bcd_uut/n74007 CTOF_DEL --- 0.495 R19C23A.A0 to R19C23A.F0 bin_to_bcd_uut/SLICE_1319 ROUTE 5 1.059 R19C23A.F0 to R19C22A.D0 bin_to_bcd_uut/n73996 CTOF_DEL --- 0.495 R19C22A.D0 to R19C22A.F0 bin_to_bcd_uut/SLICE_1092 ROUTE 3 1.036 R19C22A.F0 to R20C22B.B0 bin_to_bcd_uut/n73989 CTOF_DEL --- 0.495 R20C22B.B0 to R20C22B.F0 bin_to_bcd_uut/SLICE_1602 ROUTE 4 1.029 R20C22B.F0 to R20C22D.B1 bin_to_bcd_uut/n73981 CTOF_DEL --- 0.495 R20C22D.B1 to R20C22D.F1 bin_to_bcd_uut/SLICE_1320 ROUTE 5 2.503 R20C22D.F1 to R20C27D.C0 bin_to_bcd_uut/bcd_code_24__N_527 CTOF_DEL --- 0.495 R20C27D.C0 to R20C27D.F0 bin_to_bcd_uut/SLICE_1547 ROUTE 5 0.445 R20C27D.F0 to R20C27C.C1 bin_to_bcd_uut/n73949 CTOF_DEL --- 0.495 R20C27C.C1 to R20C27C.F1 bin_to_bcd_uut/SLICE_1391 ROUTE 3 0.764 R20C27C.F1 to R20C27A.C1 bin_to_bcd_uut/n73939 CTOF_DEL --- 0.495 R20C27A.C1 to R20C27A.F1 bin_to_bcd_uut/SLICE_1361 ROUTE 11 1.954 R20C27A.F1 to R19C27B.D0 bin_to_bcd_uut/bcd_code_24__N_572 CTOF_DEL --- 0.495 R19C27B.D0 to R19C27B.F0 bin_to_bcd_uut/SLICE_1115 ROUTE 3 0.987 R19C27B.F0 to R19C26B.A1 bin_to_bcd_uut/n73924 CTOF_DEL --- 0.495 R19C26B.A1 to R19C26B.F1 bin_to_bcd_uut/SLICE_1310 ROUTE 9 1.067 R19C26B.F1 to R19C27D.B0 bin_to_bcd_uut/bcd_code_24__N_623 CTOF_DEL --- 0.495 R19C27D.B0 to R19C27D.F0 bin_to_bcd_uut/SLICE_1107 ROUTE 3 0.646 R19C27D.F0 to R19C28B.D0 bin_to_bcd_uut/n73911 CTOF_DEL --- 0.495 R19C28B.D0 to R19C28B.F0 bin_to_bcd_uut/SLICE_1368 ROUTE 9 1.000 R19C28B.F0 to R19C28D.A1 bin_to_bcd_uut/bcd_code_24__N_674 CTOF_DEL --- 0.495 R19C28D.A1 to R19C28D.F1 bin_to_bcd_uut/SLICE_1328 ROUTE 3 1.515 R19C28D.F1 to R19C20C.A1 bin_to_bcd_uut/n73898 CTOF_DEL --- 0.495 R19C20C.A1 to R19C20C.F1 bin_to_bcd_uut/SLICE_1593 ROUTE 5 1.764 R19C20C.F1 to R17C20D.A0 bin_to_bcd_uut/n73890 CTOF_DEL --- 0.495 R17C20D.A0 to R17C20D.F0 bin_to_bcd_uut/SLICE_1369 ROUTE 2 0.976 R17C20D.F0 to R17C20D.A1 bin_to_bcd_uut/n73884 CTOF_DEL --- 0.495 R17C20D.A1 to R17C20D.F1 bin_to_bcd_uut/SLICE_1369 ROUTE 3 0.991 R17C20D.F1 to R17C19B.A1 bin_to_bcd_uut/n4 CTOF_DEL --- 0.495 R17C19B.A1 to R17C19B.F1 SLICE_382 ROUTE 2 1.287 R17C19B.F1 to R17C27A.C0 bin_to_bcd_uut/n73872 CTOF_DEL --- 0.495 R17C27A.C0 to R17C27A.F0 SLICE_379 ROUTE 3 2.572 R17C27A.F0 to R12C18A.M0 bcd_code_13 (to clk_c) -------- 78.662 (31.2% logic, 68.8% route), 49 logic levels. Clock Skew Details: Source Clock Path clk to DS18B20Z_uut/SLICE_1397: Name Fanout Delay (ns) Site Resource ROUTE 525 3.044 C1.PADDI to R16C22D.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_1447: Name Fanout Delay (ns) Site Resource ROUTE 525 3.044 C1.PADDI to R12C18A.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 34.121ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DS18B20Z_uut/data_out_i0_i1 (from clk_c +) Destination: FF Data in control_s/temp_out_i9_23433_23434_reset (to clk_c +) Delay: 78.662ns (31.2% logic, 68.8% route), 49 logic levels. Constraint Details: 78.662ns physical path delay DS18B20Z_uut/SLICE_1397 to SLICE_1447 exceeds 44.889ns delay constraint less 0.000ns skew and 0.348ns M_SET requirement (totaling 44.541ns) by 34.121ns Physical Path Details: Data path DS18B20Z_uut/SLICE_1397 to SLICE_1447: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R16C22D.CLK to R16C22D.Q1 DS18B20Z_uut/SLICE_1397 (from clk_c) ROUTE 5 1.313 R16C22D.Q1 to R14C22B.A0 data_out_1 C0TOFCO_DE --- 1.023 R14C22B.A0 to R14C22B.FCO SLICE_8 ROUTE 1 0.000 R14C22B.FCO to R14C22C.FCI n67399 FCITOFCO_D --- 0.162 R14C22C.FCI to R14C22C.FCO SLICE_4 ROUTE 1 0.000 R14C22C.FCO to R14C22D.FCI n67400 FCITOF0_DE --- 0.585 R14C22D.FCI to R14C22D.F0 SLICE_10 ROUTE 4 0.973 R14C22D.F0 to R14C23D.A1 temperature_code_10_N_1_5 CTOF_DEL --- 0.495 R14C23D.A1 to R14C23D.F1 SLICE_1559 ROUTE 2 2.786 R14C23D.F1 to R14C24B.A0 temperature_code_5 C0TOFCO_DE --- 1.023 R14C24B.A0 to R14C24B.FCO SLICE_5 ROUTE 1 0.000 R14C24B.FCO to R14C24C.FCI n67493 FCITOFCO_D --- 0.162 R14C24C.FCI to R14C24C.FCO SLICE_3 ROUTE 1 0.000 R14C24C.FCO to R14C24D.FCI n67494 FCITOF0_DE --- 0.585 R14C24D.FCI to R14C24D.F0 SLICE_2 ROUTE 1 1.383 R14C24D.F0 to R16C24C.A1 n12271 C1TOFCO_DE --- 0.889 R16C24C.A1 to R16C24C.FCO SLICE_49 ROUTE 1 0.000 R16C24C.FCO to R16C24D.FCI n67512 FCITOF1_DE --- 0.643 R16C24D.FCI to R16C24D.F1 SLICE_48 ROUTE 1 1.925 R16C24D.F1 to R17C24B.A1 n12328 C1TOFCO_DE --- 0.889 R17C24B.A1 to R17C24B.FCO SLICE_88 ROUTE 1 0.000 R17C24B.FCO to R17C24C.FCI n67499 FCITOFCO_D --- 0.162 R17C24C.FCI to R17C24C.FCO SLICE_87 ROUTE 1 0.000 R17C24C.FCO to R17C24D.FCI n67500 FCITOFCO_D --- 0.162 R17C24D.FCI to R17C24D.FCO SLICE_86 ROUTE 1 0.000 R17C24D.FCO to R17C25A.FCI n67501 FCITOFCO_D --- 0.162 R17C25A.FCI to R17C25A.FCO SLICE_85 ROUTE 1 0.000 R17C25A.FCO to R17C25B.FCI n67502 FCITOF0_DE --- 0.585 R17C25B.FCI to R17C25B.F0 SLICE_70 ROUTE 11 1.454 R17C25B.F0 to R17C26D.A0 bin_code_18 CTOF_DEL --- 0.495 R17C26D.A0 to R17C26D.F0 bin_to_bcd_uut/SLICE_968 ROUTE 2 0.445 R17C26D.F0 to R17C26D.C1 bin_to_bcd_uut/n72938 CTOF_DEL --- 0.495 R17C26D.C1 to R17C26D.F1 bin_to_bcd_uut/SLICE_968 ROUTE 8 1.032 R17C26D.F1 to R17C27C.M0 n8366 MTOOFX_DEL --- 0.376 R17C27C.M0 to R17C27C.OFX0 i60384/SLICE_806 ROUTE 5 1.056 R17C27C.OFX0 to R17C26C.B1 bcd_code_24__N_340 CTOF_DEL --- 0.495 R17C26C.B1 to R17C26C.F1 bin_to_bcd_uut/SLICE_1089 ROUTE 4 0.453 R17C26C.F1 to R17C26C.C0 bin_to_bcd_uut/n8370 CTOF_DEL --- 0.495 R17C26C.C0 to R17C26C.F0 bin_to_bcd_uut/SLICE_1089 ROUTE 4 1.466 R17C26C.F0 to R18C25D.B1 bin_to_bcd_uut/n74094 CTOF_DEL --- 0.495 R18C25D.B1 to R18C25D.F1 bin_to_bcd_uut/SLICE_1375 ROUTE 9 2.009 R18C25D.F1 to R18C22D.B1 n74081 CTOF_DEL --- 0.495 R18C22D.B1 to R18C22D.F1 bin_to_bcd_uut/SLICE_1487 ROUTE 1 0.645 R18C22D.F1 to R18C20B.D1 bin_to_bcd_uut/n35_adj_2946 CTOF_DEL --- 0.495 R18C20B.D1 to R18C20B.F1 bin_to_bcd_uut/SLICE_1114 ROUTE 8 1.426 R18C20B.F1 to R17C20B.M0 n23 MTOOFX_DEL --- 0.376 R17C20B.M0 to R17C20B.OFX0 i60382/SLICE_807 ROUTE 3 1.463 R17C20B.OFX0 to R18C22C.B1 bcd_code_24__N_367 CTOF_DEL --- 0.495 R18C22C.B1 to R18C22C.F1 bin_to_bcd_uut/SLICE_980 ROUTE 6 1.020 R18C22C.F1 to R18C23B.A1 bin_to_bcd_uut/n8378 CTOF_DEL --- 0.495 R18C23B.A1 to R18C23B.F1 bin_to_bcd_uut/SLICE_1371 ROUTE 6 1.840 R18C23B.F1 to R19C23B.A0 bin_to_bcd_uut/n74060 CTOF_DEL --- 0.495 R19C23B.A0 to R19C23B.F0 bin_to_bcd_uut/SLICE_1370 ROUTE 3 1.024 R19C23B.F0 to R19C24C.B1 bin_to_bcd_uut/n74055 CTOF_DEL --- 0.495 R19C24C.B1 to R19C24C.F1 bin_to_bcd_uut/SLICE_1343 ROUTE 11 1.550 R19C24C.F1 to R19C25B.D1 bin_to_bcd_uut/bcd_code_24__N_425 CTOF_DEL --- 0.495 R19C25B.D1 to R19C25B.F1 bin_to_bcd_uut/SLICE_1335 ROUTE 6 1.848 R19C25B.F1 to R18C28B.A1 bin_to_bcd_uut/n74030 CTOF_DEL --- 0.495 R18C28B.A1 to R18C28B.F1 bin_to_bcd_uut/SLICE_978 ROUTE 6 2.460 R18C28B.F1 to R18C25C.C1 bin_to_bcd_uut/n8391 CTOF_DEL --- 0.495 R18C25C.C1 to R18C25C.F1 bin_to_bcd_uut/SLICE_1331 ROUTE 4 1.949 R18C25C.F1 to R19C23D.A0 bin_to_bcd_uut/n74017 CTOF_DEL --- 0.495 R19C23D.A0 to R19C23D.F0 bin_to_bcd_uut/SLICE_1329 ROUTE 3 0.976 R19C23D.F0 to R19C23A.A0 bin_to_bcd_uut/n74007 CTOF_DEL --- 0.495 R19C23A.A0 to R19C23A.F0 bin_to_bcd_uut/SLICE_1319 ROUTE 5 1.059 R19C23A.F0 to R19C22A.D0 bin_to_bcd_uut/n73996 CTOF_DEL --- 0.495 R19C22A.D0 to R19C22A.F0 bin_to_bcd_uut/SLICE_1092 ROUTE 3 1.036 R19C22A.F0 to R20C22B.B0 bin_to_bcd_uut/n73989 CTOF_DEL --- 0.495 R20C22B.B0 to R20C22B.F0 bin_to_bcd_uut/SLICE_1602 ROUTE 4 1.029 R20C22B.F0 to R20C22D.B1 bin_to_bcd_uut/n73981 CTOF_DEL --- 0.495 R20C22D.B1 to R20C22D.F1 bin_to_bcd_uut/SLICE_1320 ROUTE 5 2.503 R20C22D.F1 to R20C27D.C0 bin_to_bcd_uut/bcd_code_24__N_527 CTOF_DEL --- 0.495 R20C27D.C0 to R20C27D.F0 bin_to_bcd_uut/SLICE_1547 ROUTE 5 0.445 R20C27D.F0 to R20C27C.C1 bin_to_bcd_uut/n73949 CTOF_DEL --- 0.495 R20C27C.C1 to R20C27C.F1 bin_to_bcd_uut/SLICE_1391 ROUTE 3 0.764 R20C27C.F1 to R20C27A.C1 bin_to_bcd_uut/n73939 CTOF_DEL --- 0.495 R20C27A.C1 to R20C27A.F1 bin_to_bcd_uut/SLICE_1361 ROUTE 11 1.954 R20C27A.F1 to R19C27B.D0 bin_to_bcd_uut/bcd_code_24__N_572 CTOF_DEL --- 0.495 R19C27B.D0 to R19C27B.F0 bin_to_bcd_uut/SLICE_1115 ROUTE 3 0.987 R19C27B.F0 to R19C26B.A1 bin_to_bcd_uut/n73924 CTOF_DEL --- 0.495 R19C26B.A1 to R19C26B.F1 bin_to_bcd_uut/SLICE_1310 ROUTE 9 1.067 R19C26B.F1 to R19C27D.B0 bin_to_bcd_uut/bcd_code_24__N_623 CTOF_DEL --- 0.495 R19C27D.B0 to R19C27D.F0 bin_to_bcd_uut/SLICE_1107 ROUTE 3 0.646 R19C27D.F0 to R19C28B.D0 bin_to_bcd_uut/n73911 CTOF_DEL --- 0.495 R19C28B.D0 to R19C28B.F0 bin_to_bcd_uut/SLICE_1368 ROUTE 9 1.000 R19C28B.F0 to R19C28D.A1 bin_to_bcd_uut/bcd_code_24__N_674 CTOF_DEL --- 0.495 R19C28D.A1 to R19C28D.F1 bin_to_bcd_uut/SLICE_1328 ROUTE 3 1.515 R19C28D.F1 to R19C20C.A1 bin_to_bcd_uut/n73898 CTOF_DEL --- 0.495 R19C20C.A1 to R19C20C.F1 bin_to_bcd_uut/SLICE_1593 ROUTE 5 1.764 R19C20C.F1 to R17C20D.A0 bin_to_bcd_uut/n73890 CTOF_DEL --- 0.495 R17C20D.A0 to R17C20D.F0 bin_to_bcd_uut/SLICE_1369 ROUTE 2 0.976 R17C20D.F0 to R17C20D.A1 bin_to_bcd_uut/n73884 CTOF_DEL --- 0.495 R17C20D.A1 to R17C20D.F1 bin_to_bcd_uut/SLICE_1369 ROUTE 3 0.991 R17C20D.F1 to R17C19B.A1 bin_to_bcd_uut/n4 CTOF_DEL --- 0.495 R17C19B.A1 to R17C19B.F1 SLICE_382 ROUTE 2 1.287 R17C19B.F1 to R17C27A.C0 bin_to_bcd_uut/n73872 CTOF_DEL --- 0.495 R17C27A.C0 to R17C27A.F0 SLICE_379 ROUTE 3 2.572 R17C27A.F0 to R12C18A.M0 bcd_code_13 (to clk_c) -------- 78.662 (31.2% logic, 68.8% route), 49 logic levels. Clock Skew Details: Source Clock Path clk to DS18B20Z_uut/SLICE_1397: Name Fanout Delay (ns) Site Resource ROUTE 525 3.044 C1.PADDI to R16C22D.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_1447: Name Fanout Delay (ns) Site Resource ROUTE 525 3.044 C1.PADDI to R12C18A.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 34.117ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DS18B20Z_uut/data_out_i0_i5 (from clk_c +) Destination: FF Data in control_s/temp_out_i9_23433_23434_reset (to clk_c +) Delay: 78.658ns (30.7% logic, 69.3% route), 47 logic levels. Constraint Details: 78.658ns physical path delay DS18B20Z_uut/SLICE_1490 to SLICE_1447 exceeds 44.889ns delay constraint less 0.000ns skew and 0.348ns M_SET requirement (totaling 44.541ns) by 34.117ns Physical Path Details: Data path DS18B20Z_uut/SLICE_1490 to SLICE_1447: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R13C24A.CLK to R13C24A.Q1 DS18B20Z_uut/SLICE_1490 (from clk_c) ROUTE 5 1.836 R13C24A.Q1 to R14C22D.A0 data_out_5 C0TOFCO_DE --- 1.023 R14C22D.A0 to R14C22D.FCO SLICE_10 ROUTE 1 0.000 R14C22D.FCO to R14C23A.FCI n67401 FCITOF1_DE --- 0.643 R14C23A.FCI to R14C23A.F1 SLICE_11 ROUTE 4 1.860 R14C23A.F1 to R15C24C.A1 temperature_code_10_N_1_8 CTOF_DEL --- 0.495 R15C24C.A1 to R15C24C.F1 SLICE_1600 ROUTE 2 1.772 R15C24C.F1 to R14C24C.B1 temperature_code_8 C1TOFCO_DE --- 0.889 R14C24C.B1 to R14C24C.FCO SLICE_3 ROUTE 1 0.000 R14C24C.FCO to R14C24D.FCI n67494 FCITOF0_DE --- 0.585 R14C24D.FCI to R14C24D.F0 SLICE_2 ROUTE 1 1.383 R14C24D.F0 to R16C24C.A1 n12271 C1TOFCO_DE --- 0.889 R16C24C.A1 to R16C24C.FCO SLICE_49 ROUTE 1 0.000 R16C24C.FCO to R16C24D.FCI n67512 FCITOF1_DE --- 0.643 R16C24D.FCI to R16C24D.F1 SLICE_48 ROUTE 1 1.925 R16C24D.F1 to R17C24B.A1 n12328 C1TOFCO_DE --- 0.889 R17C24B.A1 to R17C24B.FCO SLICE_88 ROUTE 1 0.000 R17C24B.FCO to R17C24C.FCI n67499 FCITOFCO_D --- 0.162 R17C24C.FCI to R17C24C.FCO SLICE_87 ROUTE 1 0.000 R17C24C.FCO to R17C24D.FCI n67500 FCITOFCO_D --- 0.162 R17C24D.FCI to R17C24D.FCO SLICE_86 ROUTE 1 0.000 R17C24D.FCO to R17C25A.FCI n67501 FCITOFCO_D --- 0.162 R17C25A.FCI to R17C25A.FCO SLICE_85 ROUTE 1 0.000 R17C25A.FCO to R17C25B.FCI n67502 FCITOF0_DE --- 0.585 R17C25B.FCI to R17C25B.F0 SLICE_70 ROUTE 11 1.454 R17C25B.F0 to R17C26D.A0 bin_code_18 CTOF_DEL --- 0.495 R17C26D.A0 to R17C26D.F0 bin_to_bcd_uut/SLICE_968 ROUTE 2 0.445 R17C26D.F0 to R17C26D.C1 bin_to_bcd_uut/n72938 CTOF_DEL --- 0.495 R17C26D.C1 to R17C26D.F1 bin_to_bcd_uut/SLICE_968 ROUTE 8 1.032 R17C26D.F1 to R17C27C.M0 n8366 MTOOFX_DEL --- 0.376 R17C27C.M0 to R17C27C.OFX0 i60384/SLICE_806 ROUTE 5 1.056 R17C27C.OFX0 to R17C26C.B1 bcd_code_24__N_340 CTOF_DEL --- 0.495 R17C26C.B1 to R17C26C.F1 bin_to_bcd_uut/SLICE_1089 ROUTE 4 0.453 R17C26C.F1 to R17C26C.C0 bin_to_bcd_uut/n8370 CTOF_DEL --- 0.495 R17C26C.C0 to R17C26C.F0 bin_to_bcd_uut/SLICE_1089 ROUTE 4 1.466 R17C26C.F0 to R18C25D.B1 bin_to_bcd_uut/n74094 CTOF_DEL --- 0.495 R18C25D.B1 to R18C25D.F1 bin_to_bcd_uut/SLICE_1375 ROUTE 9 2.009 R18C25D.F1 to R18C22D.B1 n74081 CTOF_DEL --- 0.495 R18C22D.B1 to R18C22D.F1 bin_to_bcd_uut/SLICE_1487 ROUTE 1 0.645 R18C22D.F1 to R18C20B.D1 bin_to_bcd_uut/n35_adj_2946 CTOF_DEL --- 0.495 R18C20B.D1 to R18C20B.F1 bin_to_bcd_uut/SLICE_1114 ROUTE 8 1.426 R18C20B.F1 to R17C20B.M0 n23 MTOOFX_DEL --- 0.376 R17C20B.M0 to R17C20B.OFX0 i60382/SLICE_807 ROUTE 3 1.463 R17C20B.OFX0 to R18C22C.B1 bcd_code_24__N_367 CTOF_DEL --- 0.495 R18C22C.B1 to R18C22C.F1 bin_to_bcd_uut/SLICE_980 ROUTE 6 1.020 R18C22C.F1 to R18C23B.A1 bin_to_bcd_uut/n8378 CTOF_DEL --- 0.495 R18C23B.A1 to R18C23B.F1 bin_to_bcd_uut/SLICE_1371 ROUTE 6 1.840 R18C23B.F1 to R19C23B.A0 bin_to_bcd_uut/n74060 CTOF_DEL --- 0.495 R19C23B.A0 to R19C23B.F0 bin_to_bcd_uut/SLICE_1370 ROUTE 3 1.024 R19C23B.F0 to R19C24C.B1 bin_to_bcd_uut/n74055 CTOF_DEL --- 0.495 R19C24C.B1 to R19C24C.F1 bin_to_bcd_uut/SLICE_1343 ROUTE 11 1.550 R19C24C.F1 to R19C25B.D1 bin_to_bcd_uut/bcd_code_24__N_425 CTOF_DEL --- 0.495 R19C25B.D1 to R19C25B.F1 bin_to_bcd_uut/SLICE_1335 ROUTE 6 1.848 R19C25B.F1 to R18C28B.A1 bin_to_bcd_uut/n74030 CTOF_DEL --- 0.495 R18C28B.A1 to R18C28B.F1 bin_to_bcd_uut/SLICE_978 ROUTE 6 2.460 R18C28B.F1 to R18C25C.C1 bin_to_bcd_uut/n8391 CTOF_DEL --- 0.495 R18C25C.C1 to R18C25C.F1 bin_to_bcd_uut/SLICE_1331 ROUTE 4 1.949 R18C25C.F1 to R19C23D.A0 bin_to_bcd_uut/n74017 CTOF_DEL --- 0.495 R19C23D.A0 to R19C23D.F0 bin_to_bcd_uut/SLICE_1329 ROUTE 3 0.976 R19C23D.F0 to R19C23A.A0 bin_to_bcd_uut/n74007 CTOF_DEL --- 0.495 R19C23A.A0 to R19C23A.F0 bin_to_bcd_uut/SLICE_1319 ROUTE 5 1.059 R19C23A.F0 to R19C22A.D0 bin_to_bcd_uut/n73996 CTOF_DEL --- 0.495 R19C22A.D0 to R19C22A.F0 bin_to_bcd_uut/SLICE_1092 ROUTE 3 1.036 R19C22A.F0 to R20C22B.B0 bin_to_bcd_uut/n73989 CTOF_DEL --- 0.495 R20C22B.B0 to R20C22B.F0 bin_to_bcd_uut/SLICE_1602 ROUTE 4 1.029 R20C22B.F0 to R20C22D.B1 bin_to_bcd_uut/n73981 CTOF_DEL --- 0.495 R20C22D.B1 to R20C22D.F1 bin_to_bcd_uut/SLICE_1320 ROUTE 5 2.503 R20C22D.F1 to R20C27D.C0 bin_to_bcd_uut/bcd_code_24__N_527 CTOF_DEL --- 0.495 R20C27D.C0 to R20C27D.F0 bin_to_bcd_uut/SLICE_1547 ROUTE 5 0.445 R20C27D.F0 to R20C27C.C1 bin_to_bcd_uut/n73949 CTOF_DEL --- 0.495 R20C27C.C1 to R20C27C.F1 bin_to_bcd_uut/SLICE_1391 ROUTE 3 0.764 R20C27C.F1 to R20C27A.C1 bin_to_bcd_uut/n73939 CTOF_DEL --- 0.495 R20C27A.C1 to R20C27A.F1 bin_to_bcd_uut/SLICE_1361 ROUTE 11 1.954 R20C27A.F1 to R19C27B.D0 bin_to_bcd_uut/bcd_code_24__N_572 CTOF_DEL --- 0.495 R19C27B.D0 to R19C27B.F0 bin_to_bcd_uut/SLICE_1115 ROUTE 3 0.987 R19C27B.F0 to R19C26B.A1 bin_to_bcd_uut/n73924 CTOF_DEL --- 0.495 R19C26B.A1 to R19C26B.F1 bin_to_bcd_uut/SLICE_1310 ROUTE 9 1.067 R19C26B.F1 to R19C27D.B0 bin_to_bcd_uut/bcd_code_24__N_623 CTOF_DEL --- 0.495 R19C27D.B0 to R19C27D.F0 bin_to_bcd_uut/SLICE_1107 ROUTE 3 0.646 R19C27D.F0 to R19C28B.D0 bin_to_bcd_uut/n73911 CTOF_DEL --- 0.495 R19C28B.D0 to R19C28B.F0 bin_to_bcd_uut/SLICE_1368 ROUTE 9 1.000 R19C28B.F0 to R19C28D.A1 bin_to_bcd_uut/bcd_code_24__N_674 CTOF_DEL --- 0.495 R19C28D.A1 to R19C28D.F1 bin_to_bcd_uut/SLICE_1328 ROUTE 3 1.515 R19C28D.F1 to R19C20C.A1 bin_to_bcd_uut/n73898 CTOF_DEL --- 0.495 R19C20C.A1 to R19C20C.F1 bin_to_bcd_uut/SLICE_1593 ROUTE 5 1.764 R19C20C.F1 to R17C20D.A0 bin_to_bcd_uut/n73890 CTOF_DEL --- 0.495 R17C20D.A0 to R17C20D.F0 bin_to_bcd_uut/SLICE_1369 ROUTE 2 0.976 R17C20D.F0 to R17C20D.A1 bin_to_bcd_uut/n73884 CTOF_DEL --- 0.495 R17C20D.A1 to R17C20D.F1 bin_to_bcd_uut/SLICE_1369 ROUTE 3 0.991 R17C20D.F1 to R17C19B.A1 bin_to_bcd_uut/n4 CTOF_DEL --- 0.495 R17C19B.A1 to R17C19B.F1 SLICE_382 ROUTE 2 1.287 R17C19B.F1 to R17C27A.C0 bin_to_bcd_uut/n73872 CTOF_DEL --- 0.495 R17C27A.C0 to R17C27A.F0 SLICE_379 ROUTE 3 2.572 R17C27A.F0 to R12C18A.M0 bcd_code_13 (to clk_c) -------- 78.658 (30.7% logic, 69.3% route), 47 logic levels. Clock Skew Details: Source Clock Path clk to DS18B20Z_uut/SLICE_1490: Name Fanout Delay (ns) Site Resource ROUTE 525 3.044 C1.PADDI to R13C24A.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_1447: Name Fanout Delay (ns) Site Resource ROUTE 525 3.044 C1.PADDI to R12C18A.CLK clk_c -------- 3.044 (0.0% logic, 100.0% route), 0 logic levels. Warning: 4.113MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "clk_c_generated_28" 399.840000 MHz ; 3 items scored, 1 timing error detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 0.601ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_s/i23400 (from clk_c_generated_28 +) Destination: FF Data in control_s/i23400 (to clk_c_generated_28 +) Delay: 2.369ns (40.0% logic, 60.0% route), 2 logic levels. Constraint Details: 2.369ns physical path delay control_s/SLICE_599 to control_s/SLICE_599 exceeds 2.501ns delay constraint less 0.000ns skew and 0.733ns LSRREC_SET requirement (totaling 1.768ns) by 0.601ns Physical Path Details: Data path control_s/SLICE_599 to control_s/SLICE_599: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R14C19A.CLK to R14C19A.Q0 control_s/SLICE_599 (from clk_c_generated_28) ROUTE 3 0.769 R14C19A.Q0 to R14C19C.C1 n35742 CTOF_DEL --- 0.495 R14C19C.C1 to R14C19C.F1 SLICE_1460 ROUTE 1 0.653 R14C19C.F1 to R14C19A.LSR control_s/temp_out_31__N_1907 (to clk_c_generated_28) -------- 2.369 (40.0% logic, 60.0% route), 2 logic levels. Clock Skew Details: Source Clock Path SLICE_1460 to control_s/SLICE_599: Name Fanout Delay (ns) Site Resource ROUTE 2 0.625 R14C19C.F0 to R14C19A.CLK clk_c_generated_28 -------- 0.625 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SLICE_1460 to control_s/SLICE_599: Name Fanout Delay (ns) Site Resource ROUTE 2 0.625 R14C19C.F0 to R14C19A.CLK clk_c_generated_28 -------- 0.625 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 1.160ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_s/tone_flag_378_rep_1018 (from clk_c +) Destination: FF Data in control_s/i23400 (to clk_c_generated_28 +) Delay: 3.169ns (29.9% logic, 70.1% route), 2 logic levels. Constraint Details: 3.169ns physical path delay SLICE_1555 to control_s/SLICE_599 meets 2.501ns delay constraint less -2.561ns skew and 0.733ns LSRREC_SET requirement (totaling 4.329ns) by 1.160ns Physical Path Details: Data path SLICE_1555 to control_s/SLICE_599: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R12C19D.CLK to R12C19D.Q0 SLICE_1555 (from clk_c) ROUTE 68 1.569 R12C19D.Q0 to R14C19C.D1 n75906 CTOF_DEL --- 0.495 R14C19C.D1 to R14C19C.F1 SLICE_1460 ROUTE 1 0.653 R14C19C.F1 to R14C19A.LSR control_s/temp_out_31__N_1907 (to clk_c_generated_28) -------- 3.169 (29.9% logic, 70.1% route), 2 logic levels. Clock Skew Details: Source Clock Path clk to SLICE_1555: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 525 3.044 C1.PADDI to R12C19D.CLK clk_c -------- 4.176 (27.1% logic, 72.9% route), 1 logic levels. Destination Clock Path clk to control_s/SLICE_599: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 525 3.044 C1.PADDI to R14C19B.CLK clk_c REG_DEL --- 0.452 R14C19B.CLK to R14C19B.Q0 control_s/SLICE_1301 ROUTE 3 0.989 R14C19B.Q0 to R14C19C.A0 n35743 CTOF_DEL --- 0.495 R14C19C.A0 to R14C19C.F0 SLICE_1460 ROUTE 2 0.625 R14C19C.F0 to R14C19A.CLK clk_c_generated_28 -------- 6.737 (30.9% logic, 69.1% route), 3 logic levels. Passed: The following path meets requirements by 1.740ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_s/temp_out_i0_23401_23402_set (from clk_c +) Destination: FF Data in control_s/i23400 (to clk_c_generated_28 +) Delay: 2.589ns (36.6% logic, 63.4% route), 2 logic levels. Constraint Details: 2.589ns physical path delay control_s/SLICE_1301 to control_s/SLICE_599 meets 2.501ns delay constraint less -2.561ns skew and 0.733ns LSRREC_SET requirement (totaling 4.329ns) by 1.740ns Physical Path Details: Data path control_s/SLICE_1301 to control_s/SLICE_599: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R14C19B.CLK to R14C19B.Q0 control_s/SLICE_1301 (from clk_c) ROUTE 3 0.989 R14C19B.Q0 to R14C19C.A1 n35743 CTOF_DEL --- 0.495 R14C19C.A1 to R14C19C.F1 SLICE_1460 ROUTE 1 0.653 R14C19C.F1 to R14C19A.LSR control_s/temp_out_31__N_1907 (to clk_c_generated_28) -------- 2.589 (36.6% logic, 63.4% route), 2 logic levels. Clock Skew Details: Source Clock Path clk to control_s/SLICE_1301: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 525 3.044 C1.PADDI to R14C19B.CLK clk_c -------- 4.176 (27.1% logic, 72.9% route), 1 logic levels. Destination Clock Path clk to control_s/SLICE_599: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 C1.PAD to C1.PADDI clk ROUTE 525 3.044 C1.PADDI to R14C19B.CLK clk_c REG_DEL --- 0.452 R14C19B.CLK to R14C19B.Q0 control_s/SLICE_1301 ROUTE 3 0.989 R14C19B.Q0 to R14C19C.A0 n35743 CTOF_DEL --- 0.495 R14C19C.A0 to R14C19C.F0 SLICE_1460 ROUTE 2 0.625 R14C19C.F0 to R14C19A.CLK clk_c_generated_28 -------- 6.737 (30.9% logic, 69.1% route), 3 logic levels. Warning: 322.373MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "clk_c" 22.277000 MHz ; | 22.277 MHz| 4.113 MHz| 5 * | | | FREQUENCY NET "clk_c_generated_28" | | | 399.840000 MHz ; | 399.840 MHz| 322.373 MHz| 2 * | | | ---------------------------------------------------------------------------- 2 preferences(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- bin_to_bcd_uut/n73924 | 3| 4094| 99.93% | | | bin_to_bcd_uut/n74060 | 6| 4094| 99.93% | | | bin_to_bcd_uut/n74055 | 3| 4094| 99.93% | | | bin_to_bcd_uut/bcd_code_24__N_425 | 11| 4094| 99.93% | | | bin_to_bcd_uut/n8391 | 6| 4094| 99.93% | | | bin_to_bcd_uut/n74030 | 6| 4094| 99.93% | | | bin_to_bcd_uut/n74017 | 4| 4094| 99.93% | | | bin_to_bcd_uut/n73911 | 3| 4094| 99.93% | | | bin_to_bcd_uut/n74007 | 3| 4094| 99.93% | | | bin_to_bcd_uut/n8370 | 4| 4094| 99.93% | | | bin_to_bcd_uut/n72938 | 2| 4094| 99.93% | | | n8366 | 8| 4094| 99.93% | | | bin_to_bcd_uut/n73949 | 5| 4092| 99.88% | | | bin_to_bcd_uut/n73939 | 3| 4092| 99.88% | | | bin_to_bcd_uut/bcd_code_24__N_527 | 5| 4092| 99.88% | | | bin_to_bcd_uut/bcd_code_24__N_572 | 11| 4092| 99.88% | | | n67502 | 1| 4090| 99.83% | | | bin_to_bcd_uut/bcd_code_24__N_623 | 9| 4084| 99.68% | | | bin_to_bcd_uut/n73890 | 5| 4063| 99.17% | | | bin_to_bcd_uut/n73898 | 3| 4063| 99.17% | | | n67501 | 1| 4058| 99.05% | | | bin_to_bcd_uut/bcd_code_24__N_674 | 9| 4056| 99.00% | | | bin_to_bcd_uut/n73884 | 2| 4017| 98.05% | | | bin_to_bcd_uut/n73872 | 2| 4017| 98.05% | | | bin_to_bcd_uut/n73996 | 5| 3807| 92.92% | | | bin_to_bcd_uut/n73989 | 3| 3757| 91.70% | | | bin_to_bcd_uut/n73981 | 4| 3757| 91.70% | | | bcd_code_13 | 3| 3481| 84.96% | | | n67500 | 1| 3334| 81.38% | | | n67400 | 1| 3331| 81.30% | | | n67512 | 1| 3178| 77.57% | | | temperature_code_5 | 2| 3172| 77.42% | | | bin_to_bcd_uut/n4 | 3| 3169| 77.35% | | | n67499 | 1| 3142| 76.69% | | | temperature_code_10_N_1_5 | 4| 3109| 75.88% | | | bin_to_bcd_uut/n8378 | 6| 3100| 75.67% | | | bin_to_bcd_uut/n35_adj_2946 | 1| 3076| 75.08% | | | n74081 | 9| 3076| 75.08% | | | n23 | 8| 3076| 75.08% | | | n67493 | 1| 2973| 72.57% | | | n12328 | 1| 2841| 69.34% | | | n67399 | 1| 2647| 64.61% | | | bin_code_18 | 11| 2557| 62.41% | | | bcd_code_24__N_367 | 3| 2290| 55.89% | | | bcd_code_24__N_344 | 9| 2268| 55.36% | | | data_out_1 | 5| 2080| 50.77% | | | n67494 | 1| 1984| 48.43% | | | bin_to_bcd_uut/bcd_code_24__N_362 | 10| 1848| 45.11% | | | bcd_code_24__N_340 | 5| 1826| 44.57% | | | bin_to_bcd_uut/n74094 | 4| 1814| 44.28% | | | control_s/tx_data_out_7_N_2736_1 | 1| 1384| 33.78% | | | n12271 | 1| 1369| 33.41% | | | control_s/n73056 | 1| 1307| 31.90% | | | bin_code_20 | 12| 1299| 31.71% | | | n67503 | 1| 1299| 31.71% | | | n67511 | 1| 1215| 29.66% | | | bin_to_bcd_uut/n74090 | 3| 1018| 24.85% | | | n12273 | 1| 1009| 24.63% | | | bin_to_bcd_uut/n74079 | 3| 994| 24.26% | | | bin_to_bcd_uut/bcd_code_24__N_402 | 5| 994| 24.26% | | | bin_to_bcd_uut/n74083 | 5| 989| 24.14% | | | n67401 | 1| 915| 22.33% | | | temperature_code_8 | 2| 915| 22.33% | | | temperature_code_10_N_1_8 | 4| 915| 22.33% | | | bin_to_bcd_uut/bcd_code_24__N_407 | 9| 908| 22.16% | | | n12272 | 1| 895| 21.85% | | | bin_to_bcd_uut/bcd_code_24__N_767 | 3| 848| 20.70% | | | bcd_code_24__N_371 | 7| 786| 19.18% | | | n67514 | 1| 724| 17.67% | | | data_out_5 | 5| 691| 16.87% | | | data_out_4 | 5| 622| 15.18% | | | n67513 | 1| 615| 15.01% | | | n12325 | 1| 551| 13.45% | | | control_s/tx_data_out_7_N_2736_2 | 1| 536| 13.08% | | | control_s/n73061 | 1| 536| 13.08% | | | bcd_code_14 | 3| 536| 13.08% | | | n67398 | 1| 452| 11.03% | | | data_out_0 | 5| 452| 11.03% | | | bin_to_bcd_uut/n74093 | 5| 432| 10.54% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 30 clocks: Clock Domain: control_s/clk_c_generated_9 Source: control_s/SLICE_1579.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_8 Source: SLICE_1577.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_6 Source: control_s/SLICE_1477.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_5 Source: control_s/SLICE_1472.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_4 Source: control_s/SLICE_1473.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_3 Source: control_s/SLICE_1474.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_27 Source: control_s/SLICE_1465.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_26 Source: control_s/SLICE_1466.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_25 Source: control_s/SLICE_1467.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_24 Source: control_s/SLICE_1590.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_23 Source: control_s/SLICE_1591.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_22 Source: control_s/SLICE_1603.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_21 Source: control_s/SLICE_1591.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_20 Source: control_s/SLICE_1476.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_2 Source: control_s/SLICE_1475.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_19 Source: control_s/SLICE_1468.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_18 Source: control_s/SLICE_1469.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_17 Source: control_s/SLICE_1590.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_16 Source: control_s/SLICE_1589.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_15 Source: control_s/SLICE_1587.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_14 Source: control_s/SLICE_1579.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_13 Source: control_s/SLICE_1470.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_12 Source: control_s/SLICE_1471.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_11 Source: control_s/SLICE_1462.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_10 Source: control_s/SLICE_1589.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_1 Source: control_s/SLICE_1464.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: clk_c_generated_7 Source: SLICE_1577.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: clk_c_generated_28 Source: SLICE_1460.F0 Loads: 2 Covered under: FREQUENCY NET "clk_c_generated_28" 399.840000 MHz ; Data transfers from: Clock Domain: clk_c Source: clk.PAD Covered under: FREQUENCY NET "clk_c_generated_28" 399.840000 MHz ; Transfers: 2 Clock Domain: clk_c Source: clk.PAD Loads: 525 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Data transfers from: Clock Domain: control_s/clk_c_generated_9 Source: control_s/SLICE_1579.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_8 Source: SLICE_1577.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_6 Source: control_s/SLICE_1477.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_5 Source: control_s/SLICE_1472.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_4 Source: control_s/SLICE_1473.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_3 Source: control_s/SLICE_1474.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_27 Source: control_s/SLICE_1465.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_26 Source: control_s/SLICE_1466.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_25 Source: control_s/SLICE_1467.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_24 Source: control_s/SLICE_1590.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_23 Source: control_s/SLICE_1591.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_22 Source: control_s/SLICE_1603.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_21 Source: control_s/SLICE_1591.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_20 Source: control_s/SLICE_1476.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_2 Source: control_s/SLICE_1475.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_19 Source: control_s/SLICE_1468.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_18 Source: control_s/SLICE_1469.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_17 Source: control_s/SLICE_1590.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_16 Source: control_s/SLICE_1589.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_15 Source: control_s/SLICE_1587.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_14 Source: control_s/SLICE_1579.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_13 Source: control_s/SLICE_1470.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_12 Source: control_s/SLICE_1471.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_11 Source: control_s/SLICE_1462.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_10 Source: control_s/SLICE_1589.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_1 Source: control_s/SLICE_1464.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: clk_c_generated_7 Source: SLICE_1577.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: clk_c_generated_28 Source: SLICE_1460.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: DS18B20Z_uut/clk_1mhz Source: DS18B20Z_uut/SLICE_223.Q0 Loads: 20 No transfer within this clock domain is found Timing summary (Setup): --------------- Timing errors: 4097 Score: 137943026 Cumulative negative slack: 137943026 Constraints cover 2147483647 paths, 2 nets, and 12423 connections (98.08% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 Sun Feb 28 14:14:45 2021 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o step_impl1.twr -gui -msgset C:/Users/lzsh/Desktop/step/promote.xml step_impl1.ncd step_impl1.prf Design file: step_impl1.ncd Preference file: step_impl1.prf Device,speed: LCMXO2-4000HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "clk_c" 22.277000 MHz (0 errors)
  • 4096 items scored, 0 timing errors detected.
  • FREQUENCY NET "clk_c_generated_28" 399.840000 MHz (2 errors)
  • 3 items scored, 2 timing errors detected. 28 potential circuit loops found in timing analysis. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "clk_c" 22.277000 MHz ; 4096 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q u1/Uart_Rx_uut/uart_rx0_46 (from clk_c +) Destination: FF Data in u1/Uart_Rx_uut/uart_rx1_47 (to clk_c +) Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: 0.285ns physical path delay SLICE_644 to SLICE_644 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path SLICE_644 to SLICE_644: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R16C16B.CLK to R16C16B.Q0 SLICE_644 (from clk_c) ROUTE 1 0.152 R16C16B.Q0 to R16C16B.M1 u1/Uart_Rx_uut/uart_rx0 (to clk_c) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to SLICE_644: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R16C16B.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_644: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R16C16B.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_s/tx_data_out__i5 (from clk_c +) Destination: FF Data in u1/Uart_Tx_uut/tx_data_r__i5 (to clk_c +) Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: 0.285ns physical path delay control_s/SLICE_630 to SLICE_650 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path control_s/SLICE_630 to SLICE_650: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R16C17C.CLK to R16C17C.Q0 control_s/SLICE_630 (from clk_c) ROUTE 1 0.152 R16C17C.Q0 to R16C17D.M0 tx_data_4 (to clk_c) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to control_s/SLICE_630: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R16C17C.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_650: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R16C17D.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_s/tx_data_out__i6 (from clk_c +) Destination: FF Data in u1/Uart_Tx_uut/tx_data_r__i6 (to clk_c +) Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: 0.285ns physical path delay control_s/SLICE_630 to SLICE_650 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path control_s/SLICE_630 to SLICE_650: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R16C17C.CLK to R16C17C.Q1 control_s/SLICE_630 (from clk_c) ROUTE 1 0.152 R16C17C.Q1 to R16C17D.M1 tx_data_5 (to clk_c) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to control_s/SLICE_630: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R16C17C.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_650: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R16C17D.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DS18B20Z_uut/temperature_buffer_i0_i1 (from clk_c +) Destination: FF Data in DS18B20Z_uut/temperature_i0_i1 (to clk_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_16 to SLICE_19 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_16 to SLICE_19: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C21B.CLK to R10C21B.Q0 SLICE_16 (from clk_c) ROUTE 2 0.154 R10C21B.Q0 to R10C21A.M1 DS18B20Z_uut/temperature_buffer_1 (to clk_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R10C21B.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_19: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R10C21A.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q key_s/key_rst_i2 (from clk_c +) Destination: FF Data in key_s/key_rst_pre_i2 (to clk_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_4 to SLICE_10 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_4 to SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R14C22C.CLK to R14C22C.Q0 SLICE_4 (from clk_c) ROUTE 2 0.154 R14C22C.Q0 to R14C22D.M1 key_s/key_rst_2 (to clk_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R14C22C.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R14C22D.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q u1/Uart_Rx_uut/uart_rx1_47 (from clk_c +) Destination: FF Data in u1/Uart_Rx_uut/rx_data_i0_i7 (to clk_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_644 to SLICE_643 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_644 to SLICE_643: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R16C16B.CLK to R16C16B.Q1 SLICE_644 (from clk_c) ROUTE 10 0.154 R16C16B.Q1 to R16C16A.M0 u1/Uart_Rx_uut/uart_rx1 (to clk_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to SLICE_644: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R16C16B.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_643: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R16C16A.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q key_s/key_rst_i1 (from clk_c +) Destination: FF Data in key_s/key_rst_pre_i1 (to clk_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_8 to SLICE_10 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_8 to SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R14C22B.CLK to R14C22B.Q1 SLICE_8 (from clk_c) ROUTE 2 0.154 R14C22B.Q1 to R14C22D.M0 key_s/key_rst_1 (to clk_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to SLICE_8: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R14C22B.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R14C22D.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q key_s/key_rst_i0 (from clk_c +) Destination: FF Data in key_s/key_rst_pre_i0 (to clk_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_8 to SLICE_4 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_8 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R14C22B.CLK to R14C22B.Q0 SLICE_8 (from clk_c) ROUTE 2 0.154 R14C22B.Q0 to R14C22C.M1 key_s/key_rst_0 (to clk_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to SLICE_8: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R14C22B.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R14C22C.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_s/cnt_rxn_FSM_i0_i8 (from clk_c +) Destination: FF Data in control_s/cnt_rxn_FSM_i0_i9 (to clk_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay control_s/SLICE_1544 to control_s/SLICE_1544 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path control_s/SLICE_1544 to control_s/SLICE_1544: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R15C8C.CLK to R15C8C.Q0 control_s/SLICE_1544 (from clk_c) ROUTE 12 0.154 R15C8C.Q0 to R15C8C.M1 control_s/n1110 (to clk_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to control_s/SLICE_1544: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R15C8C.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to control_s/SLICE_1544: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R15C8C.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_s/cnt_rxn_FSM_i0_i6 (from clk_c +) Destination: FF Data in control_s/cnt_rxn_FSM_i0_i7 (to clk_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay control_s/SLICE_1086 to control_s/SLICE_1086 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path control_s/SLICE_1086 to control_s/SLICE_1086: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R15C7C.CLK to R15C7C.Q0 control_s/SLICE_1086 (from clk_c) ROUTE 13 0.154 R15C7C.Q0 to R15C7C.M1 control_s/n1112 (to clk_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path clk to control_s/SLICE_1086: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R15C7C.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk to control_s/SLICE_1086: Name Fanout Delay (ns) Site Resource ROUTE 525 1.116 C1.PADDI to R15C7C.CLK clk_c -------- 1.116 (0.0% logic, 100.0% route), 0 logic levels. ================================================================================ Preference: FREQUENCY NET "clk_c_generated_28" 399.840000 MHz ; 3 items scored, 2 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 0.494ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_s/temp_out_i0_23401_23402_set (from clk_c +) Destination: FF Data in control_s/i23400 (to clk_c_generated_28 +) Delay: 0.594ns (39.4% logic, 60.6% route), 2 logic levels. Constraint Details: 0.594ns physical path delay control_s/SLICE_1301 to control_s/SLICE_599 exceeds 0.000ns LSRREC_HLD and 0.000ns delay constraint less -1.088ns skew requirement (totaling 1.088ns) by 0.494ns Physical Path Details: Data path control_s/SLICE_1301 to control_s/SLICE_599: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R14C19B.CLK to R14C19B.Q0 control_s/SLICE_1301 (from clk_c) ROUTE 3 0.217 R14C19B.Q0 to R14C19C.A1 n35743 CTOF_DEL --- 0.101 R14C19C.A1 to R14C19C.F1 SLICE_1460 ROUTE 1 0.143 R14C19C.F1 to R14C19A.LSR control_s/temp_out_31__N_1907 (to clk_c_generated_28) -------- 0.594 (39.4% logic, 60.6% route), 2 logic levels. Clock Skew Details: Source Clock Path clk to control_s/SLICE_1301: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.449 C1.PAD to C1.PADDI clk ROUTE 525 1.116 C1.PADDI to R14C19B.CLK clk_c -------- 1.565 (28.7% logic, 71.3% route), 1 logic levels. Destination Clock Path clk to control_s/SLICE_599: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.449 C1.PAD to C1.PADDI clk ROUTE 525 1.116 C1.PADDI to R12C19D.CLK clk_c REG_DEL --- 0.154 R12C19D.CLK to R12C19D.Q0 SLICE_1555 ROUTE 68 0.555 R12C19D.Q0 to R14C19C.D0 n75906 CTOF_DEL --- 0.177 R14C19C.D0 to R14C19C.F0 SLICE_1460 ROUTE 2 0.202 R14C19C.F0 to R14C19A.CLK clk_c_generated_28 -------- 2.653 (29.4% logic, 70.6% route), 3 logic levels. Error: The following path exceeds requirements by 0.340ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_s/tone_flag_378_rep_1018 (from clk_c +) Destination: FF Data in control_s/i23400 (to clk_c_generated_28 +) Delay: 0.748ns (31.3% logic, 68.7% route), 2 logic levels. Constraint Details: 0.748ns physical path delay SLICE_1555 to control_s/SLICE_599 exceeds 0.000ns LSRREC_HLD and 0.000ns delay constraint less -1.088ns skew requirement (totaling 1.088ns) by 0.340ns Physical Path Details: Data path SLICE_1555 to control_s/SLICE_599: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R12C19D.CLK to R12C19D.Q0 SLICE_1555 (from clk_c) ROUTE 68 0.371 R12C19D.Q0 to R14C19C.D1 n75906 CTOF_DEL --- 0.101 R14C19C.D1 to R14C19C.F1 SLICE_1460 ROUTE 1 0.143 R14C19C.F1 to R14C19A.LSR control_s/temp_out_31__N_1907 (to clk_c_generated_28) -------- 0.748 (31.3% logic, 68.7% route), 2 logic levels. Clock Skew Details: Source Clock Path clk to SLICE_1555: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.449 C1.PAD to C1.PADDI clk ROUTE 525 1.116 C1.PADDI to R12C19D.CLK clk_c -------- 1.565 (28.7% logic, 71.3% route), 1 logic levels. Destination Clock Path clk to control_s/SLICE_599: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.449 C1.PAD to C1.PADDI clk ROUTE 525 1.116 C1.PADDI to R12C19D.CLK clk_c REG_DEL --- 0.154 R12C19D.CLK to R12C19D.Q0 SLICE_1555 ROUTE 68 0.555 R12C19D.Q0 to R14C19C.D0 n75906 CTOF_DEL --- 0.177 R14C19C.D0 to R14C19C.F0 SLICE_1460 ROUTE 2 0.202 R14C19C.F0 to R14C19A.CLK clk_c_generated_28 -------- 2.653 (29.4% logic, 70.6% route), 3 logic levels. Passed: The following path meets requirements by 0.520ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q control_s/i23400 (from clk_c_generated_28 +) Destination: FF Data in control_s/i23400 (to clk_c_generated_28 +) Delay: 0.520ns (45.0% logic, 55.0% route), 2 logic levels. Constraint Details: 0.520ns physical path delay control_s/SLICE_599 to control_s/SLICE_599 meets 0.000ns LSRREC_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.000ns) by 0.520ns Physical Path Details: Data path control_s/SLICE_599 to control_s/SLICE_599: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R14C19A.CLK to R14C19A.Q0 control_s/SLICE_599 (from clk_c_generated_28) ROUTE 3 0.143 R14C19A.Q0 to R14C19C.C1 n35742 CTOF_DEL --- 0.101 R14C19C.C1 to R14C19C.F1 SLICE_1460 ROUTE 1 0.143 R14C19C.F1 to R14C19A.LSR control_s/temp_out_31__N_1907 (to clk_c_generated_28) -------- 0.520 (45.0% logic, 55.0% route), 2 logic levels. Clock Skew Details: Source Clock Path SLICE_1460 to control_s/SLICE_599: Name Fanout Delay (ns) Site Resource ROUTE 2 0.202 R14C19C.F0 to R14C19A.CLK clk_c_generated_28 -------- 0.202 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SLICE_1460 to control_s/SLICE_599: Name Fanout Delay (ns) Site Resource ROUTE 2 0.202 R14C19C.F0 to R14C19A.CLK clk_c_generated_28 -------- 0.202 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "clk_c" 22.277000 MHz ; | 0.000 ns| 0.304 ns| 1 | | | FREQUENCY NET "clk_c_generated_28" | | | 399.840000 MHz ; | 0.000 ns| -0.494 ns| 2 * | | | ---------------------------------------------------------------------------- 1 preference(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- control_s/temp_out_31__N_1907 | 1| 2| 100.00% | | | n75906 | 68| 1| 50.00% | | | n35743 | 3| 1| 50.00% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 30 clocks: Clock Domain: control_s/clk_c_generated_9 Source: control_s/SLICE_1579.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_8 Source: SLICE_1577.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_6 Source: control_s/SLICE_1477.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_5 Source: control_s/SLICE_1472.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_4 Source: control_s/SLICE_1473.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_3 Source: control_s/SLICE_1474.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_27 Source: control_s/SLICE_1465.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_26 Source: control_s/SLICE_1466.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_25 Source: control_s/SLICE_1467.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_24 Source: control_s/SLICE_1590.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_23 Source: control_s/SLICE_1591.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_22 Source: control_s/SLICE_1603.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_21 Source: control_s/SLICE_1591.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_20 Source: control_s/SLICE_1476.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_2 Source: control_s/SLICE_1475.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_19 Source: control_s/SLICE_1468.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_18 Source: control_s/SLICE_1469.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_17 Source: control_s/SLICE_1590.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_16 Source: control_s/SLICE_1589.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_15 Source: control_s/SLICE_1587.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_14 Source: control_s/SLICE_1579.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_13 Source: control_s/SLICE_1470.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_12 Source: control_s/SLICE_1471.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_11 Source: control_s/SLICE_1462.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_10 Source: control_s/SLICE_1589.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: control_s/clk_c_generated_1 Source: control_s/SLICE_1464.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: clk_c_generated_7 Source: SLICE_1577.F0 Loads: 2 No transfer within this clock domain is found Clock Domain: clk_c_generated_28 Source: SLICE_1460.F0 Loads: 2 Covered under: FREQUENCY NET "clk_c_generated_28" 399.840000 MHz ; Data transfers from: Clock Domain: clk_c Source: clk.PAD Covered under: FREQUENCY NET "clk_c_generated_28" 399.840000 MHz ; Transfers: 2 Clock Domain: clk_c Source: clk.PAD Loads: 525 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Data transfers from: Clock Domain: control_s/clk_c_generated_9 Source: control_s/SLICE_1579.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_8 Source: SLICE_1577.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_6 Source: control_s/SLICE_1477.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_5 Source: control_s/SLICE_1472.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_4 Source: control_s/SLICE_1473.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_3 Source: control_s/SLICE_1474.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_27 Source: control_s/SLICE_1465.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_26 Source: control_s/SLICE_1466.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_25 Source: control_s/SLICE_1467.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_24 Source: control_s/SLICE_1590.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_23 Source: control_s/SLICE_1591.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_22 Source: control_s/SLICE_1603.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_21 Source: control_s/SLICE_1591.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_20 Source: control_s/SLICE_1476.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_2 Source: control_s/SLICE_1475.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_19 Source: control_s/SLICE_1468.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_18 Source: control_s/SLICE_1469.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_17 Source: control_s/SLICE_1590.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_16 Source: control_s/SLICE_1589.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_15 Source: control_s/SLICE_1587.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_14 Source: control_s/SLICE_1579.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_13 Source: control_s/SLICE_1470.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_12 Source: control_s/SLICE_1471.F1 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_11 Source: control_s/SLICE_1462.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_10 Source: control_s/SLICE_1589.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: control_s/clk_c_generated_1 Source: control_s/SLICE_1464.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: clk_c_generated_7 Source: SLICE_1577.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: clk_c_generated_28 Source: SLICE_1460.F0 Covered under: FREQUENCY NET "clk_c" 22.277000 MHz ; Transfers: 1 Clock Domain: DS18B20Z_uut/clk_1mhz Source: DS18B20Z_uut/SLICE_223.Q0 Loads: 20 No transfer within this clock domain is found Timing summary (Hold): --------------- Timing errors: 2 Score: 834 Cumulative negative slack: 834 Constraints cover 2147483647 paths, 2 nets, and 12423 connections (98.08% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 4097 (setup), 2 (hold) Score: 137943026 (setup), 834 (hold) Cumulative negative slack: 137943860 (137943026+834) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------