Setting log file to 'C:/Users/17152/Desktop/lf_project - 1.0/impl1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file D:/diamond/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
(VERI-1482) Analyzing Verilog file C:/Users/17152/Desktop/lf_project - 1.0/lf_project.v
(VERI-1482) Analyzing Verilog file C:/Users/17152/Desktop/lf_project - 1.0/oled.v
(VERI-1482) Analyzing Verilog file C:/Users/17152/Desktop/lf_project - 1.0/ds18b20.v
(VERI-1482) Analyzing Verilog file C:/Users/17152/Desktop/lf_project - 1.0/bin_to_bcd.v
(VERI-1482) Analyzing Verilog file C:/Users/17152/Desktop/lf_project - 1.0/led.v
(VERI-1482) Analyzing Verilog file C:/Users/17152/Desktop/lf_project - 1.0/Baud9600.v
(VERI-1482) Analyzing Verilog file C:/Users/17152/Desktop/lf_project - 1.0/clock.v
(VERI-1482) Analyzing Verilog file C:/Users/17152/Desktop/lf_project - 1.0/clk_1ms.v
(VERI-1482) Analyzing Verilog file C:/Users/17152/Desktop/lf_project - 1.0/uart_rx.v
(VERI-1482) Analyzing Verilog file C:/Users/17152/Desktop/lf_project - 1.0/uart_tx.v
(VERI-1482) Analyzing Verilog file C:/Users/17152/Desktop/lf_project - 1.0/buzz.v
INFO - C:/Users/17152/Desktop/lf_project - 1.0/lf_project.v(1,8-1,18) (VERI-1018) compiling module lf_project
INFO - C:/Users/17152/Desktop/lf_project - 1.0/lf_project.v(1,1-169,10) (VERI-9000) elaborating module 'lf_project'
INFO - C:/Users/17152/Desktop/lf_project - 1.0/ds18b20.v(2,1-250,10) (VERI-9000) elaborating module 'DS18B20Z_uniq_1'
INFO - C:/Users/17152/Desktop/lf_project - 1.0/bin_to_bcd.v(2,1-31,10) (VERI-9000) elaborating module 'bin_to_bcd_uniq_1'
INFO - C:/Users/17152/Desktop/lf_project - 1.0/bin_to_bcd.v(2,1-31,10) (VERI-9000) elaborating module 'bin_to_bcd_uniq_2'
INFO - C:/Users/17152/Desktop/lf_project - 1.0/bin_to_bcd.v(2,1-31,10) (VERI-9000) elaborating module 'bin_to_bcd_uniq_3'
INFO - C:/Users/17152/Desktop/lf_project - 1.0/oled.v(2,1-310,10) (VERI-9000) elaborating module 'OLED12832_uniq_1'
INFO - C:/Users/17152/Desktop/lf_project - 1.0/buzz.v(2,1-141,10) (VERI-9000) elaborating module 'buzzer_uniq_1'
INFO - C:/Users/17152/Desktop/lf_project - 1.0/Baud9600.v(1,1-23,10) (VERI-9000) elaborating module 'clk_uart_uniq_1'
INFO - C:/Users/17152/Desktop/lf_project - 1.0/uart_tx.v(2,1-78,10) (VERI-9000) elaborating module 'uart_tx_uniq_1'
INFO - C:/Users/17152/Desktop/lf_project - 1.0/uart_rx.v(3,1-105,10) (VERI-9000) elaborating module 'uart_rx_uniq_1'
INFO - C:/Users/17152/Desktop/lf_project - 1.0/clk_1ms.v(1,1-25,10) (VERI-9000) elaborating module 'clk_1ms_uniq_1'
INFO - C:/Users/17152/Desktop/lf_project - 1.0/clock.v(2,1-105,10) (VERI-9000) elaborating module 'clock_uniq_1'
INFO - C:/Users/17152/Desktop/lf_project - 1.0/led.v(1,1-25,10) (VERI-9000) elaborating module 'signal_led_uniq_1'
Done: design load finished with (0) errors, and (0) warnings