Map TRACE Report
Loading design for application trce from file lf_project_impl1_map.ncd.
Design name: lf_project
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-4000HC
Package: CSBGA132
Performance: 4
Loading device for application trce from file 'xo2c4000.nph' in environment: D:/diamond/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.11.0.396.4
Tue Feb 23 11:26:23 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o lf_project_impl1.tw1 -gui -msgset C:/Users/17152/Desktop/lf_project - 1.0/promote.xml lf_project_impl1_map.ncd lf_project_impl1.prf
Design file: lf_project_impl1_map.ncd
Preference file: lf_project_impl1.prf
Device,speed: LCMXO2-4000HC,4
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY 8.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
Report: 12.736MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
================================================================================
Preference: FREQUENCY 8.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 46.481ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q DS18B20Z_lf/data_out_i0_i11 (from clk_c +)
Destination: FF Data in OLED12832_lf/char_i34 (to clk_c +)
Delay: 78.353ns (33.2% logic, 66.8% route), 52 logic levels.
Constraint Details:
78.353ns physical path delay SLICE_985 to OLED12832_lf/SLICE_297 meets
125.000ns delay constraint less
0.166ns DIN_SET requirement (totaling 124.834ns) by 46.481ns
Physical Path Details:
Data path SLICE_985 to OLED12832_lf/SLICE_297:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 SLICE_985.CLK to SLICE_985.Q1 SLICE_985 (from clk_c)
ROUTE 1 e 1.234 SLICE_985.Q1 to SLICE_1684.C0 data_out_11
CTOF_DEL --- 0.495 SLICE_1684.C0 to SLICE_1684.F0 SLICE_1684
ROUTE 8 e 1.234 SLICE_1684.F0 to SLICE_1650.C1 n8_adj_3562
CTOF_DEL --- 0.495 SLICE_1650.C1 to SLICE_1650.F1 SLICE_1650
ROUTE 38 e 1.234 SLICE_1650.F1 to SLICE_2321.C1 n88625
CTOF_DEL --- 0.495 SLICE_2321.C1 to SLICE_2321.F1 SLICE_2321
ROUTE 2 e 1.234 SLICE_2321.F1 to SLICE_15.A1 temperature_code_4
C1TOFCO_DE --- 0.889 SLICE_15.A1 to SLICE_15.FCO SLICE_15
ROUTE 1 e 0.001 SLICE_15.FCO to SLICE_14.FCI n80348
FCITOFCO_D --- 0.162 SLICE_14.FCI to SLICE_14.FCO SLICE_14
ROUTE 1 e 0.001 SLICE_14.FCO to SLICE_13.FCI n80349
FCITOFCO_D --- 0.162 SLICE_13.FCI to SLICE_13.FCO SLICE_13
ROUTE 1 e 0.001 SLICE_13.FCO to SLICE_11.FCI n80350
FCITOF1_DE --- 0.643 SLICE_11.FCI to SLICE_11.F1 SLICE_11
ROUTE 1 e 1.234 SLICE_11.F1 to SLICE_4.A0 n23038
C0TOFCO_DE --- 1.023 SLICE_4.A0 to SLICE_4.FCO SLICE_4
ROUTE 1 e 0.001 SLICE_4.FCO to SLICE_3.FCI n80357
FCITOF0_DE --- 0.585 SLICE_3.FCI to SLICE_3.F0 SLICE_3
ROUTE 1 e 1.234 SLICE_3.F0 to SLICE_20.A0 n23132
C0TOFCO_DE --- 1.023 SLICE_20.A0 to SLICE_20.FCO SLICE_20
ROUTE 1 e 0.001 SLICE_20.FCO to SLICE_19.FCI n80344
FCITOFCO_D --- 0.162 SLICE_19.FCI to SLICE_19.FCO SLICE_19
ROUTE 1 e 0.001 SLICE_19.FCO to SLICE_18.FCI n80345
FCITOFCO_D --- 0.162 SLICE_18.FCI to SLICE_18.FCO SLICE_18
ROUTE 1 e 0.001 SLICE_18.FCO to SLICE_17.FCI n80346
FCITOFCO_D --- 0.162 SLICE_17.FCI to SLICE_17.FCO SLICE_17
ROUTE 1 e 0.001 SLICE_17.FCO to SLICE_16.FCI n80347
FCITOF0_DE --- 0.585 SLICE_16.FCI to SLICE_16.F0 SLICE_16
ROUTE 11 e 1.234 SLICE_16.F0 to *SLICE_2111.D1 bin_code_20
CTOF_DEL --- 0.495 *SLICE_2111.D1 to *SLICE_2111.F1 bin_to_bcd_lf/SLICE_2111
ROUTE 3 e 1.234 *SLICE_2111.F1 to *SLICE_1431.A1 bin_to_bcd_lf/n88491
CTOF_DEL --- 0.495 *SLICE_1431.A1 to *SLICE_1431.F1 bin_to_bcd_lf/SLICE_1431
ROUTE 5 e 1.234 *SLICE_1431.F1 to *SLICE_1606.C1 bin_to_bcd_lf/n90728
CTOF_DEL --- 0.495 *SLICE_1606.C1 to *SLICE_1606.F1 bin_to_bcd_lf/SLICE_1606
ROUTE 4 e 1.234 *SLICE_1606.F1 to *SLICE_2016.B1 bin_to_bcd_lf/n88475
CTOF_DEL --- 0.495 *SLICE_2016.B1 to *SLICE_2016.F1 bin_to_bcd_lf/SLICE_2016
ROUTE 8 e 1.234 *SLICE_2016.F1 to *SLICE_2086.D1 n88448
CTOF_DEL --- 0.495 *SLICE_2086.D1 to *SLICE_2086.F1 bin_to_bcd_lf/SLICE_2086
ROUTE 1 e 1.234 *SLICE_2086.F1 to *SLICE_1626.B1 bin_to_bcd_lf/n35
CTOF_DEL --- 0.495 *SLICE_1626.B1 to *SLICE_1626.F1 bin_to_bcd_lf/SLICE_1626
ROUTE 7 e 1.234 *SLICE_1626.F1 to *SLICE_2045.D0 n23
CTOF_DEL --- 0.495 *SLICE_2045.D0 to *SLICE_2045.F0 bin_to_bcd_lf/SLICE_2045
ROUTE 2 e 1.234 *SLICE_2045.F0 to *SLICE_1432.A0 bin_to_bcd_lf/n88409
CTOF_DEL --- 0.495 *SLICE_1432.A0 to *SLICE_1432.F0 bin_to_bcd_lf/SLICE_1432
ROUTE 6 e 1.234 *SLICE_1432.F0 to *SLICE_2009.C0 bin_to_bcd_lf/n13515
CTOF_DEL --- 0.495 *SLICE_2009.C0 to *SLICE_2009.F0 bin_to_bcd_lf/SLICE_2009
ROUTE 4 e 1.234 *SLICE_2009.F0 to *SLICE_2097.B1 bin_to_bcd_lf/n88380
CTOF_DEL --- 0.495 *SLICE_2097.B1 to *SLICE_2097.F1 bin_to_bcd_lf/SLICE_2097
ROUTE 3 e 1.234 *SLICE_2097.F1 to *SLICE_2002.D1 bin_to_bcd_lf/n88358
CTOF_DEL --- 0.495 *SLICE_2002.D1 to *SLICE_2002.F1 bin_to_bcd_lf/SLICE_2002
ROUTE 9 e 1.234 *SLICE_2002.F1 to *SLICE_2084.C1 bin_to_bcd_lf/bcd_code_24__N_436
CTOF_DEL --- 0.495 *SLICE_2084.C1 to *SLICE_2084.F1 bin_to_bcd_lf/SLICE_2084
ROUTE 3 e 1.234 *SLICE_2084.F1 to *SLICE_2003.D1 bin_to_bcd_lf/n88320
CTOF_DEL --- 0.495 *SLICE_2003.D1 to *SLICE_2003.F1 bin_to_bcd_lf/SLICE_2003
ROUTE 10 e 1.234 *SLICE_2003.F1 to *SLICE_1601.C0 bin_to_bcd_lf/bcd_code_24__N_474
CTOF_DEL --- 0.495 *SLICE_1601.C0 to *SLICE_1601.F0 bin_to_bcd_lf/SLICE_1601
ROUTE 3 e 1.234 *SLICE_1601.F0 to *SLICE_2084.D0 bin_to_bcd_lf/n88281
CTOF_DEL --- 0.495 *SLICE_2084.D0 to *SLICE_2084.F0 bin_to_bcd_lf/SLICE_2084
ROUTE 10 e 1.234 *SLICE_2084.F0 to *SLICE_2091.C0 bin_to_bcd_lf/bcd_code_24__N_510
CTOF_DEL --- 0.495 *SLICE_2091.C0 to *SLICE_2091.F0 bin_to_bcd_lf/SLICE_2091
ROUTE 3 e 1.234 *SLICE_2091.F0 to *SLICE_2074.D1 bin_to_bcd_lf/n88235
CTOF_DEL --- 0.495 *SLICE_2074.D1 to *SLICE_2074.F1 bin_to_bcd_lf/SLICE_2074
ROUTE 8 e 1.234 *SLICE_2074.F1 to *SLICE_2058.C1 bin_to_bcd_lf/bcd_code_24__N_552
CTOF_DEL --- 0.495 *SLICE_2058.C1 to *SLICE_2058.F1 bin_to_bcd_lf/SLICE_2058
ROUTE 4 e 1.234 *SLICE_2058.F1 to *SLICE_2057.C1 bin_to_bcd_lf/bcd_code_24__N_547
CTOF_DEL --- 0.495 *SLICE_2057.C1 to *SLICE_2057.F1 bin_to_bcd_lf/SLICE_2057
ROUTE 5 e 1.234 *SLICE_2057.F1 to *SLICE_1628.D0 bin_to_bcd_lf/n88136
CTOF_DEL --- 0.495 *SLICE_1628.D0 to *SLICE_1628.F0 bin_to_bcd_lf/SLICE_1628
ROUTE 2 e 1.234 *SLICE_1628.F0 to *SLICE_2069.D0 bin_to_bcd_lf/n88122
CTOF_DEL --- 0.495 *SLICE_2069.D0 to *SLICE_2069.F0 bin_to_bcd_lf/SLICE_2069
ROUTE 10 e 1.234 *SLICE_2069.F0 to *SLICE_1621.C0 bin_to_bcd_lf/bcd_code_24__N_592
CTOF_DEL --- 0.495 *SLICE_1621.C0 to *SLICE_1621.F0 bin_to_bcd_lf/SLICE_1621
ROUTE 2 e 1.234 *SLICE_1621.F0 to *SLICE_2044.D0 bin_to_bcd_lf/n88078
CTOF_DEL --- 0.495 *SLICE_2044.D0 to *SLICE_2044.F0 bin_to_bcd_lf/SLICE_2044
ROUTE 10 e 1.234 *SLICE_2044.F0 to *SLICE_2031.C1 bin_to_bcd_lf/bcd_code_24__N_643
CTOF_DEL --- 0.495 *SLICE_2031.C1 to *SLICE_2031.F1 bin_to_bcd_lf/SLICE_2031
ROUTE 2 e 1.234 *SLICE_2031.F1 to *SLICE_2043.D1 bin_to_bcd_lf/n88027
CTOF_DEL --- 0.495 *SLICE_2043.D1 to *SLICE_2043.F1 bin_to_bcd_lf/SLICE_2043
ROUTE 4 e 1.234 *SLICE_2043.F1 to *SLICE_2037.D1 bin_to_bcd_lf/n88014
CTOF_DEL --- 0.495 *SLICE_2037.D1 to *SLICE_2037.F1 bin_to_bcd_lf/SLICE_2037
ROUTE 5 e 1.234 *SLICE_2037.F1 to *SLICE_2053.C0 bin_to_bcd_lf/bcd_code_24__N_689
CTOF_DEL --- 0.495 *SLICE_2053.C0 to *SLICE_2053.F0 bin_to_bcd_lf/SLICE_2053
ROUTE 4 e 1.234 *SLICE_2053.F0 to *SLICE_2034.D0 bin_to_bcd_lf/n87968
CTOF_DEL --- 0.495 *SLICE_2034.D0 to *SLICE_2034.F0 bin_to_bcd_lf/SLICE_2034
ROUTE 4 e 1.234 *SLICE_2034.F0 to *SLICE_2029.C1 bin_to_bcd_lf/bcd_code_24__N_680
CTOF_DEL --- 0.495 *SLICE_2029.C1 to *SLICE_2029.F1 bin_to_bcd_lf/SLICE_2029
ROUTE 6 e 1.234 *SLICE_2029.F1 to SLICE_979.D1 bin_to_bcd_lf/n87943
CTOF_DEL --- 0.495 SLICE_979.D1 to SLICE_979.F1 SLICE_979
ROUTE 2 e 1.234 SLICE_979.F1 to *SLICE_2034.D1 bin_to_bcd_lf/n87936
CTOF_DEL --- 0.495 *SLICE_2034.D1 to *SLICE_2034.F1 bin_to_bcd_lf/SLICE_2034
ROUTE 7 e 1.234 *SLICE_2034.F1 to *SLICE_2093.C1 bin_to_bcd_lf/bcd_code_24__N_727
CTOF_DEL --- 0.495 *SLICE_2093.C1 to *SLICE_2093.F1 bin_to_bcd_lf/SLICE_2093
ROUTE 5 e 1.234 *SLICE_2093.F1 to *SLICE_2071.B1 n87921
CTOF_DEL --- 0.495 *SLICE_2071.B1 to *SLICE_2071.F1 bin_to_bcd_lf/SLICE_2071
ROUTE 1 e 1.234 *SLICE_2071.F1 to *SLICE_1198.D1 n87911
CTOOFX_DEL --- 0.721 *SLICE_1198.D1 to *ICE_1198.OFX0 OLED12832_lf/i37_adj_417/SLICE_1198
ROUTE 1 e 1.234 *ICE_1198.OFX0 to SLICE_1527.A1 OLED12832_lf/n17_adj_3353
CTOF_DEL --- 0.495 SLICE_1527.A1 to SLICE_1527.F1 SLICE_1527
ROUTE 1 e 0.480 SLICE_1527.F1 to SLICE_1527.B0 OLED12832_lf/char_167_N_1296_34
CTOF_DEL --- 0.495 SLICE_1527.B0 to SLICE_1527.F0 SLICE_1527
ROUTE 1 e 1.234 SLICE_1527.F0 to */SLICE_297.C1 OLED12832_lf/n16_adj_3352
CTOF_DEL --- 0.495 */SLICE_297.C1 to */SLICE_297.F1 OLED12832_lf/SLICE_297
ROUTE 1 e 0.001 */SLICE_297.F1 to *SLICE_297.DI1 OLED12832_lf/char_167_N_915_34 (to clk_c)
--------
78.353 (33.2% logic, 66.8% route), 52 logic levels.
Report: 12.736MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY 8.000000 MHz ; | 8.000 MHz| 12.736 MHz| 52
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 6 clocks:
Clock Domain: uart_en Source: clock_lf/SLICE_1020.Q0 Loads: 13
Covered under: FREQUENCY 8.000000 MHz ;
Data transfers from:
Clock Domain: clk_c Source: clk.PAD
Covered under: FREQUENCY 8.000000 MHz ; Transfers: 16
Clock Domain: clk_o Source: clk_uart_lf/SLICE_654.Q0 Loads: 7
Covered under: FREQUENCY 8.000000 MHz ;
Data transfers from:
Clock Domain: uart_en Source: clock_lf/SLICE_1020.Q0
Covered under: FREQUENCY 8.000000 MHz ; Transfers: 17
Clock Domain: clk_c Source: clk.PAD Loads: 779
Covered under: FREQUENCY 8.000000 MHz ;
Data transfers from:
Clock Domain: uart_en Source: clock_lf/SLICE_1020.Q0
Covered under: FREQUENCY 8.000000 MHz ; Transfers: 2
Clock Domain: clk_o Source: clk_uart_lf/SLICE_654.Q0
Covered under: FREQUENCY 8.000000 MHz ; Transfers: 1
Clock Domain: B1_c Source: SLICE_235.Q0
Covered under: FREQUENCY 8.000000 MHz ; Transfers: 1
Clock Domain: clk_1ms Source: clk_1ms_lf/SLICE_653.Q0 Loads: 7
No transfer within this clock domain is found
Data transfers from:
Clock Domain: clk_c Source: clk.PAD
Covered under: FREQUENCY 8.000000 MHz ; Transfers: 47
Clock Domain: DS18B20Z_lf/clk_1mhz Source: DS18B20Z_lf/SLICE_237.Q0 Loads: 10
No transfer within this clock domain is found
Data transfers from:
Clock Domain: clk_c Source: clk.PAD
Covered under: FREQUENCY 8.000000 MHz ; Transfers: 21
Clock Domain: B1_c Source: SLICE_235.Q0 Loads: 16
No transfer within this clock domain is found
Data transfers from:
Clock Domain: clk_c Source: clk.PAD
Covered under: FREQUENCY 8.000000 MHz ; Transfers: 8
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 2147483647 paths, 6 nets, and 14997 connections (94.04% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.11.0.396.4
Tue Feb 23 11:26:23 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o lf_project_impl1.tw1 -gui -msgset C:/Users/17152/Desktop/lf_project - 1.0/promote.xml lf_project_impl1_map.ncd lf_project_impl1.prf
Design file: lf_project_impl1_map.ncd
Preference file: lf_project_impl1.prf
Device,speed: LCMXO2-4000HC,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY 8.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
================================================================================
Preference: FREQUENCY 8.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.441ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q buzzer_lf/num_i0_i3 (from clk_c +)
Destination: FF Data in buzzer_lf/num_i0_i3 (to clk_c +)
Delay: 0.428ns (53.3% logic, 46.7% route), 2 logic levels.
Constraint Details:
0.428ns physical path delay buzzer_lf/SLICE_634 to buzzer_lf/SLICE_634 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.441ns
Physical Path Details:
Data path buzzer_lf/SLICE_634 to buzzer_lf/SLICE_634:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 *SLICE_634.CLK to */SLICE_634.Q0 buzzer_lf/SLICE_634 (from clk_c)
ROUTE 7 e 0.199 */SLICE_634.Q0 to */SLICE_634.M0 buzzer_lf/num_3
MTOOFX_DEL --- 0.095 */SLICE_634.M0 to *LICE_634.OFX0 buzzer_lf/SLICE_634
ROUTE 1 e 0.001 *LICE_634.OFX0 to *SLICE_634.DI0 buzzer_lf/num_5_N_1992_3 (to clk_c)
--------
0.428 (53.3% logic, 46.7% route), 2 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY 8.000000 MHz ; | -| -| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 6 clocks:
Clock Domain: uart_en Source: clock_lf/SLICE_1020.Q0 Loads: 13
Covered under: FREQUENCY 8.000000 MHz ;
Data transfers from:
Clock Domain: clk_c Source: clk.PAD
Covered under: FREQUENCY 8.000000 MHz ; Transfers: 16
Clock Domain: clk_o Source: clk_uart_lf/SLICE_654.Q0 Loads: 7
Covered under: FREQUENCY 8.000000 MHz ;
Data transfers from:
Clock Domain: uart_en Source: clock_lf/SLICE_1020.Q0
Covered under: FREQUENCY 8.000000 MHz ; Transfers: 17
Clock Domain: clk_c Source: clk.PAD Loads: 779
Covered under: FREQUENCY 8.000000 MHz ;
Data transfers from:
Clock Domain: uart_en Source: clock_lf/SLICE_1020.Q0
Covered under: FREQUENCY 8.000000 MHz ; Transfers: 2
Clock Domain: clk_o Source: clk_uart_lf/SLICE_654.Q0
Covered under: FREQUENCY 8.000000 MHz ; Transfers: 1
Clock Domain: B1_c Source: SLICE_235.Q0
Covered under: FREQUENCY 8.000000 MHz ; Transfers: 1
Clock Domain: clk_1ms Source: clk_1ms_lf/SLICE_653.Q0 Loads: 7
No transfer within this clock domain is found
Data transfers from:
Clock Domain: clk_c Source: clk.PAD
Covered under: FREQUENCY 8.000000 MHz ; Transfers: 47
Clock Domain: DS18B20Z_lf/clk_1mhz Source: DS18B20Z_lf/SLICE_237.Q0 Loads: 10
No transfer within this clock domain is found
Data transfers from:
Clock Domain: clk_c Source: clk.PAD
Covered under: FREQUENCY 8.000000 MHz ; Transfers: 21
Clock Domain: B1_c Source: SLICE_235.Q0 Loads: 16
No transfer within this clock domain is found
Data transfers from:
Clock Domain: clk_c Source: clk.PAD
Covered under: FREQUENCY 8.000000 MHz ; Transfers: 8
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 2147483647 paths, 6 nets, and 15782 connections (98.96% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------