I/O Timing Report 19 potential circuit loops found in timing analysis. Loading design for application iotiming from file lf_project_impl1.ncd. Design name: lf_project NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-4000HC Package: CSBGA132 Performance: 5 Package Status: Final Version 1.44. Performance Hardware Data Status: Final Version 34.4. Loading design for application iotiming from file lf_project_impl1.ncd. Design name: lf_project NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-4000HC Package: CSBGA132 Performance: 6 Package Status: Final Version 1.44. Performance Hardware Data Status: Final Version 34.4. Loading design for application iotiming from file lf_project_impl1.ncd. Design name: lf_project NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-4000HC Package: CSBGA132 Performance: M Package Status: Final Version 1.44. Performance Hardware Data Status: Final Version 34.4. // Design: lf_project // Package: CSBGA132 // ncd File: lf_project_impl1.ncd // Version: Diamond (64-bit) 3.11.0.396.4 // Written on Mon Feb 22 21:11:35 2021 // M: Minimum Performance Grade // iotiming lf_project_impl1.ncd lf_project_impl1.prf -gui -msgset C:/Users/17152/Desktop/lf_project - 1.0/promote.xml I/O Timing Report (All units are in ns) Worst Case Results across Performance Grades (M, 6, 5, 4): // Input Setup and Hold Times Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- hour clk R 12.348 4 0.116 M min_a clk R 16.714 4 1.154 4 min_d clk R 14.035 4 -0.154 M one_wire clk R 3.849 4 0.797 4 rst_n clk R 15.085 4 0.772 4 uart_in clk R 14.930 4 0.496 6 // Clock to Output Delay Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ B1 clk R 11.058 4 3.457 M beeper clk R 10.166 4 3.243 M oled_clk clk R 10.846 4 3.408 M oled_csn clk R 10.275 4 3.233 M oled_dat clk R 10.347 4 3.268 M oled_dcn clk R 10.693 4 3.333 M oled_rst clk R 10.716 4 3.384 M // Internal_Clock to Input Port Internal_Clock -------------------------------------------------------- one_wire DS18B20Z_lf/clk_1mhz rst_n clk_1ms rst_n clock_lf/hour_out_7_ rst_n clock_lf/hour_out_7_ rst_n clock_lf/hour_out_7_ rst_n clock_lf/hour_out_7_ rst_n clock_lf/hour_out_7_ rst_n clock_lf/hour_out_7_ rst_n clock_lf/hour_out_7_ rst_n clock_lf/hour_out_7_ rst_n clock_lf/hour_out_7_ rst_n clock_lf/hour_out_7_ rst_n clock_lf/hour_out_7_ rst_n clock_lf/hour_out_7_ rst_n clock_lf/hour_out_7_ rst_n clock_lf/min_out_4_d rst_n clock_lf/hour_out_7_ rst_n uart_en rst_n clk_o // Internal_Clock to Output Port Internal_Clock -------------------------------------------------------- one_wire DS18B20Z_lf/clk_1mhz uart_out clk_o WARNING: you must also run trce with hold speed: 4 WARNING: you must also run trce with hold speed: 6