PAR: Place And Route Diamond (64-bit) 3.11.0.396.4. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. Tue Feb 23 11:26:24 2021 D:/diamond/diamond/3.11_x64/ispfpga\bin\nt64\par -f lf_project_impl1.p2t lf_project_impl1_map.ncd lf_project_impl1.dir lf_project_impl1.prf -gui -msgset C:/Users/17152/Desktop/lf_project - 1.0/promote.xml Preference file: lf_project_impl1.prf. Cost Table Summary Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ 5_1 * 0 40.402 0 0.048 0 44 Completed * : Design saved. Total (real) run time for 1-seed: 44 secs par done! Note: user must run 'Trace' for timing closure signoff. Lattice Place and Route Report for Design "lf_project_impl1_map.ncd" Tue Feb 23 11:26:24 2021 Best Par Run PAR: Place And Route Diamond (64-bit) 3.11.0.396.4. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset "C:/Users/17152/Desktop/lf_project - 1.0/promote.xml" -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF lf_project_impl1_map.ncd lf_project_impl1.dir/5_1.ncd lf_project_impl1.prf Preference file: lf_project_impl1.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file lf_project_impl1_map.ncd. Design name: lf_project NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-4000HC Package: CSBGA132 Performance: 4 Loading device for application par from file 'xo2c4000.nph' in environment: D:/diamond/diamond/3.11_x64/ispfpga. Package Status: Final Version 1.44. Performance Hardware Data Status: Final Version 34.4. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 28+4(JTAG)/280 11% used 28+4(JTAG)/105 30% bonded SLICE 1759/2160 81% used GSR 1/1 100% used Number of Signals: 4577 Number of Connections: 15948 Pin Constraint Summary: 28 out of 28 pins locked (100% locked). The following 2 signals are selected to use the primary clock routing resources: clk_c (driver: clk, clk load #: 779) uart_en (driver: clock_lf/SLICE_1020, clk load #: 13) WARNING - par: Signal "clk_c" is selected to use Primary clock resources. However, its driver comp "clk" is located at "C1", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. The following 8 signals are selected to use the secondary clock routing resources: clk_c_enable_925 (driver: SLICE_2115, clk load #: 0, sr load #: 0, ce load #: 156) n90736 (driver: SLICE_1655, clk load #: 0, sr load #: 25, ce load #: 0) n90734 (driver: SLICE_2099, clk load #: 0, sr load #: 25, ce load #: 0) n90737 (driver: SLICE_2100, clk load #: 0, sr load #: 25, ce load #: 0) n90738 (driver: SLICE_2101, clk load #: 0, sr load #: 25, ce load #: 0) n90739 (driver: SLICE_2115, clk load #: 0, sr load #: 25, ce load #: 0) n90735 (driver: SLICE_2099, clk load #: 0, sr load #: 25, ce load #: 0) clk_c_enable_613 (driver: SLICE_235, clk load #: 0, sr load #: 0, ce load #: 13) Signal rst_n_c is selected as Global Set/Reset. Starting Placer Phase 0. .......... Finished Placer Phase 0. REAL time: 8 secs Starting Placer Phase 1. ....................... Placer score = 1027336. Finished Placer Phase 1. REAL time: 19 secs Starting Placer Phase 2. . Placer score = 1016672 Finished Placer Phase 2. REAL time: 20 secs Clock Report Global Clock Resources: CLK_PIN : 0 out of 8 (0%) General PIO: 1 out of 280 (0%) PLL : 0 out of 2 (0%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Global Clocks: PRIMARY "clk_c" from comp "clk" on PIO site "C1 (PL4A)", clk load = 779 PRIMARY "uart_en" from Q0 on comp "clock_lf/SLICE_1020" on site "R2C16D", clk load = 13 SECONDARY "clk_c_enable_925" from F1 on comp "SLICE_2115" on site "R12C17B", clk load = 0, ce load = 156, sr load = 0 SECONDARY "n90736" from F0 on comp "SLICE_1655" on site "R12C15C", clk load = 0, ce load = 0, sr load = 25 SECONDARY "n90734" from F0 on comp "SLICE_2099" on site "R12C17A", clk load = 0, ce load = 0, sr load = 25 SECONDARY "n90737" from F0 on comp "SLICE_2100" on site "R12C15D", clk load = 0, ce load = 0, sr load = 25 SECONDARY "n90738" from F0 on comp "SLICE_2101" on site "R12C17C", clk load = 0, ce load = 0, sr load = 25 SECONDARY "n90739" from F0 on comp "SLICE_2115" on site "R12C17B", clk load = 0, ce load = 0, sr load = 25 SECONDARY "n90735" from F1 on comp "SLICE_2099" on site "R12C17A", clk load = 0, ce load = 0, sr load = 25 SECONDARY "clk_c_enable_613" from F1 on comp "SLICE_235" on site "R12C15A", clk load = 0, ce load = 13, sr load = 0 PRIMARY : 2 out of 8 (25%) SECONDARY: 8 out of 8 (100%) Edge Clocks: No edge clock selected. I/O Usage Summary (final): 28 + 4(JTAG) out of 280 (11.4%) PIO sites used. 28 + 4(JTAG) out of 105 (30.5%) bonded PIO sites used. Number of PIO comps: 28; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+----------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+----------------+------------+-----------+ | 0 | 2 / 26 ( 7%) | 3.3V | - | | 1 | 11 / 26 ( 42%) | 3.3V | - | | 2 | 13 / 28 ( 46%) | 3.3V | - | | 3 | 1 / 7 ( 14%) | 3.3V | - | | 4 | 0 / 8 ( 0%) | - | - | | 5 | 1 / 10 ( 10%) | 3.3V | - | +----------+----------------+------------+-----------+ Total placer CPU time: 20 secs Dumping design to file lf_project_impl1.dir/5_1.ncd. 0 connections routed; 15948 unrouted. Starting router resource preassignment WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Signal=B1_c loads=16 clock_loads=1 Signal=clk_o loads=7 clock_loads=6 Signal=clk_1ms loads=7 clock_loads=1 Signal=DS18B20Z_lf/clk_1mhz loads=10 clock_loads=2 Completed router resource preassignment. Real time: 26 secs Start NBR router at 11:26:50 02/23/21 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** Start NBR special constraint process at 11:26:50 02/23/21 Start NBR section for initial routing at 11:26:51 02/23/21 Level 4, iteration 1 671(0.28%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 40.770ns/0.000ns; real time: 29 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 17 (2.74%) Start NBR section for normal routing at 11:26:53 02/23/21 Level 4, iteration 1 325(0.14%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 40.411ns/0.000ns; real time: 30 secs Level 4, iteration 2 141(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 40.404ns/0.000ns; real time: 31 secs Level 4, iteration 3 68(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 40.404ns/0.000ns; real time: 31 secs Level 4, iteration 4 31(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 40.404ns/0.000ns; real time: 32 secs Level 4, iteration 5 11(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 40.404ns/0.000ns; real time: 32 secs Level 4, iteration 6 6(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 40.404ns/0.000ns; real time: 32 secs Level 4, iteration 7 3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 40.404ns/0.000ns; real time: 32 secs Level 4, iteration 8 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 40.404ns/0.000ns; real time: 32 secs Start NBR section for setup/hold timing optimization with effort level 3 at 11:26:56 02/23/21 Level 4, iteration 0 Level 4, iteration 1 2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<hold >: 0.043ns/0.000ns; real time: 39 secs Level 4, iteration 2 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<hold >: 0.043ns/0.000ns; real time: 39 secs Level 4, iteration 0 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 40.382ns/0.000ns; real time: 40 secs Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 40.382ns/0.000ns; real time: 40 secs Start NBR section for re-routing at 11:27:04 02/23/21 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 40.402ns/0.000ns; real time: 40 secs Start NBR section for post-routing at 11:27:04 02/23/21 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) Estimated worst slack<setup> : 40.402ns Timing score<setup> : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Signal=B1_c loads=16 clock_loads=1 Signal=clk_o loads=7 clock_loads=6 Signal=clk_1ms loads=7 clock_loads=1 Signal=DS18B20Z_lf/clk_1mhz loads=10 clock_loads=2 Total CPU time 43 secs Total REAL time: 44 secs Completely routed. End of route. 15948 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 Timing score: 0 Dumping design to file lf_project_impl1.dir/5_1.ncd. All signals are completely routed. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack<setup/<ns>> = 40.402 PAR_SUMMARY::Timing score<setup/<ns>> = 0.000 PAR_SUMMARY::Worst slack<hold /<ns>> = 0.048 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000 PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 44 secs Total REAL time to completion: 44 secs par done! Note: user must run 'Trace' for timing closure signoff. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.