module clk_uart_tx(clk_in,clk_out);//9600Baud
input clk_in;
output clk_out;
reg clk_out;
reg[9:0] times;
initial
    times = 0;
always @(posedge clk_in)
    begin
	 if(times < 625)
	     times = times+1;
	 else
	     begin
		  clk_out = ~clk_out;
		  times = 0;
		  end
	 end
endmodule
