module clk_buzzer(clk_in,clk_out);
input clk_in;
output clk_out;
reg clk_out;
reg [22:0] times_out;

initial
    begin
	 times_out = 0;
	 clk_out = 0;
	 end
always @(posedge clk_in)
    begin
	 if(time_out < 1200000)
	     begin
		  time_out = time_out+1;
		  end
	 else
	     begin
		  clk_out = ~clk_out;
		  time_out = 0;
		  end
    end
endmodule	 