{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1611646630401 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611646630412 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 26 15:37:10 2021 " "Processing started: Tue Jan 26 15:37:10 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611646630412 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646630412 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off pro_1 -c pro_1 " "Command: quartus_map --read_settings_files=on --write_settings_files=off pro_1 -c pro_1" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646630412 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1611646631641 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1611646631641 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pro_1.bdf 1 1 " "Found 1 design units, including 1 entities, in source file pro_1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 pro_1 " "Found entity 1: pro_1" {  } { { "pro_1.bdf" "" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646641312 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646641312 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "temperature.v(35) " "Verilog HDL information at temperature.v(35): always construct contains both blocking and non-blocking assignments" {  } { { "temperature.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/temperature.v" 35 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1611646641315 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "temperature.v 1 1 " "Found 1 design units, including 1 entities, in source file temperature.v" { { "Info" "ISGN_ENTITY_NAME" "1 temperature " "Found entity 1: temperature" {  } { { "temperature.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/temperature.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646641316 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646641316 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_1mhz.v 1 1 " "Found 1 design units, including 1 entities, in source file clk_1mhz.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_1MHz " "Found entity 1: clk_1MHz" {  } { { "clk_1MHz.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_1MHz.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646641319 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646641319 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tem_trans.v 1 1 " "Found 1 design units, including 1 entities, in source file tem_trans.v" { { "Info" "ISGN_ENTITY_NAME" "1 tem_trans " "Found entity 1: tem_trans" {  } { { "tem_trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646641321 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646641321 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CMD cmd OLED.v(10) " "Verilog HDL Declaration information at OLED.v(10): object \"CMD\" differs only in case from object \"cmd\" in the same scope" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 10 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1611646641325 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "oled.v 1 1 " "Found 1 design units, including 1 entities, in source file oled.v" { { "Info" "ISGN_ENTITY_NAME" "1 OLED " "Found entity 1: OLED" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646641325 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646641325 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reset.v 1 1 " "Found 1 design units, including 1 entities, in source file reset.v" { { "Info" "ISGN_ENTITY_NAME" "1 reset " "Found entity 1: reset" {  } { { "reset.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/reset.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646641328 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646641328 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_buzzer.v 1 1 " "Found 1 design units, including 1 entities, in source file clk_buzzer.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_buzzer " "Found entity 1: clk_buzzer" {  } { { "clk_buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_buzzer.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646641331 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646641331 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "buzzer.v(30) " "Verilog HDL information at buzzer.v(30): always construct contains both blocking and non-blocking assignments" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 30 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1611646641333 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "buzzer.v(73) " "Verilog HDL information at buzzer.v(73): always construct contains both blocking and non-blocking assignments" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 73 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1611646641334 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "buzzer.v 1 1 " "Found 1 design units, including 1 entities, in source file buzzer.v" { { "Info" "ISGN_ENTITY_NAME" "1 buzzer " "Found entity 1: buzzer" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646641334 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646641334 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "pro_1 " "Elaborating entity \"pro_1\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1611646641518 ""}
{ "Warning" "WSGN_SEARCH_FILE" "uart_tx.v 1 1 " "Using design file uart_tx.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 uart_tx " "Found entity 1: uart_tx" {  } { { "uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_tx.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646641548 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1611646641548 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_tx uart_tx:inst4 " "Elaborating entity \"uart_tx\" for hierarchy \"uart_tx:inst4\"" {  } { { "pro_1.bdf" "inst4" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -240 -8384 -8200 -128 "inst4" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646641548 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_tx.v(28) " "Verilog HDL assignment warning at uart_tx.v(28): truncated value with size 2 to match size of target (1)" {  } { { "uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_tx.v" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641550 "|pro_1|uart_tx:inst4"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_tx.v(42) " "Verilog HDL assignment warning at uart_tx.v(42): truncated value with size 2 to match size of target (1)" {  } { { "uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_tx.v" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641550 "|pro_1|uart_tx:inst4"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 uart_tx.v(48) " "Verilog HDL assignment warning at uart_tx.v(48): truncated value with size 32 to match size of target (6)" {  } { { "uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_tx.v" 48 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641550 "|pro_1|uart_tx:inst4"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_tx.v(53) " "Verilog HDL assignment warning at uart_tx.v(53): truncated value with size 2 to match size of target (1)" {  } { { "uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_tx.v" 53 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641550 "|pro_1|uart_tx:inst4"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "tab.data_a 0 uart_tx.v(9) " "Net \"tab.data_a\" at uart_tx.v(9) has no driver or initial value, using a default initial value '0'" {  } { { "uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_tx.v" 9 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646641550 "|pro_1|uart_tx:inst4"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "tab.waddr_a 0 uart_tx.v(9) " "Net \"tab.waddr_a\" at uart_tx.v(9) has no driver or initial value, using a default initial value '0'" {  } { { "uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_tx.v" 9 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646641550 "|pro_1|uart_tx:inst4"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "tab.we_a 0 uart_tx.v(9) " "Net \"tab.we_a\" at uart_tx.v(9) has no driver or initial value, using a default initial value '0'" {  } { { "uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_tx.v" 9 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646641551 "|pro_1|uart_tx:inst4"}
{ "Warning" "WSGN_SEARCH_FILE" "clk_uart_tx.v 1 1 " "Using design file clk_uart_tx.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 clk_uart_tx " "Found entity 1: clk_uart_tx" {  } { { "clk_uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_uart_tx.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646641559 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1611646641559 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_uart_tx clk_uart_tx:inst2 " "Elaborating entity \"clk_uart_tx\" for hierarchy \"clk_uart_tx:inst2\"" {  } { { "pro_1.bdf" "inst2" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -208 -9528 -9376 -128 "inst2" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646641559 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 clk_uart_tx.v(11) " "Verilog HDL assignment warning at clk_uart_tx.v(11): truncated value with size 32 to match size of target (10)" {  } { { "clk_uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_uart_tx.v" 11 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641559 "|pro_1|clk_uart_tx:inst2"}
{ "Warning" "WSGN_SEARCH_FILE" "clock.v 1 1 " "Using design file clock.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Found entity 1: clock" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646641567 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1611646641567 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock clock:inst1 " "Elaborating entity \"clock\" for hierarchy \"clock:inst1\"" {  } { { "pro_1.bdf" "inst1" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -368 -9160 -8960 -224 "inst1" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646641568 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(32) " "Verilog HDL assignment warning at clock.v(32): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 32 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641569 "|pro_1|clock:inst1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(38) " "Verilog HDL assignment warning at clock.v(38): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641569 "|pro_1|clock:inst1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(44) " "Verilog HDL assignment warning at clock.v(44): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 44 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641569 "|pro_1|clock:inst1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(50) " "Verilog HDL assignment warning at clock.v(50): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 50 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641569 "|pro_1|clock:inst1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 clock.v(76) " "Verilog HDL assignment warning at clock.v(76): truncated value with size 32 to match size of target (16)" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 76 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641569 "|pro_1|clock:inst1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(79) " "Verilog HDL assignment warning at clock.v(79): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 79 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641569 "|pro_1|clock:inst1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(83) " "Verilog HDL assignment warning at clock.v(83): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 83 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641569 "|pro_1|clock:inst1"}
{ "Warning" "WSGN_SEARCH_FILE" "clk_second.v 1 1 " "Using design file clk_second.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 clk_second " "Found entity 1: clk_second" {  } { { "clk_second.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_second.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646641578 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1611646641578 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_second clk_second:inst " "Elaborating entity \"clk_second\" for hierarchy \"clk_second:inst\"" {  } { { "pro_1.bdf" "inst" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -304 -9528 -9360 -224 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646641578 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 clk_second.v(18) " "Verilog HDL assignment warning at clk_second.v(18): truncated value with size 32 to match size of target (23)" {  } { { "clk_second.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_second.v" 18 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641579 "|pro_1|clk_second:inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 clk_second.v(27) " "Verilog HDL assignment warning at clk_second.v(27): truncated value with size 32 to match size of target (23)" {  } { { "clk_second.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_second.v" 27 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641579 "|pro_1|clk_second:inst"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tem_trans tem_trans:inst9 " "Elaborating entity \"tem_trans\" for hierarchy \"tem_trans:inst9\"" {  } { { "pro_1.bdf" "inst9" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -24 -8656 -8440 88 "inst9" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646641579 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 tem_trans.v(13) " "Verilog HDL assignment warning at tem_trans.v(13): truncated value with size 32 to match size of target (21)" {  } { { "tem_trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 13 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641580 "|pro_1|tem_trans:inst9"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 tem_trans.v(14) " "Verilog HDL assignment warning at tem_trans.v(14): truncated value with size 32 to match size of target (8)" {  } { { "tem_trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 14 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641580 "|pro_1|tem_trans:inst9"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 tem_trans.v(15) " "Verilog HDL assignment warning at tem_trans.v(15): truncated value with size 32 to match size of target (8)" {  } { { "tem_trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 15 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641580 "|pro_1|tem_trans:inst9"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "temperature temperature:inst8 " "Elaborating entity \"temperature\" for hierarchy \"temperature:inst8\"" {  } { { "pro_1.bdf" "inst8" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -40 -9008 -8840 40 "inst8" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646641581 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 temperature.v(68) " "Verilog HDL assignment warning at temperature.v(68): truncated value with size 32 to match size of target (4)" {  } { { "temperature.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/temperature.v" 68 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641582 "|pro_1|temperature:inst8"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 temperature.v(134) " "Verilog HDL assignment warning at temperature.v(134): truncated value with size 32 to match size of target (3)" {  } { { "temperature.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/temperature.v" 134 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641583 "|pro_1|temperature:inst8"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_1MHz clk_1MHz:inst7 " "Elaborating entity \"clk_1MHz\" for hierarchy \"clk_1MHz:inst7\"" {  } { { "pro_1.bdf" "inst7" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -40 -9528 -9376 40 "inst7" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646641583 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 clk_1MHz.v(9) " "Verilog HDL assignment warning at clk_1MHz.v(9): truncated value with size 32 to match size of target (3)" {  } { { "clk_1MHz.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_1MHz.v" 9 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641583 "|pro_1|clk_1MHz:inst7"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reset reset:inst12 " "Elaborating entity \"reset\" for hierarchy \"reset:inst12\"" {  } { { "pro_1.bdf" "inst12" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -8 -9160 -9024 104 "inst12" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646641584 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "OLED OLED:inst10 " "Elaborating entity \"OLED\" for hierarchy \"OLED:inst10\"" {  } { { "pro_1.bdf" "inst10" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -432 -8112 -7928 -224 "inst10" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646641585 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 OLED.v(84) " "Verilog HDL assignment warning at OLED.v(84): truncated value with size 32 to match size of target (5)" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 84 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641589 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "cmd.data_a 0 OLED.v(14) " "Net \"cmd.data_a\" at OLED.v(14) has no driver or initial value, using a default initial value '0'" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 14 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646641589 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "cmd.waddr_a 0 OLED.v(14) " "Net \"cmd.waddr_a\" at OLED.v(14) has no driver or initial value, using a default initial value '0'" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 14 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646641589 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 OLED.v(15) " "Net \"mem.data_a\" at OLED.v(15) has no driver or initial value, using a default initial value '0'" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 15 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646641589 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 OLED.v(15) " "Net \"mem.waddr_a\" at OLED.v(15) has no driver or initial value, using a default initial value '0'" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 15 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646641589 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "cmd.we_a 0 OLED.v(14) " "Net \"cmd.we_a\" at OLED.v(14) has no driver or initial value, using a default initial value '0'" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 14 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646641589 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 OLED.v(15) " "Net \"mem.we_a\" at OLED.v(15) has no driver or initial value, using a default initial value '0'" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 15 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646641589 "|pro_1|OLED:inst10"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "buzzer buzzer:inst13 " "Elaborating entity \"buzzer\" for hierarchy \"buzzer:inst13\"" {  } { { "pro_1.bdf" "inst13" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -128 -8368 -8184 16 "inst13" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646641589 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "flag_1 buzzer.v(17) " "Verilog HDL or VHDL warning at buzzer.v(17): object \"flag_1\" assigned a value but never read" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 17 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1611646641592 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "flag_2 buzzer.v(17) " "Verilog HDL or VHDL warning at buzzer.v(17): object \"flag_2\" assigned a value but never read" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 17 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1611646641592 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 buzzer.v(26) " "Verilog HDL assignment warning at buzzer.v(26): truncated value with size 32 to match size of target (6)" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 26 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641592 "|pro_1|buzzer:inst13"}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "buzzer.v(36) " "Verilog HDL Case Statement information at buzzer.v(36): all case item expressions in this case statement are onehot" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 36 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1611646641592 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 buzzer.v(66) " "Verilog HDL assignment warning at buzzer.v(66): truncated value with size 8 to match size of target (4)" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641592 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 buzzer.v(67) " "Verilog HDL assignment warning at buzzer.v(67): truncated value with size 32 to match size of target (6)" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 67 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641592 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "buzzer.v(91) " "Verilog HDL Case Statement warning at buzzer.v(91): case item expression never matches the case expression" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 91 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "Analysis & Synthesis" 0 -1 1611646641592 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "buzzer.v(92) " "Verilog HDL Case Statement warning at buzzer.v(92): case item expression never matches the case expression" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 92 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "Analysis & Synthesis" 0 -1 1611646641592 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "buzzer.v(93) " "Verilog HDL Case Statement warning at buzzer.v(93): case item expression never matches the case expression" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 93 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "Analysis & Synthesis" 0 -1 1611646641593 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "buzzer.v(94) " "Verilog HDL Case Statement warning at buzzer.v(94): case item expression never matches the case expression" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 94 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "Analysis & Synthesis" 0 -1 1611646641593 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "buzzer.v(95) " "Verilog HDL Case Statement warning at buzzer.v(95): case item expression never matches the case expression" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 95 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "Analysis & Synthesis" 0 -1 1611646641593 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "buzzer.v(96) " "Verilog HDL Case Statement warning at buzzer.v(96): case item expression never matches the case expression" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 96 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "Analysis & Synthesis" 0 -1 1611646641593 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 buzzer.v(107) " "Verilog HDL assignment warning at buzzer.v(107): truncated value with size 32 to match size of target (18)" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 107 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641593 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 buzzer.v(113) " "Verilog HDL assignment warning at buzzer.v(113): truncated value with size 32 to match size of target (24)" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 113 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641593 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "judge\[2\] 0 buzzer.v(18) " "Net \"judge\[2\]\" at buzzer.v(18) has no driver or initial value, using a default initial value '0'" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 18 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646641593 "|pro_1|buzzer:inst13"}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "TIMES times uart_rx.v(5) " "Verilog HDL Declaration information at uart_rx.v(5): object \"TIMES\" differs only in case from object \"times\" in the same scope" {  } { { "uart_rx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_rx.v" 5 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1611646641601 ""}
{ "Warning" "WSGN_SEARCH_FILE" "uart_rx.v 1 1 " "Using design file uart_rx.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 uart_rx " "Found entity 1: uart_rx" {  } { { "uart_rx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_rx.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646641601 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1611646641601 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_rx uart_rx:inst3 " "Elaborating entity \"uart_rx\" for hierarchy \"uart_rx:inst3\"" {  } { { "pro_1.bdf" "inst3" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -128 -8952 -8768 -48 "inst3" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646641602 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 uart_rx.v(37) " "Verilog HDL assignment warning at uart_rx.v(37): truncated value with size 32 to match size of target (11)" {  } { { "uart_rx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_rx.v" 37 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641606 "|pro_1|uart_rx:inst3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 uart_rx.v(38) " "Verilog HDL assignment warning at uart_rx.v(38): truncated value with size 32 to match size of target (11)" {  } { { "uart_rx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_rx.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641606 "|pro_1|uart_rx:inst3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 uart_rx.v(57) " "Verilog HDL assignment warning at uart_rx.v(57): truncated value with size 32 to match size of target (11)" {  } { { "uart_rx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_rx.v" 57 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641606 "|pro_1|uart_rx:inst3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 uart_rx.v(60) " "Verilog HDL assignment warning at uart_rx.v(60): truncated value with size 32 to match size of target (11)" {  } { { "uart_rx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_rx.v" 60 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641606 "|pro_1|uart_rx:inst3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 uart_rx.v(72) " "Verilog HDL assignment warning at uart_rx.v(72): truncated value with size 32 to match size of target (4)" {  } { { "uart_rx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_rx.v" 72 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641606 "|pro_1|uart_rx:inst3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 uart_rx.v(88) " "Verilog HDL assignment warning at uart_rx.v(88): truncated value with size 32 to match size of target (6)" {  } { { "uart_rx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_rx.v" 88 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641606 "|pro_1|uart_rx:inst3"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_buzzer clk_buzzer:inst11 " "Elaborating entity \"clk_buzzer\" for hierarchy \"clk_buzzer:inst11\"" {  } { { "pro_1.bdf" "inst11" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { 136 -9528 -9376 216 "inst11" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646641606 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 clk_buzzer.v(16) " "Verilog HDL assignment warning at clk_buzzer.v(16): truncated value with size 32 to match size of target (23)" {  } { { "clk_buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_buzzer.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641606 "|pro_1|clk_buzzer:inst11"}
{ "Warning" "WSGN_SEARCH_FILE" "trans.v 1 1 " "Using design file trans.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 trans " "Found entity 1: trans" {  } { { "trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646641615 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1611646641615 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "trans trans:inst5 " "Elaborating entity \"trans\" for hierarchy \"trans:inst5\"" {  } { { "pro_1.bdf" "inst5" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -400 -8856 -8640 -320 "inst5" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646641615 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 trans.v(7) " "Verilog HDL assignment warning at trans.v(7): truncated value with size 32 to match size of target (8)" {  } { { "trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 7 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641616 "|pro_1|trans:inst5"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 trans.v(8) " "Verilog HDL assignment warning at trans.v(8): truncated value with size 32 to match size of target (8)" {  } { { "trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 8 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646641616 "|pro_1|trans:inst5"}
{ "Critical Warning" "WCDB_CDB_LESS_INI_CONTENT" "16 10 C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram0_uart_tx_5cd61368.hdl.mif " "Memory depth (16) in the design file differs from memory depth (10) in the Memory Initialization File \"C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram0_uart_tx_5cd61368.hdl.mif\" -- setting initial value for remaining addresses to 0" {  } {  } 1 127005 "Memory depth (%1!d!) in the design file differs from memory depth (%2!d!) in the Memory Initialization File \"%3!s!\" -- setting initial value for remaining addresses to 0" 0 0 "Analysis & Synthesis" 0 -1 1611646642138 ""}
{ "Critical Warning" "WCDB_CDB_LESS_INI_CONTENT" "32 25 C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram0_OLED_2af399.hdl.mif " "Memory depth (32) in the design file differs from memory depth (25) in the Memory Initialization File \"C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram0_OLED_2af399.hdl.mif\" -- setting initial value for remaining addresses to 0" {  } {  } 1 127005 "Memory depth (%1!d!) in the design file differs from memory depth (%2!d!) in the Memory Initialization File \"%3!s!\" -- setting initial value for remaining addresses to 0" 0 0 "Analysis & Synthesis" 0 -1 1611646642139 ""}
{ "Critical Warning" "WCDB_CDB_LESS_INI_CONTENT" "128 124 C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram1_OLED_2af399.hdl.mif " "Memory depth (128) in the design file differs from memory depth (124) in the Memory Initialization File \"C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram1_OLED_2af399.hdl.mif\" -- setting initial value for remaining addresses to 0" {  } {  } 1 127005 "Memory depth (%1!d!) in the design file differs from memory depth (%2!d!) in the Memory Initialization File \"%3!s!\" -- setting initial value for remaining addresses to 0" 0 0 "Analysis & Synthesis" 0 -1 1611646642141 ""}
{ "Warning" "WCDB_CDB_RAM_MIF_CONTAIN_DONT_CARE" "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram1_OLED_2af399.hdl.mif " "Memory Initialization File or Hexadecimal (Intel-Format) File \"C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram1_OLED_2af399.hdl.mif\" contains \"don't care\" values -- overwriting them with 0s" {  } {  } 0 127007 "Memory Initialization File or Hexadecimal (Intel-Format) File \"%1!s!\" contains \"don't care\" values -- overwriting them with 0s" 0 0 "Analysis & Synthesis" 0 -1 1611646642144 ""}
{ "Info" "IINFER_UNINFERRED_RAM_SUMMARY" "3 " "Found 3 instances of uninferred RAM logic" { { "Info" "IINFER_MIF_NOT_SUPPORTED_FOR_HARDCOPY" "uart_tx:inst4\|tab " "RAM logic \"uart_tx:inst4\|tab\" is uninferred because MIF is not supported for the selected family" {  } { { "uart_tx.v" "tab" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_tx.v" 9 -1 0 } }  } 0 276013 "RAM logic \"%1!s!\" is uninferred because MIF is not supported for the selected family" 0 0 "Design Software" 0 -1 1611646642165 ""} { "Info" "IINFER_MIF_NOT_SUPPORTED_FOR_HARDCOPY" "OLED:inst10\|cmd " "RAM logic \"OLED:inst10\|cmd\" is uninferred because MIF is not supported for the selected family" {  } { { "OLED.v" "cmd" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 14 -1 0 } }  } 0 276013 "RAM logic \"%1!s!\" is uninferred because MIF is not supported for the selected family" 0 0 "Design Software" 0 -1 1611646642165 ""} { "Info" "IINFER_MIF_NOT_SUPPORTED_FOR_HARDCOPY" "OLED:inst10\|mem " "RAM logic \"OLED:inst10\|mem\" is uninferred because MIF is not supported for the selected family" {  } { { "OLED.v" "mem" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 15 -1 0 } }  } 0 276013 "RAM logic \"%1!s!\" is uninferred because MIF is not supported for the selected family" 0 0 "Design Software" 0 -1 1611646642165 ""}  } {  } 0 276014 "Found %1!d! instances of uninferred RAM logic" 0 0 "Analysis & Synthesis" 0 -1 1611646642165 ""}
{ "Warning" "WCDB_CDB_RAM_MIF_CONTAIN_DONT_CARE" "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram1_OLED_2af399.hdl.mif " "Memory Initialization File or Hexadecimal (Intel-Format) File \"C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram1_OLED_2af399.hdl.mif\" contains \"don't care\" values -- overwriting them with 0s" {  } {  } 0 127007 "Memory Initialization File or Hexadecimal (Intel-Format) File \"%1!s!\" contains \"don't care\" values -- overwriting them with 0s" 0 0 "Analysis & Synthesis" 0 -1 1611646642170 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "6 " "Inferred 6 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "tem_trans:inst9\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"tem_trans:inst9\|Mod0\"" {  } { { "tem_trans.v" "Mod0" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 15 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1611646643955 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "tem_trans:inst9\|Div1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"tem_trans:inst9\|Div1\"" {  } { { "tem_trans.v" "Div1" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 14 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1611646643955 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "trans:inst6\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"trans:inst6\|Div0\"" {  } { { "trans.v" "Div0" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 7 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1611646643955 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "trans:inst5\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"trans:inst5\|Div0\"" {  } { { "trans.v" "Div0" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 7 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1611646643955 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "trans:inst5\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"trans:inst5\|Mod0\"" {  } { { "trans.v" "Mod0" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 8 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1611646643955 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "trans:inst6\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"trans:inst6\|Mod0\"" {  } { { "trans.v" "Mod0" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 8 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1611646643955 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1611646643955 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "tem_trans:inst9\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"tem_trans:inst9\|lpm_divide:Mod0\"" {  } { { "tem_trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 15 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646643998 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tem_trans:inst9\|lpm_divide:Mod0 " "Instantiated megafunction \"tem_trans:inst9\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 21 " "Parameter \"LPM_WIDTHN\" = \"21\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646643998 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646643998 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646643998 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646643998 ""}  } { { "tem_trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 15 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1611646643998 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_nll.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_nll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_nll " "Found entity 1: lpm_divide_nll" {  } { { "db/lpm_divide_nll.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/lpm_divide_nll.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646644033 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646644033 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_mlh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_mlh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_mlh " "Found entity 1: sign_div_unsign_mlh" {  } { { "db/sign_div_unsign_mlh.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/sign_div_unsign_mlh.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646644043 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646644043 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_mhe.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_mhe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_mhe " "Found entity 1: alt_u_div_mhe" {  } { { "db/alt_u_div_mhe.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/alt_u_div_mhe.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646644063 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646644063 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_t3c.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_t3c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_t3c " "Found entity 1: add_sub_t3c" {  } { { "db/add_sub_t3c.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/add_sub_t3c.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646644106 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646644106 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_u3c.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_u3c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_u3c " "Found entity 1: add_sub_u3c" {  } { { "db/add_sub_u3c.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/add_sub_u3c.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646644143 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646644143 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "tem_trans:inst9\|lpm_divide:Div1 " "Elaborated megafunction instantiation \"tem_trans:inst9\|lpm_divide:Div1\"" {  } { { "tem_trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 14 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646644153 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tem_trans:inst9\|lpm_divide:Div1 " "Instantiated megafunction \"tem_trans:inst9\|lpm_divide:Div1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 21 " "Parameter \"LPM_WIDTHN\" = \"21\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646644153 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646644153 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646644153 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646644153 ""}  } { { "tem_trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 14 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1611646644153 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ktl.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_ktl.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ktl " "Found entity 1: lpm_divide_ktl" {  } { { "db/lpm_divide_ktl.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/lpm_divide_ktl.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646644189 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646644189 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "trans:inst6\|lpm_divide:Div0 " "Elaborated megafunction instantiation \"trans:inst6\|lpm_divide:Div0\"" {  } { { "trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 7 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646644199 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "trans:inst6\|lpm_divide:Div0 " "Instantiated megafunction \"trans:inst6\|lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 7 " "Parameter \"LPM_WIDTHN\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646644199 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646644199 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646644199 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646644199 ""}  } { { "trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 7 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1611646644199 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_8sl.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_8sl.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_8sl " "Found entity 1: lpm_divide_8sl" {  } { { "db/lpm_divide_8sl.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/lpm_divide_8sl.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646644233 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646644233 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_akh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_akh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_akh " "Found entity 1: sign_div_unsign_akh" {  } { { "db/sign_div_unsign_akh.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/sign_div_unsign_akh.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646644244 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646644244 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_uee.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_uee.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_uee " "Found entity 1: alt_u_div_uee" {  } { { "db/alt_u_div_uee.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/alt_u_div_uee.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646644255 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646644255 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "trans:inst5\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"trans:inst5\|lpm_divide:Mod0\"" {  } { { "trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 8 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646644270 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "trans:inst5\|lpm_divide:Mod0 " "Instantiated megafunction \"trans:inst5\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 7 " "Parameter \"LPM_WIDTHN\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646644270 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646644270 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646644270 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646644270 ""}  } { { "trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 8 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1611646644270 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_bkl.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_bkl.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_bkl " "Found entity 1: lpm_divide_bkl" {  } { { "db/lpm_divide_bkl.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/lpm_divide_bkl.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646644306 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646644306 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 4 -1 0 } } { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 55 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1611646644711 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1611646644712 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1611646646425 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "9 " "9 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1611646650339 ""}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "tem_trans:inst9\|lpm_divide:Div1\|lpm_divide_ktl:auto_generated\|sign_div_unsign_mlh:divider\|alt_u_div_mhe:divider\|add_sub_17_result_int\[0\]~10 " "Logic cell \"tem_trans:inst9\|lpm_divide:Div1\|lpm_divide_ktl:auto_generated\|sign_div_unsign_mlh:divider\|alt_u_div_mhe:divider\|add_sub_17_result_int\[0\]~10\"" {  } { { "db/alt_u_div_mhe.tdf" "add_sub_17_result_int\[0\]~10" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/alt_u_div_mhe.tdf" 72 23 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1611646650349 ""}  } {  } 0 17016 "Found the following redundant logic cells in design" 0 0 "Analysis & Synthesis" 0 -1 1611646650349 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/output_files/pro_1.map.smsg " "Generated suppressed messages file C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/output_files/pro_1.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646650401 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1611646650549 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646650549 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "2232 " "Implemented 2232 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1611646650717 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1611646650717 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "1 " "Implemented 1 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1611646650717 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2218 " "Implemented 2218 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1611646650717 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1611646650717 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 65 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 65 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4812 " "Peak virtual memory: 4812 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611646650745 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 26 15:37:30 2021 " "Processing ended: Tue Jan 26 15:37:30 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611646650745 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:20 " "Elapsed time: 00:00:20" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611646650745 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:29 " "Total CPU time (on all processors): 00:00:29" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611646650745 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646650745 ""}
