module clk_second(clk_in,clk_1ms,clk_500ms);
input clk_in;
output clk_1ms,clk_500ms;
reg clk_1ms,clk_500ms;
reg [22:0] times_1ms,times_500ms;

initial
    begin
    times_1ms = 0;
	 times_500ms = 0;
	 clk_1ms = 0;
	 clk_500ms = 0;
	 end
always @(posedge clk_in)
    begin
    if(times_1ms < 6000)
	     begin
	     times_1ms = times_1ms+1;
	     end
	 else
        begin
        clk_1ms = ~clk_1ms;
		  times_1ms = 0;
	     end
	 if(times_500ms < 3000000)
	     begin
		  times_500ms = times_500ms+1;
		  end
	 else
	     begin
		  clk_500ms = ~clk_500ms;
		  times_500ms = 0;
		  end
    end
endmodule	 