{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1611646165871 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611646165895 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 26 15:29:25 2021 " "Processing started: Tue Jan 26 15:29:25 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611646165895 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646165895 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off pro_1 -c pro_1 " "Command: quartus_map --read_settings_files=on --write_settings_files=off pro_1 -c pro_1" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646165906 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1611646167247 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1611646167248 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pro_1.bdf 1 1 " "Found 1 design units, including 1 entities, in source file pro_1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 pro_1 " "Found entity 1: pro_1" {  } { { "pro_1.bdf" "" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646177304 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646177304 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "temperature.v(35) " "Verilog HDL information at temperature.v(35): always construct contains both blocking and non-blocking assignments" {  } { { "temperature.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/temperature.v" 35 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1611646177409 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "temperature.v 1 1 " "Found 1 design units, including 1 entities, in source file temperature.v" { { "Info" "ISGN_ENTITY_NAME" "1 temperature " "Found entity 1: temperature" {  } { { "temperature.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/temperature.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646177412 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646177412 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_1mhz.v 1 1 " "Found 1 design units, including 1 entities, in source file clk_1mhz.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_1MHz " "Found entity 1: clk_1MHz" {  } { { "clk_1MHz.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_1MHz.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646177415 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646177415 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tem_trans.v 1 1 " "Found 1 design units, including 1 entities, in source file tem_trans.v" { { "Info" "ISGN_ENTITY_NAME" "1 tem_trans " "Found entity 1: tem_trans" {  } { { "tem_trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646177421 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646177421 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CMD cmd OLED.v(10) " "Verilog HDL Declaration information at OLED.v(10): object \"CMD\" differs only in case from object \"cmd\" in the same scope" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 10 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1611646177425 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "oled.v 1 1 " "Found 1 design units, including 1 entities, in source file oled.v" { { "Info" "ISGN_ENTITY_NAME" "1 OLED " "Found entity 1: OLED" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646177426 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646177426 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reset.v 1 1 " "Found 1 design units, including 1 entities, in source file reset.v" { { "Info" "ISGN_ENTITY_NAME" "1 reset " "Found entity 1: reset" {  } { { "reset.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/reset.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646177429 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646177429 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_buzzer.v 1 1 " "Found 1 design units, including 1 entities, in source file clk_buzzer.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_buzzer " "Found entity 1: clk_buzzer" {  } { { "clk_buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_buzzer.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646177432 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646177432 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "buzzer.v(30) " "Verilog HDL information at buzzer.v(30): always construct contains both blocking and non-blocking assignments" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 30 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1611646177435 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "buzzer.v(73) " "Verilog HDL information at buzzer.v(73): always construct contains both blocking and non-blocking assignments" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 73 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1611646177435 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "buzzer.v 1 1 " "Found 1 design units, including 1 entities, in source file buzzer.v" { { "Info" "ISGN_ENTITY_NAME" "1 buzzer " "Found entity 1: buzzer" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646177436 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646177436 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "pro_1 " "Elaborating entity \"pro_1\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1611646177868 ""}
{ "Warning" "WSGN_SEARCH_FILE" "uart_tx.v 1 1 " "Using design file uart_tx.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 uart_tx " "Found entity 1: uart_tx" {  } { { "uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_tx.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646178054 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1611646178054 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_tx uart_tx:inst4 " "Elaborating entity \"uart_tx\" for hierarchy \"uart_tx:inst4\"" {  } { { "pro_1.bdf" "inst4" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -240 -8384 -8200 -128 "inst4" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646178055 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_tx.v(28) " "Verilog HDL assignment warning at uart_tx.v(28): truncated value with size 2 to match size of target (1)" {  } { { "uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_tx.v" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178060 "|pro_1|uart_tx:inst4"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_tx.v(42) " "Verilog HDL assignment warning at uart_tx.v(42): truncated value with size 2 to match size of target (1)" {  } { { "uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_tx.v" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178060 "|pro_1|uart_tx:inst4"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 uart_tx.v(48) " "Verilog HDL assignment warning at uart_tx.v(48): truncated value with size 32 to match size of target (6)" {  } { { "uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_tx.v" 48 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178060 "|pro_1|uart_tx:inst4"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_tx.v(53) " "Verilog HDL assignment warning at uart_tx.v(53): truncated value with size 2 to match size of target (1)" {  } { { "uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_tx.v" 53 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178060 "|pro_1|uart_tx:inst4"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "tab.data_a 0 uart_tx.v(9) " "Net \"tab.data_a\" at uart_tx.v(9) has no driver or initial value, using a default initial value '0'" {  } { { "uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_tx.v" 9 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646178060 "|pro_1|uart_tx:inst4"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "tab.waddr_a 0 uart_tx.v(9) " "Net \"tab.waddr_a\" at uart_tx.v(9) has no driver or initial value, using a default initial value '0'" {  } { { "uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_tx.v" 9 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646178060 "|pro_1|uart_tx:inst4"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "tab.we_a 0 uart_tx.v(9) " "Net \"tab.we_a\" at uart_tx.v(9) has no driver or initial value, using a default initial value '0'" {  } { { "uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_tx.v" 9 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646178060 "|pro_1|uart_tx:inst4"}
{ "Warning" "WSGN_SEARCH_FILE" "clk_uart_tx.v 1 1 " "Using design file clk_uart_tx.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 clk_uart_tx " "Found entity 1: clk_uart_tx" {  } { { "clk_uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_uart_tx.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646178072 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1611646178072 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_uart_tx clk_uart_tx:inst2 " "Elaborating entity \"clk_uart_tx\" for hierarchy \"clk_uart_tx:inst2\"" {  } { { "pro_1.bdf" "inst2" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -208 -9528 -9376 -128 "inst2" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646178072 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 clk_uart_tx.v(11) " "Verilog HDL assignment warning at clk_uart_tx.v(11): truncated value with size 32 to match size of target (10)" {  } { { "clk_uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_uart_tx.v" 11 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178073 "|pro_1|clk_uart_tx:inst2"}
{ "Warning" "WSGN_SEARCH_FILE" "clock.v 1 1 " "Using design file clock.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Found entity 1: clock" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646178081 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1611646178081 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock clock:inst1 " "Elaborating entity \"clock\" for hierarchy \"clock:inst1\"" {  } { { "pro_1.bdf" "inst1" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -368 -9160 -8960 -224 "inst1" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646178081 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(32) " "Verilog HDL assignment warning at clock.v(32): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 32 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178083 "|pro_1|clock:inst1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(38) " "Verilog HDL assignment warning at clock.v(38): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178084 "|pro_1|clock:inst1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(44) " "Verilog HDL assignment warning at clock.v(44): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 44 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178084 "|pro_1|clock:inst1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(50) " "Verilog HDL assignment warning at clock.v(50): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 50 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178084 "|pro_1|clock:inst1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 clock.v(76) " "Verilog HDL assignment warning at clock.v(76): truncated value with size 32 to match size of target (16)" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 76 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178084 "|pro_1|clock:inst1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(79) " "Verilog HDL assignment warning at clock.v(79): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 79 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178084 "|pro_1|clock:inst1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(83) " "Verilog HDL assignment warning at clock.v(83): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 83 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178084 "|pro_1|clock:inst1"}
{ "Warning" "WSGN_SEARCH_FILE" "clk_second.v 1 1 " "Using design file clk_second.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 clk_second " "Found entity 1: clk_second" {  } { { "clk_second.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_second.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646178093 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1611646178093 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_second clk_second:inst " "Elaborating entity \"clk_second\" for hierarchy \"clk_second:inst\"" {  } { { "pro_1.bdf" "inst" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -304 -9528 -9360 -224 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646178093 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 clk_second.v(18) " "Verilog HDL assignment warning at clk_second.v(18): truncated value with size 32 to match size of target (23)" {  } { { "clk_second.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_second.v" 18 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178095 "|pro_1|clk_second:inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 clk_second.v(27) " "Verilog HDL assignment warning at clk_second.v(27): truncated value with size 32 to match size of target (23)" {  } { { "clk_second.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_second.v" 27 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178095 "|pro_1|clk_second:inst"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tem_trans tem_trans:inst9 " "Elaborating entity \"tem_trans\" for hierarchy \"tem_trans:inst9\"" {  } { { "pro_1.bdf" "inst9" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -24 -8656 -8440 88 "inst9" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646178095 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 tem_trans.v(13) " "Verilog HDL assignment warning at tem_trans.v(13): truncated value with size 32 to match size of target (21)" {  } { { "tem_trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 13 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178097 "|pro_1|tem_trans:inst9"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 tem_trans.v(14) " "Verilog HDL assignment warning at tem_trans.v(14): truncated value with size 32 to match size of target (8)" {  } { { "tem_trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 14 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178097 "|pro_1|tem_trans:inst9"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 tem_trans.v(15) " "Verilog HDL assignment warning at tem_trans.v(15): truncated value with size 32 to match size of target (8)" {  } { { "tem_trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 15 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178097 "|pro_1|tem_trans:inst9"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "temperature temperature:inst8 " "Elaborating entity \"temperature\" for hierarchy \"temperature:inst8\"" {  } { { "pro_1.bdf" "inst8" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -40 -9008 -8840 40 "inst8" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646178097 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 temperature.v(68) " "Verilog HDL assignment warning at temperature.v(68): truncated value with size 32 to match size of target (4)" {  } { { "temperature.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/temperature.v" 68 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178100 "|pro_1|temperature:inst8"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 temperature.v(134) " "Verilog HDL assignment warning at temperature.v(134): truncated value with size 32 to match size of target (3)" {  } { { "temperature.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/temperature.v" 134 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178100 "|pro_1|temperature:inst8"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_1MHz clk_1MHz:inst7 " "Elaborating entity \"clk_1MHz\" for hierarchy \"clk_1MHz:inst7\"" {  } { { "pro_1.bdf" "inst7" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -40 -9528 -9376 40 "inst7" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646178101 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 clk_1MHz.v(9) " "Verilog HDL assignment warning at clk_1MHz.v(9): truncated value with size 32 to match size of target (3)" {  } { { "clk_1MHz.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_1MHz.v" 9 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178102 "|pro_1|clk_1MHz:inst7"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reset reset:inst12 " "Elaborating entity \"reset\" for hierarchy \"reset:inst12\"" {  } { { "pro_1.bdf" "inst12" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -8 -9160 -9024 104 "inst12" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646178103 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "OLED OLED:inst10 " "Elaborating entity \"OLED\" for hierarchy \"OLED:inst10\"" {  } { { "pro_1.bdf" "inst10" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -432 -8024 -7840 -224 "inst10" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646178105 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 OLED.v(84) " "Verilog HDL assignment warning at OLED.v(84): truncated value with size 32 to match size of target (5)" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 84 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178110 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "cmd.data_a 0 OLED.v(14) " "Net \"cmd.data_a\" at OLED.v(14) has no driver or initial value, using a default initial value '0'" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 14 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646178110 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "cmd.waddr_a 0 OLED.v(14) " "Net \"cmd.waddr_a\" at OLED.v(14) has no driver or initial value, using a default initial value '0'" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 14 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646178110 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 OLED.v(15) " "Net \"mem.data_a\" at OLED.v(15) has no driver or initial value, using a default initial value '0'" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 15 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646178110 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 OLED.v(15) " "Net \"mem.waddr_a\" at OLED.v(15) has no driver or initial value, using a default initial value '0'" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 15 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646178110 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "cmd.we_a 0 OLED.v(14) " "Net \"cmd.we_a\" at OLED.v(14) has no driver or initial value, using a default initial value '0'" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 14 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646178111 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 OLED.v(15) " "Net \"mem.we_a\" at OLED.v(15) has no driver or initial value, using a default initial value '0'" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 15 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646178111 "|pro_1|OLED:inst10"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "buzzer buzzer:inst13 " "Elaborating entity \"buzzer\" for hierarchy \"buzzer:inst13\"" {  } { { "pro_1.bdf" "inst13" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -128 -8368 -8184 16 "inst13" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646178111 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "flag_1 buzzer.v(17) " "Verilog HDL or VHDL warning at buzzer.v(17): object \"flag_1\" assigned a value but never read" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 17 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1611646178116 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "flag_2 buzzer.v(17) " "Verilog HDL or VHDL warning at buzzer.v(17): object \"flag_2\" assigned a value but never read" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 17 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1611646178116 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 buzzer.v(26) " "Verilog HDL assignment warning at buzzer.v(26): truncated value with size 32 to match size of target (6)" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 26 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178116 "|pro_1|buzzer:inst13"}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "buzzer.v(36) " "Verilog HDL Case Statement information at buzzer.v(36): all case item expressions in this case statement are onehot" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 36 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1611646178116 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 buzzer.v(66) " "Verilog HDL assignment warning at buzzer.v(66): truncated value with size 8 to match size of target (4)" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178116 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 buzzer.v(67) " "Verilog HDL assignment warning at buzzer.v(67): truncated value with size 32 to match size of target (6)" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 67 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178116 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "buzzer.v(91) " "Verilog HDL Case Statement warning at buzzer.v(91): case item expression never matches the case expression" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 91 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "Analysis & Synthesis" 0 -1 1611646178116 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "buzzer.v(92) " "Verilog HDL Case Statement warning at buzzer.v(92): case item expression never matches the case expression" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 92 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "Analysis & Synthesis" 0 -1 1611646178116 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "buzzer.v(93) " "Verilog HDL Case Statement warning at buzzer.v(93): case item expression never matches the case expression" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 93 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "Analysis & Synthesis" 0 -1 1611646178116 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "buzzer.v(94) " "Verilog HDL Case Statement warning at buzzer.v(94): case item expression never matches the case expression" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 94 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "Analysis & Synthesis" 0 -1 1611646178116 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "buzzer.v(95) " "Verilog HDL Case Statement warning at buzzer.v(95): case item expression never matches the case expression" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 95 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "Analysis & Synthesis" 0 -1 1611646178116 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "buzzer.v(96) " "Verilog HDL Case Statement warning at buzzer.v(96): case item expression never matches the case expression" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 96 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "Analysis & Synthesis" 0 -1 1611646178116 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 buzzer.v(107) " "Verilog HDL assignment warning at buzzer.v(107): truncated value with size 32 to match size of target (18)" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 107 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178116 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 buzzer.v(113) " "Verilog HDL assignment warning at buzzer.v(113): truncated value with size 32 to match size of target (24)" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 113 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178116 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "judge\[2\] 0 buzzer.v(18) " "Net \"judge\[2\]\" at buzzer.v(18) has no driver or initial value, using a default initial value '0'" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 18 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1611646178116 "|pro_1|buzzer:inst13"}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "TIMES times uart_rx.v(5) " "Verilog HDL Declaration information at uart_rx.v(5): object \"TIMES\" differs only in case from object \"times\" in the same scope" {  } { { "uart_rx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_rx.v" 5 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1611646178124 ""}
{ "Warning" "WSGN_SEARCH_FILE" "uart_rx.v 1 1 " "Using design file uart_rx.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 uart_rx " "Found entity 1: uart_rx" {  } { { "uart_rx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_rx.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646178125 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1611646178125 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_rx uart_rx:inst3 " "Elaborating entity \"uart_rx\" for hierarchy \"uart_rx:inst3\"" {  } { { "pro_1.bdf" "inst3" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -128 -8952 -8768 -48 "inst3" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646178125 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 uart_rx.v(37) " "Verilog HDL assignment warning at uart_rx.v(37): truncated value with size 32 to match size of target (11)" {  } { { "uart_rx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_rx.v" 37 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178130 "|pro_1|uart_rx:inst3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 uart_rx.v(38) " "Verilog HDL assignment warning at uart_rx.v(38): truncated value with size 32 to match size of target (11)" {  } { { "uart_rx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_rx.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178130 "|pro_1|uart_rx:inst3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 uart_rx.v(57) " "Verilog HDL assignment warning at uart_rx.v(57): truncated value with size 32 to match size of target (11)" {  } { { "uart_rx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_rx.v" 57 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178130 "|pro_1|uart_rx:inst3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 uart_rx.v(60) " "Verilog HDL assignment warning at uart_rx.v(60): truncated value with size 32 to match size of target (11)" {  } { { "uart_rx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_rx.v" 60 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178130 "|pro_1|uart_rx:inst3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 uart_rx.v(72) " "Verilog HDL assignment warning at uart_rx.v(72): truncated value with size 32 to match size of target (4)" {  } { { "uart_rx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_rx.v" 72 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178130 "|pro_1|uart_rx:inst3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 uart_rx.v(88) " "Verilog HDL assignment warning at uart_rx.v(88): truncated value with size 32 to match size of target (6)" {  } { { "uart_rx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_rx.v" 88 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178130 "|pro_1|uart_rx:inst3"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_buzzer clk_buzzer:inst11 " "Elaborating entity \"clk_buzzer\" for hierarchy \"clk_buzzer:inst11\"" {  } { { "pro_1.bdf" "inst11" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { 136 -9528 -9376 216 "inst11" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646178130 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 clk_buzzer.v(16) " "Verilog HDL assignment warning at clk_buzzer.v(16): truncated value with size 32 to match size of target (23)" {  } { { "clk_buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_buzzer.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178130 "|pro_1|clk_buzzer:inst11"}
{ "Warning" "WSGN_SEARCH_FILE" "trans.v 1 1 " "Using design file trans.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 trans " "Found entity 1: trans" {  } { { "trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646178139 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1611646178139 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "trans trans:inst5 " "Elaborating entity \"trans\" for hierarchy \"trans:inst5\"" {  } { { "pro_1.bdf" "inst5" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -400 -8856 -8640 -320 "inst5" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646178139 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 trans.v(7) " "Verilog HDL assignment warning at trans.v(7): truncated value with size 32 to match size of target (8)" {  } { { "trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 7 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178140 "|pro_1|trans:inst5"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 trans.v(8) " "Verilog HDL assignment warning at trans.v(8): truncated value with size 32 to match size of target (8)" {  } { { "trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 8 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1611646178140 "|pro_1|trans:inst5"}
{ "Critical Warning" "WCDB_CDB_LESS_INI_CONTENT" "16 10 C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram0_uart_tx_5cd61368.hdl.mif " "Memory depth (16) in the design file differs from memory depth (10) in the Memory Initialization File \"C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram0_uart_tx_5cd61368.hdl.mif\" -- setting initial value for remaining addresses to 0" {  } {  } 1 127005 "Memory depth (%1!d!) in the design file differs from memory depth (%2!d!) in the Memory Initialization File \"%3!s!\" -- setting initial value for remaining addresses to 0" 0 0 "Analysis & Synthesis" 0 -1 1611646179607 ""}
{ "Critical Warning" "WCDB_CDB_LESS_INI_CONTENT" "32 25 C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram0_OLED_2af399.hdl.mif " "Memory depth (32) in the design file differs from memory depth (25) in the Memory Initialization File \"C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram0_OLED_2af399.hdl.mif\" -- setting initial value for remaining addresses to 0" {  } {  } 1 127005 "Memory depth (%1!d!) in the design file differs from memory depth (%2!d!) in the Memory Initialization File \"%3!s!\" -- setting initial value for remaining addresses to 0" 0 0 "Analysis & Synthesis" 0 -1 1611646179615 ""}
{ "Critical Warning" "WCDB_CDB_LESS_INI_CONTENT" "128 124 C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram1_OLED_2af399.hdl.mif " "Memory depth (128) in the design file differs from memory depth (124) in the Memory Initialization File \"C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram1_OLED_2af399.hdl.mif\" -- setting initial value for remaining addresses to 0" {  } {  } 1 127005 "Memory depth (%1!d!) in the design file differs from memory depth (%2!d!) in the Memory Initialization File \"%3!s!\" -- setting initial value for remaining addresses to 0" 0 0 "Analysis & Synthesis" 0 -1 1611646179618 ""}
{ "Warning" "WCDB_CDB_RAM_MIF_CONTAIN_DONT_CARE" "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram1_OLED_2af399.hdl.mif " "Memory Initialization File or Hexadecimal (Intel-Format) File \"C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram1_OLED_2af399.hdl.mif\" contains \"don't care\" values -- overwriting them with 0s" {  } {  } 0 127007 "Memory Initialization File or Hexadecimal (Intel-Format) File \"%1!s!\" contains \"don't care\" values -- overwriting them with 0s" 0 0 "Analysis & Synthesis" 0 -1 1611646179621 ""}
{ "Info" "IINFER_UNINFERRED_RAM_SUMMARY" "3 " "Found 3 instances of uninferred RAM logic" { { "Info" "IINFER_MIF_NOT_SUPPORTED_FOR_HARDCOPY" "uart_tx:inst4\|tab " "RAM logic \"uart_tx:inst4\|tab\" is uninferred because MIF is not supported for the selected family" {  } { { "uart_tx.v" "tab" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/uart_tx.v" 9 -1 0 } }  } 0 276013 "RAM logic \"%1!s!\" is uninferred because MIF is not supported for the selected family" 0 0 "Design Software" 0 -1 1611646179672 ""} { "Info" "IINFER_MIF_NOT_SUPPORTED_FOR_HARDCOPY" "OLED:inst10\|cmd " "RAM logic \"OLED:inst10\|cmd\" is uninferred because MIF is not supported for the selected family" {  } { { "OLED.v" "cmd" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 14 -1 0 } }  } 0 276013 "RAM logic \"%1!s!\" is uninferred because MIF is not supported for the selected family" 0 0 "Design Software" 0 -1 1611646179672 ""} { "Info" "IINFER_MIF_NOT_SUPPORTED_FOR_HARDCOPY" "OLED:inst10\|mem " "RAM logic \"OLED:inst10\|mem\" is uninferred because MIF is not supported for the selected family" {  } { { "OLED.v" "mem" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 15 -1 0 } }  } 0 276013 "RAM logic \"%1!s!\" is uninferred because MIF is not supported for the selected family" 0 0 "Design Software" 0 -1 1611646179672 ""}  } {  } 0 276014 "Found %1!d! instances of uninferred RAM logic" 0 0 "Analysis & Synthesis" 0 -1 1611646179672 ""}
{ "Warning" "WCDB_CDB_RAM_MIF_CONTAIN_DONT_CARE" "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram1_OLED_2af399.hdl.mif " "Memory Initialization File or Hexadecimal (Intel-Format) File \"C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/pro_1.ram1_OLED_2af399.hdl.mif\" contains \"don't care\" values -- overwriting them with 0s" {  } {  } 0 127007 "Memory Initialization File or Hexadecimal (Intel-Format) File \"%1!s!\" contains \"don't care\" values -- overwriting them with 0s" 0 0 "Analysis & Synthesis" 0 -1 1611646179676 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "6 " "Inferred 6 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "tem_trans:inst9\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"tem_trans:inst9\|Mod0\"" {  } { { "tem_trans.v" "Mod0" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 15 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1611646181460 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "tem_trans:inst9\|Div1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"tem_trans:inst9\|Div1\"" {  } { { "tem_trans.v" "Div1" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 14 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1611646181460 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "trans:inst6\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"trans:inst6\|Div0\"" {  } { { "trans.v" "Div0" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 7 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1611646181460 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "trans:inst5\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"trans:inst5\|Div0\"" {  } { { "trans.v" "Div0" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 7 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1611646181460 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "trans:inst5\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"trans:inst5\|Mod0\"" {  } { { "trans.v" "Mod0" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 8 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1611646181460 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "trans:inst6\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"trans:inst6\|Mod0\"" {  } { { "trans.v" "Mod0" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 8 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1611646181460 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1611646181460 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "tem_trans:inst9\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"tem_trans:inst9\|lpm_divide:Mod0\"" {  } { { "tem_trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 15 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646181768 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tem_trans:inst9\|lpm_divide:Mod0 " "Instantiated megafunction \"tem_trans:inst9\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 21 " "Parameter \"LPM_WIDTHN\" = \"21\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646181770 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646181770 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646181770 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646181770 ""}  } { { "tem_trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 15 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1611646181770 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_nll.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_nll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_nll " "Found entity 1: lpm_divide_nll" {  } { { "db/lpm_divide_nll.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/lpm_divide_nll.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646181985 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646181985 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_mlh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_mlh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_mlh " "Found entity 1: sign_div_unsign_mlh" {  } { { "db/sign_div_unsign_mlh.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/sign_div_unsign_mlh.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646181998 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646181998 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_mhe.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_mhe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_mhe " "Found entity 1: alt_u_div_mhe" {  } { { "db/alt_u_div_mhe.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/alt_u_div_mhe.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646182018 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646182018 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_t3c.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_t3c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_t3c " "Found entity 1: add_sub_t3c" {  } { { "db/add_sub_t3c.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/add_sub_t3c.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646182088 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646182088 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_u3c.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_u3c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_u3c " "Found entity 1: add_sub_u3c" {  } { { "db/add_sub_u3c.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/add_sub_u3c.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646182125 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646182125 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "tem_trans:inst9\|lpm_divide:Div1 " "Elaborated megafunction instantiation \"tem_trans:inst9\|lpm_divide:Div1\"" {  } { { "tem_trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 14 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646182170 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tem_trans:inst9\|lpm_divide:Div1 " "Instantiated megafunction \"tem_trans:inst9\|lpm_divide:Div1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 21 " "Parameter \"LPM_WIDTHN\" = \"21\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646182170 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646182170 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646182170 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646182170 ""}  } { { "tem_trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/tem_trans.v" 14 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1611646182170 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ktl.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_ktl.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ktl " "Found entity 1: lpm_divide_ktl" {  } { { "db/lpm_divide_ktl.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/lpm_divide_ktl.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646182204 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646182204 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "trans:inst6\|lpm_divide:Div0 " "Elaborated megafunction instantiation \"trans:inst6\|lpm_divide:Div0\"" {  } { { "trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 7 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646182214 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "trans:inst6\|lpm_divide:Div0 " "Instantiated megafunction \"trans:inst6\|lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 7 " "Parameter \"LPM_WIDTHN\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646182214 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646182214 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646182214 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646182214 ""}  } { { "trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 7 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1611646182214 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_8sl.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_8sl.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_8sl " "Found entity 1: lpm_divide_8sl" {  } { { "db/lpm_divide_8sl.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/lpm_divide_8sl.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646182249 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646182249 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_akh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_akh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_akh " "Found entity 1: sign_div_unsign_akh" {  } { { "db/sign_div_unsign_akh.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/sign_div_unsign_akh.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646182260 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646182260 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_uee.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_uee.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_uee " "Found entity 1: alt_u_div_uee" {  } { { "db/alt_u_div_uee.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/alt_u_div_uee.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646182267 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646182267 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "trans:inst5\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"trans:inst5\|lpm_divide:Mod0\"" {  } { { "trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 8 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646182289 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "trans:inst5\|lpm_divide:Mod0 " "Instantiated megafunction \"trans:inst5\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 7 " "Parameter \"LPM_WIDTHN\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646182289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646182289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646182289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1611646182289 ""}  } { { "trans.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/trans.v" 8 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1611646182289 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_bkl.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_bkl.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_bkl " "Found entity 1: lpm_divide_bkl" {  } { { "db/lpm_divide_bkl.tdf" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/lpm_divide_bkl.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1611646182324 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646182324 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 4 -1 0 } } { "OLED.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/OLED.v" 55 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1611646183001 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1611646183001 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1611646184820 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "9 " "9 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1611646188932 ""}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "tem_trans:inst9\|lpm_divide:Div1\|lpm_divide_ktl:auto_generated\|sign_div_unsign_mlh:divider\|alt_u_div_mhe:divider\|add_sub_17_result_int\[0\]~10 " "Logic cell \"tem_trans:inst9\|lpm_divide:Div1\|lpm_divide_ktl:auto_generated\|sign_div_unsign_mlh:divider\|alt_u_div_mhe:divider\|add_sub_17_result_int\[0\]~10\"" {  } { { "db/alt_u_div_mhe.tdf" "add_sub_17_result_int\[0\]~10" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/db/alt_u_div_mhe.tdf" 72 23 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1611646189114 ""}  } {  } 0 17016 "Found the following redundant logic cells in design" 0 0 "Analysis & Synthesis" 0 -1 1611646189114 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/output_files/pro_1.map.smsg " "Generated suppressed messages file C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/output_files/pro_1.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646189330 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1611646189743 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1611646189743 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "2232 " "Implemented 2232 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1611646190582 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1611646190582 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "1 " "Implemented 1 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1611646190582 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2218 " "Implemented 2218 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1611646190582 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1611646190582 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 65 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 65 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4840 " "Peak virtual memory: 4840 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611646190608 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 26 15:29:50 2021 " "Processing ended: Tue Jan 26 15:29:50 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611646190608 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:25 " "Elapsed time: 00:00:25" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611646190608 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Total CPU time (on all processors): 00:00:27" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611646190608 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1611646190608 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1611646196385 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611646196395 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 26 15:29:54 2021 " "Processing started: Tue Jan 26 15:29:54 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611646196395 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1611646196395 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off pro_1 -c pro_1 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off pro_1 -c pro_1" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1611646196395 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1611646197623 ""}
{ "Info" "0" "" "Project  = pro_1" {  } {  } 0 0 "Project  = pro_1" 0 0 "Fitter" 0 0 1611646197633 ""}
{ "Info" "0" "" "Revision = pro_1" {  } {  } 0 0 "Revision = pro_1" 0 0 "Fitter" 0 0 1611646197634 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1611646197782 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1611646197783 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "pro_1 10M02SCM153C8G " "Selected device 10M02SCM153C8G for design \"pro_1\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1611646197845 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1611646197973 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1611646197973 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1611646198420 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1611646198467 ""}
{ "Critical Warning" "WFCUDA_FCUDA_SPS_DEVICE_POWER_LIMITATION" "" "Review the Power Analyzer report file (<design>.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures." {  } {  } 1 16562 "Review the Power Analyzer report file (<design>.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures." 0 0 "Fitter" 0 -1 1611646199239 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08SCM153C8G " "Device 10M08SCM153C8G is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611646199257 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M04SCM153C8G " "Device 10M04SCM153C8G is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1611646199257 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1611646199257 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ G1 " "Pin ~ALTERA_TMS~ is reserved at location G1" {  } { { "d:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 4099 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611646199363 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ J1 " "Pin ~ALTERA_TCK~ is reserved at location J1" {  } { { "d:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 4101 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611646199363 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ H5 " "Pin ~ALTERA_TDI~ is reserved at location H5" {  } { { "d:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 4103 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611646199363 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ H4 " "Pin ~ALTERA_TDO~ is reserved at location H4" {  } { { "d:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 4105 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611646199363 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ D8 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location D8" {  } { { "d:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 4107 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611646199363 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ E8 " "Pin ~ALTERA_nCONFIG~ is reserved at location E8" {  } { { "d:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 4109 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611646199363 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ D6 " "Pin ~ALTERA_nSTATUS~ is reserved at location D6" {  } { { "d:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 4111 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611646199363 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ E6 " "Pin ~ALTERA_CONF_DONE~ is reserved at location E6" {  } { { "d:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 4113 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1611646199363 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1611646199363 ""}
{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" {  } {  } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611646199367 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" {  } {  } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611646199367 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" {  } {  } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611646199367 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" {  } {  } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1611646199367 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1611646199388 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "pro_1.sdc " "Synopsys Design Constraints File file not found: 'pro_1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1611646200719 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1611646200722 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1611646200743 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1611646200748 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1611646200752 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN J5 (CLK0p, DIFFIO_RX_L14p, DIFFOUT_L14p, High_Speed)) " "Automatically promoted node clk~input (placed in PIN J5 (CLK0p, DIFFIO_RX_L14p, DIFFOUT_L14p, High_Speed))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1611646200945 ""}  } { { "pro_1.bdf" "" { Schematic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/pro_1.bdf" { { -280 -9744 -9576 -264 "clk" "" } } } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 4090 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1611646200945 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_buzzer:inst11\|clk_out  " "Automatically promoted node clk_buzzer:inst11\|clk_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1611646200945 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_buzzer:inst11\|clk_out~0 " "Destination node clk_buzzer:inst11\|clk_out~0" {  } { { "clk_buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_buzzer.v" 3 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 2665 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1611646200945 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1611646200945 ""}  } { { "clk_buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_buzzer.v" 3 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 91 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1611646200945 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_1MHz:inst7\|clk_1MHz  " "Automatically promoted node clk_1MHz:inst7\|clk_1MHz " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1611646200946 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_1MHz:inst7\|clk_1MHz~0 " "Destination node clk_1MHz:inst7\|clk_1MHz~0" {  } { { "clk_1MHz.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_1MHz.v" 3 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 3251 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1611646200946 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1611646200946 ""}  } { { "clk_1MHz.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_1MHz.v" 3 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 819 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1611646200946 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_second:inst\|clk_1ms  " "Automatically promoted node clk_second:inst\|clk_1ms " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1611646200946 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_second:inst\|clk_1ms~0 " "Destination node clk_second:inst\|clk_1ms~0" {  } { { "clk_second.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_second.v" 3 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 3249 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1611646200946 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1611646200946 ""}  } { { "clk_second.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_second.v" 3 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 1046 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1611646200946 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clock:inst1\|t_i_u  " "Automatically promoted node clock:inst1\|t_i_u " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1611646200946 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "buzzer:inst13\|judge\[0\] " "Destination node buzzer:inst13\|judge\[0\]" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 109 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 325 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1611646200946 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "buzzer:inst13\|Equal5~0 " "Destination node buzzer:inst13\|Equal5~0" {  } { { "buzzer.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/buzzer.v" 119 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 3841 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1611646200946 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1611646200946 ""}  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 4 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 1118 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1611646200946 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_second:inst\|clk_500ms  " "Automatically promoted node clk_second:inst\|clk_500ms " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1611646200946 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_second:inst\|clk_500ms~0 " "Destination node clk_second:inst\|clk_500ms~0" {  } { { "clk_second.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_second.v" 3 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 3639 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1611646200946 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1611646200946 ""}  } { { "clk_second.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_second.v" 3 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 1043 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1611646200946 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_uart_tx:inst2\|clk_out  " "Automatically promoted node clk_uart_tx:inst2\|clk_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1611646200946 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_uart_tx:inst2\|clk_out~0 " "Destination node clk_uart_tx:inst2\|clk_out~0" {  } { { "clk_uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_uart_tx.v" 3 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 1808 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1611646200946 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1611646200946 ""}  } { { "clk_uart_tx.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clk_uart_tx.v" 3 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 1130 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1611646200946 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset:inst12\|rst~0  " "Automatically promoted node reset:inst12\|rst~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1611646200947 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "temperature:inst8\|bus_output " "Destination node temperature:inst8\|bus_output" {  } { { "temperature.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/temperature.v" 13 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 933 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1611646200947 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "temperature:inst8\|data_out\[0\]~1 " "Destination node temperature:inst8\|data_out\[0\]~1" {  } { { "temperature.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/temperature.v" 51 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 2569 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1611646200947 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clock:inst1\|Equal1~0 " "Destination node clock:inst1\|Equal1~0" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 56 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 3169 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1611646200947 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clock:inst1\|min_set~16 " "Destination node clock:inst1\|min_set~16" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 3179 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1611646200947 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clock:inst1\|min_set~19 " "Destination node clock:inst1\|min_set~19" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 3184 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1611646200947 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clock:inst1\|LessThan0~1 " "Destination node clock:inst1\|LessThan0~1" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 54 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 3230 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1611646200947 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clock:inst1\|min_set~21 " "Destination node clock:inst1\|min_set~21" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 3234 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1611646200947 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clock:inst1\|hour_set~13 " "Destination node clock:inst1\|hour_set~13" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 3237 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1611646200947 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clock:inst1\|hour_set~14 " "Destination node clock:inst1\|hour_set~14" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 3238 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1611646200947 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clock:inst1\|hour_set~15 " "Destination node clock:inst1\|hour_set~15" {  } { { "clock.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/clock.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 3239 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1611646200947 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" {  } {  } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Design Software" 0 -1 1611646200947 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1611646200947 ""}  } { { "reset.v" "" { Text "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/reset.v" 3 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 0 { 0 ""} 0 2568 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1611646200947 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1611646201500 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1611646201502 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1611646201502 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1611646201505 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1611646201508 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1611646201512 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1611646201512 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1611646201513 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1611646201627 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1611646201629 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1611646201629 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611646201722 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." {  } {  } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1611646201872 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1611646202593 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611646203134 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1611646203218 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1611646205962 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611646205962 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1611646206661 ""}
{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "2e+02 ns 2.3% " "2e+02 ns of routing delay (approximately 2.3% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." {  } {  } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1611646207728 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "11 " "Router estimated average interconnect usage is 11% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X9_Y0 X18_Y8 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X9_Y0 to location X18_Y8" {  } { { "loc" "" { Generic "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X9_Y0 to location X18_Y8"} { { 12 { 0 ""} 9 0 10 9 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1611646208176 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1611646208176 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1611646211394 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1611646211394 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:05 " "Fitter routing operations ending: elapsed time is 00:00:05" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611646211397 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 1.94 " "Total time spent on timing analysis during the Fitter is 1.94 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1611646211663 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1611646211729 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1611646212345 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1611646212346 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1611646213174 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611646213879 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/output_files/pro_1.fit.smsg " "Generated suppressed messages file C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/output_files/pro_1.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1611646214333 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5717 " "Peak virtual memory: 5717 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611646215130 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 26 15:30:15 2021 " "Processing ended: Tue Jan 26 15:30:15 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611646215130 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:21 " "Elapsed time: 00:00:21" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611646215130 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611646215130 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1611646215130 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1611646218713 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611646218724 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 26 15:30:18 2021 " "Processing started: Tue Jan 26 15:30:18 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611646218724 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1611646218724 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off pro_1 -c pro_1 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off pro_1 -c pro_1" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1611646218724 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1611646219434 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1611646219968 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1611646219992 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4694 " "Peak virtual memory: 4694 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611646220486 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 26 15:30:20 2021 " "Processing ended: Tue Jan 26 15:30:20 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611646220486 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611646220486 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611646220486 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1611646220486 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1611646227209 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Power Analyzer Quartus Prime " "Running Quartus Prime Power Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611646227220 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 26 15:30:27 2021 " "Processing started: Tue Jan 26 15:30:27 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611646227220 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Power Analyzer" 0 -1 1611646227220 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_pow --read_settings_files=off --write_settings_files=off pro_1 -c pro_1 " "Command: quartus_pow --read_settings_files=off --write_settings_files=off pro_1 -c pro_1" {  } {  } 0 0 "Command: %1!s!" 0 0 "Power Analyzer" 0 -1 1611646227220 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Power Analyzer" 0 -1 1611646228005 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1611646228128 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1611646228128 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "pro_1.sdc " "Synopsys Design Constraints File file not found: 'pro_1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Power Analyzer" 0 -1 1611646228593 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk " "Node: clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register OLED:inst10\|oled_dat clk " "Register OLED:inst10\|oled_dat is being clocked by clk" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1611646228613 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1611646228613 "|pro_1|clk"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_buzzer:inst11\|clk_out " "Node: clk_buzzer:inst11\|clk_out was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register buzzer:inst13\|stop clk_buzzer:inst11\|clk_out " "Register buzzer:inst13\|stop is being clocked by clk_buzzer:inst11\|clk_out" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1611646228614 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1611646228614 "|pro_1|clk_buzzer:inst11|clk_out"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_second:inst\|clk_1ms " "Node: clk_second:inst\|clk_1ms was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register clock:inst1\|t_i_u clk_second:inst\|clk_1ms " "Register clock:inst1\|t_i_u is being clocked by clk_second:inst\|clk_1ms" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1611646228614 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1611646228614 "|pro_1|clk_second:inst|clk_1ms"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_second:inst\|clk_500ms " "Node: clk_second:inst\|clk_500ms was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register clock:inst1\|hour_set\[2\] clk_second:inst\|clk_500ms " "Register clock:inst1\|hour_set\[2\] is being clocked by clk_second:inst\|clk_500ms" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1611646228614 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1611646228614 "|pro_1|clk_second:inst|clk_500ms"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_1MHz:inst7\|clk_1MHz " "Node: clk_1MHz:inst7\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register temperature:inst8\|data_out\[0\] clk_1MHz:inst7\|clk_1MHz " "Register temperature:inst8\|data_out\[0\] is being clocked by clk_1MHz:inst7\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1611646228614 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1611646228614 "|pro_1|clk_1MHz:inst7|clk_1MHz"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_uart_tx:inst2\|clk_out " "Node: clk_uart_tx:inst2\|clk_out was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register uart_tx:inst4\|i\[0\] clk_uart_tx:inst2\|clk_out " "Register uart_tx:inst4\|i\[0\] is being clocked by clk_uart_tx:inst2\|clk_out" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1611646228614 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1611646228614 "|pro_1|clk_uart_tx:inst2|clk_out"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clock:inst1\|t_i_u " "Node: clock:inst1\|t_i_u was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register uart_tx:inst4\|flag_1 clock:inst1\|t_i_u " "Register uart_tx:inst4\|flag_1 is being clocked by clock:inst1\|t_i_u" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1611646228614 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1611646228614 "|pro_1|clock:inst1|t_i_u"}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Power Analyzer" 0 -1 1611646228615 ""}
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" {  } {  } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1611646228655 ""}
{ "Warning" "WPUTIL_PUTIL_NO_CLK_DOMAINS_FOUND" "" "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" {  } {  } 0 222013 "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" 0 0 "Power Analyzer" 0 -1 1611646228707 ""}
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" {  } {  } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1611646228727 ""}
{ "Info" "IPATFAM_USING_ADVANCED_IO_POWER" "" "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" {  } {  } 0 218000 "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" 0 0 "Power Analyzer" 0 -1 1611646229041 ""}
{ "Warning" "WPAN_PAN_NO_THERMAL_MODEL_SELECTED" "" "No board thermal model was selected.  Analyzing without board thermal modeling." {  } {  } 0 215044 "No board thermal model was selected.  Analyzing without board thermal modeling." 0 0 "Power Analyzer" 0 -1 1611646229044 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Power Analyzer" 0 -1 1611646229115 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Power Analyzer" 0 -1 1611646229886 ""}
{ "Info" "IPAN_AVG_TOGGLE_RATE_PER_DESIGN" "0.000 millions of transitions / sec " "Average toggle rate for this design is 0.000 millions of transitions / sec" {  } {  } 0 215049 "Average toggle rate for this design is %1!s!" 0 0 "Power Analyzer" 0 -1 1611646230469 ""}
{ "Info" "IPAN_PAN_TOTAL_POWER_ESTIMATION" "72.29 mW " "Total thermal power estimate for the design is 72.29 mW" {  } { { "d:/intelfpga_lite/19.1/quartus/bin64/Report_Window_01.qrpt" "" { Report "d:/intelfpga_lite/19.1/quartus/bin64/Report_Window_01.qrpt" "Compiler" "" "" "" "" { } "PowerPlay Power Analyzer Summary" } }  } 0 215031 "Total thermal power estimate for the design is %1!s!" 0 0 "Power Analyzer" 0 -1 1611646230656 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Power Analyzer 0 s 12 s Quartus Prime " "Quartus Prime Power Analyzer was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4876 " "Peak virtual memory: 4876 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611646230856 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 26 15:30:30 2021 " "Processing ended: Tue Jan 26 15:30:30 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611646230856 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611646230856 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611646230856 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Power Analyzer" 0 -1 1611646230856 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Power Analyzer" 0 -1 1611646237986 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611646237996 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 26 15:30:37 2021 " "Processing started: Tue Jan 26 15:30:37 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611646237996 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1611646237996 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta pro_1 -c pro_1 " "Command: quartus_sta pro_1 -c pro_1" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1611646237996 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1611646238831 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1611646239124 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1611646239124 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1611646239161 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1611646239161 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "pro_1.sdc " "Synopsys Design Constraints File file not found: 'pro_1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1611646239370 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1611646239370 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1611646239375 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk_buzzer:inst11\|clk_out clk_buzzer:inst11\|clk_out " "create_clock -period 1.000 -name clk_buzzer:inst11\|clk_out clk_buzzer:inst11\|clk_out" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1611646239375 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk_second:inst\|clk_1ms clk_second:inst\|clk_1ms " "create_clock -period 1.000 -name clk_second:inst\|clk_1ms clk_second:inst\|clk_1ms" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1611646239375 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk_second:inst\|clk_500ms clk_second:inst\|clk_500ms " "create_clock -period 1.000 -name clk_second:inst\|clk_500ms clk_second:inst\|clk_500ms" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1611646239375 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk_1MHz:inst7\|clk_1MHz clk_1MHz:inst7\|clk_1MHz " "create_clock -period 1.000 -name clk_1MHz:inst7\|clk_1MHz clk_1MHz:inst7\|clk_1MHz" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1611646239375 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk_uart_tx:inst2\|clk_out clk_uart_tx:inst2\|clk_out " "create_clock -period 1.000 -name clk_uart_tx:inst2\|clk_out clk_uart_tx:inst2\|clk_out" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1611646239375 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clock:inst1\|t_i_u clock:inst1\|t_i_u " "create_clock -period 1.000 -name clock:inst1\|t_i_u clock:inst1\|t_i_u" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1611646239375 ""}  } {  } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1611646239375 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1611646239386 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1611646239388 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1611646239399 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1611646239445 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." {  } {  } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1611646239464 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1611646239474 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -21.557 " "Worst-case setup slack is -21.557" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239477 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239477 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -21.557            -242.460 clock:inst1\|t_i_u  " "  -21.557            -242.460 clock:inst1\|t_i_u " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239477 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -21.523           -2047.323 clk  " "  -21.523           -2047.323 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239477 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -6.082            -421.117 clk_1MHz:inst7\|clk_1MHz  " "   -6.082            -421.117 clk_1MHz:inst7\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239477 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.863             -51.442 clk_second:inst\|clk_500ms  " "   -4.863             -51.442 clk_second:inst\|clk_500ms " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239477 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.706            -268.000 clk_buzzer:inst11\|clk_out  " "   -4.706            -268.000 clk_buzzer:inst11\|clk_out " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239477 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.555            -161.241 clk_second:inst\|clk_1ms  " "   -4.555            -161.241 clk_second:inst\|clk_1ms " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239477 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.160             -20.498 clk_uart_tx:inst2\|clk_out  " "   -4.160             -20.498 clk_uart_tx:inst2\|clk_out " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239477 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1611646239477 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.344 " "Worst-case hold slack is 0.344" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239489 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239489 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.344               0.000 clk  " "    0.344               0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239489 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.344               0.000 clk_1MHz:inst7\|clk_1MHz  " "    0.344               0.000 clk_1MHz:inst7\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239489 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.364               0.000 clk_buzzer:inst11\|clk_out  " "    0.364               0.000 clk_buzzer:inst11\|clk_out " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239489 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.366               0.000 clk_uart_tx:inst2\|clk_out  " "    0.366               0.000 clk_uart_tx:inst2\|clk_out " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239489 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.383               0.000 clock:inst1\|t_i_u  " "    0.383               0.000 clock:inst1\|t_i_u " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239489 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.696               0.000 clk_second:inst\|clk_1ms  " "    0.696               0.000 clk_second:inst\|clk_1ms " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239489 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.091               0.000 clk_second:inst\|clk_500ms  " "    1.091               0.000 clk_second:inst\|clk_500ms " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239489 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1611646239489 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -2.969 " "Worst-case recovery slack is -2.969" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239498 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239498 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.969            -248.340 clk  " "   -2.969            -248.340 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239498 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1611646239498 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.129 " "Worst-case removal slack is 2.129" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239506 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239506 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.129               0.000 clk  " "    2.129               0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239506 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1611646239506 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000            -590.365 clk  " "   -3.000            -590.365 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487            -194.797 clk_buzzer:inst11\|clk_out  " "   -1.487            -194.797 clk_buzzer:inst11\|clk_out " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487            -159.109 clk_1MHz:inst7\|clk_1MHz  " "   -1.487            -159.109 clk_1MHz:inst7\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487             -62.454 clk_second:inst\|clk_1ms  " "   -1.487             -62.454 clk_second:inst\|clk_1ms " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487             -20.818 clock:inst1\|t_i_u  " "   -1.487             -20.818 clock:inst1\|t_i_u " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487             -16.357 clk_second:inst\|clk_500ms  " "   -1.487             -16.357 clk_second:inst\|clk_500ms " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487             -13.383 clk_uart_tx:inst2\|clk_out  " "   -1.487             -13.383 clk_uart_tx:inst2\|clk_out " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646239514 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1611646239514 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1611646239540 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1611646239580 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1611646240440 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1611646240613 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1611646240634 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -20.061 " "Worst-case setup slack is -20.061" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -20.061            -225.087 clock:inst1\|t_i_u  " "  -20.061            -225.087 clock:inst1\|t_i_u " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -19.989           -1898.210 clk  " "  -19.989           -1898.210 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -5.705            -394.730 clk_1MHz:inst7\|clk_1MHz  " "   -5.705            -394.730 clk_1MHz:inst7\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.553             -48.255 clk_second:inst\|clk_500ms  " "   -4.553             -48.255 clk_second:inst\|clk_500ms " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.496            -250.630 clk_buzzer:inst11\|clk_out  " "   -4.496            -250.630 clk_buzzer:inst11\|clk_out " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.322            -151.576 clk_second:inst\|clk_1ms  " "   -4.322            -151.576 clk_second:inst\|clk_1ms " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.804             -18.977 clk_uart_tx:inst2\|clk_out  " "   -3.804             -18.977 clk_uart_tx:inst2\|clk_out " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240637 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1611646240637 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.306 " "Worst-case hold slack is 0.306" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.306               0.000 clk  " "    0.306               0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.306               0.000 clk_1MHz:inst7\|clk_1MHz  " "    0.306               0.000 clk_1MHz:inst7\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.325               0.000 clk_buzzer:inst11\|clk_out  " "    0.325               0.000 clk_buzzer:inst11\|clk_out " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.327               0.000 clk_uart_tx:inst2\|clk_out  " "    0.327               0.000 clk_uart_tx:inst2\|clk_out " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.342               0.000 clock:inst1\|t_i_u  " "    0.342               0.000 clock:inst1\|t_i_u " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.655               0.000 clk_second:inst\|clk_1ms  " "    0.655               0.000 clk_second:inst\|clk_1ms " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.037               0.000 clk_second:inst\|clk_500ms  " "    1.037               0.000 clk_second:inst\|clk_500ms " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240648 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1611646240648 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -2.783 " "Worst-case recovery slack is -2.783" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.783            -231.282 clk  " "   -2.783            -231.282 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240657 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1611646240657 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.974 " "Worst-case removal slack is 1.974" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240664 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240665 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.974               0.000 clk  " "    1.974               0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240665 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1611646240664 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000            -590.365 clk  " "   -3.000            -590.365 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487            -194.797 clk_buzzer:inst11\|clk_out  " "   -1.487            -194.797 clk_buzzer:inst11\|clk_out " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487            -159.109 clk_1MHz:inst7\|clk_1MHz  " "   -1.487            -159.109 clk_1MHz:inst7\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487             -62.454 clk_second:inst\|clk_1ms  " "   -1.487             -62.454 clk_second:inst\|clk_1ms " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487             -20.818 clock:inst1\|t_i_u  " "   -1.487             -20.818 clock:inst1\|t_i_u " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487             -16.357 clk_second:inst\|clk_500ms  " "   -1.487             -16.357 clk_second:inst\|clk_500ms " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487             -13.383 clk_uart_tx:inst2\|clk_out  " "   -1.487             -13.383 clk_uart_tx:inst2\|clk_out " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240673 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1611646240673 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1611646240696 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1611646240889 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1611646240897 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -7.433 " "Worst-case setup slack is -7.433" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240901 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240901 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -7.433             -82.670 clock:inst1\|t_i_u  " "   -7.433             -82.670 clock:inst1\|t_i_u " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240901 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -7.310            -555.361 clk  " "   -7.310            -555.361 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240901 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.773            -107.436 clk_1MHz:inst7\|clk_1MHz  " "   -1.773            -107.436 clk_1MHz:inst7\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240901 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.413             -46.845 clk_buzzer:inst11\|clk_out  " "   -1.413             -46.845 clk_buzzer:inst11\|clk_out " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240901 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.282             -41.822 clk_second:inst\|clk_1ms  " "   -1.282             -41.822 clk_second:inst\|clk_1ms " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240901 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.196             -12.547 clk_second:inst\|clk_500ms  " "   -1.196             -12.547 clk_second:inst\|clk_500ms " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240901 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.978              -3.812 clk_uart_tx:inst2\|clk_out  " "   -0.978              -3.812 clk_uart_tx:inst2\|clk_out " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240901 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1611646240901 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.145 " "Worst-case hold slack is 0.145" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240912 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240912 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.145               0.000 clk  " "    0.145               0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240912 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.145               0.000 clk_1MHz:inst7\|clk_1MHz  " "    0.145               0.000 clk_1MHz:inst7\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240912 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.152               0.000 clk_buzzer:inst11\|clk_out  " "    0.152               0.000 clk_buzzer:inst11\|clk_out " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240912 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.153               0.000 clk_uart_tx:inst2\|clk_out  " "    0.153               0.000 clk_uart_tx:inst2\|clk_out " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240912 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.157               0.000 clock:inst1\|t_i_u  " "    0.157               0.000 clock:inst1\|t_i_u " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240912 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.237               0.000 clk_second:inst\|clk_1ms  " "    0.237               0.000 clk_second:inst\|clk_1ms " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240912 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.366               0.000 clk_second:inst\|clk_500ms  " "    0.366               0.000 clk_second:inst\|clk_500ms " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240912 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1611646240912 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -0.809 " "Worst-case recovery slack is -0.809" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240921 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240921 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.809             -50.928 clk  " "   -0.809             -50.928 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240921 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1611646240921 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.829 " "Worst-case removal slack is 0.829" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.829               0.000 clk  " "    0.829               0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240929 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1611646240929 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240938 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240938 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000            -412.267 clk  " "   -3.000            -412.267 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240938 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000            -131.000 clk_buzzer:inst11\|clk_out  " "   -1.000            -131.000 clk_buzzer:inst11\|clk_out " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240938 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000            -107.000 clk_1MHz:inst7\|clk_1MHz  " "   -1.000            -107.000 clk_1MHz:inst7\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240938 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000             -42.000 clk_second:inst\|clk_1ms  " "   -1.000             -42.000 clk_second:inst\|clk_1ms " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240938 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000             -14.000 clock:inst1\|t_i_u  " "   -1.000             -14.000 clock:inst1\|t_i_u " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240938 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000             -11.000 clk_second:inst\|clk_500ms  " "   -1.000             -11.000 clk_second:inst\|clk_500ms " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240938 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -9.000 clk_uart_tx:inst2\|clk_out  " "   -1.000              -9.000 clk_uart_tx:inst2\|clk_out " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1611646240938 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1611646240938 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1611646241721 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1611646241722 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4840 " "Peak virtual memory: 4840 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611646241801 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 26 15:30:41 2021 " "Processing ended: Tue Jan 26 15:30:41 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611646241801 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611646241801 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611646241801 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1611646241801 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1611646245999 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611646246010 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 26 15:30:45 2021 " "Processing started: Tue Jan 26 15:30:45 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611646246010 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1611646246010 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off pro_1 -c pro_1 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off pro_1 -c pro_1" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1611646246010 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1611646246723 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "pro_1.vo C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/simulation/modelsim/ simulation " "Generated file pro_1.vo in folder \"C:/Users/Dell/Desktop/FPGA_2020WINTER/project_2020winter/pro_1_19.1/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1611646247457 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4657 " "Peak virtual memory: 4657 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611646247497 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 26 15:30:47 2021 " "Processing ended: Tue Jan 26 15:30:47 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611646247497 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611646247497 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611646247497 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1611646247497 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 89 s " "Quartus Prime Full Compilation was successful. 0 errors, 89 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1611646248200 ""}
