{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1614090621105 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1614090621113 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 23 22:30:20 2021 " "Processing started: Tue Feb 23 22:30:20 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1614090621113 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090621113 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mission -c mission " "Command: quartus_map --read_settings_files=on --write_settings_files=off mission -c mission" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090621113 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1614090621540 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1614090621540 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mission.v 1 1 " "Found 1 design units, including 1 entities, in source file mission.v" { { "Info" "ISGN_ENTITY_NAME" "1 mission " "Found entity 1: mission" {  } { { "mission.v" "" { Text "C:/FPGA/my_project/mission/mission.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090630845 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090630845 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "temperature.v 1 1 " "Found 1 design units, including 1 entities, in source file temperature.v" { { "Info" "ISGN_ENTITY_NAME" "1 temperature " "Found entity 1: temperature" {  } { { "temperature.v" "" { Text "C:/FPGA/my_project/mission/temperature.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090630848 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090630848 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "clock.v(15) " "Verilog HDL information at clock.v(15): always construct contains both blocking and non-blocking assignments" {  } { { "clock.v" "" { Text "C:/FPGA/my_project/mission/clock.v" 15 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1614090630851 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.v 1 1 " "Found 1 design units, including 1 entities, in source file clock.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Found entity 1: clock" {  } { { "clock.v" "" { Text "C:/FPGA/my_project/mission/clock.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090630852 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090630852 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "div_rill.v(32) " "Verilog HDL information at div_rill.v(32): always construct contains both blocking and non-blocking assignments" {  } { { "div_rill.v" "" { Text "C:/FPGA/my_project/mission/div_rill.v" 32 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1614090630854 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div_rill.v 1 1 " "Found 1 design units, including 1 entities, in source file div_rill.v" { { "Info" "ISGN_ENTITY_NAME" "1 div_rill " "Found entity 1: div_rill" {  } { { "div_rill.v" "" { Text "C:/FPGA/my_project/mission/div_rill.v" 10 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090630855 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090630855 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "mission " "Elaborating entity \"mission\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1614090630932 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 mission.v(109) " "Verilog HDL assignment warning at mission.v(109): truncated value with size 32 to match size of target (1)" {  } { { "mission.v" "" { Text "C:/FPGA/my_project/mission/mission.v" 109 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630933 "|mission"}
{ "Warning" "WSGN_SEARCH_FILE" "debounce.v 1 1 " "Using design file debounce.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Debounce " "Found entity 1: Debounce" {  } { { "debounce.v" "" { Text "C:/FPGA/my_project/mission/debounce.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090630945 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1614090630945 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Debounce Debounce:Debounce1 " "Elaborating entity \"Debounce\" for hierarchy \"Debounce:Debounce1\"" {  } { { "mission.v" "Debounce1" { Text "C:/FPGA/my_project/mission/mission.v" 38 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614090630946 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 debounce.v(32) " "Verilog HDL assignment warning at debounce.v(32): truncated value with size 32 to match size of target (1)" {  } { { "debounce.v" "" { Text "C:/FPGA/my_project/mission/debounce.v" 32 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630948 "|mission|Debounce:Debounce1"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock clock:clock1 " "Elaborating entity \"clock\" for hierarchy \"clock:clock1\"" {  } { { "mission.v" "clock1" { Text "C:/FPGA/my_project/mission/mission.v" 58 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614090630950 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 25 clock.v(29) " "Verilog HDL assignment warning at clock.v(29): truncated value with size 32 to match size of target (25)" {  } { { "clock.v" "" { Text "C:/FPGA/my_project/mission/clock.v" 29 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630951 "|mission|clock:clock1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(33) " "Verilog HDL assignment warning at clock.v(33): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "C:/FPGA/my_project/mission/clock.v" 33 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630951 "|mission|clock:clock1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(38) " "Verilog HDL assignment warning at clock.v(38): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "C:/FPGA/my_project/mission/clock.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630951 "|mission|clock:clock1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(42) " "Verilog HDL assignment warning at clock.v(42): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "C:/FPGA/my_project/mission/clock.v" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630951 "|mission|clock:clock1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(47) " "Verilog HDL assignment warning at clock.v(47): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "C:/FPGA/my_project/mission/clock.v" 47 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630951 "|mission|clock:clock1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(52) " "Verilog HDL assignment warning at clock.v(52): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "C:/FPGA/my_project/mission/clock.v" 52 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630951 "|mission|clock:clock1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(57) " "Verilog HDL assignment warning at clock.v(57): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "C:/FPGA/my_project/mission/clock.v" 57 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630951 "|mission|clock:clock1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 25 clock.v(66) " "Verilog HDL assignment warning at clock.v(66): truncated value with size 32 to match size of target (25)" {  } { { "clock.v" "" { Text "C:/FPGA/my_project/mission/clock.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630952 "|mission|clock:clock1"}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "uart_seg.v(88) " "Verilog HDL information at uart_seg.v(88): always construct contains both blocking and non-blocking assignments" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 88 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1614090630965 ""}
{ "Warning" "WSGN_SEARCH_FILE" "uart_seg.v 1 1 " "Using design file uart_seg.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 uart_seg " "Found entity 1: uart_seg" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090630966 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1614090630966 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_seg uart_seg:uart_seg1 " "Elaborating entity \"uart_seg\" for hierarchy \"uart_seg:uart_seg1\"" {  } { { "mission.v" "uart_seg1" { Text "C:/FPGA/my_project/mission/mission.v" 70 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614090630967 ""}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "send uart_seg.v(45) " "Verilog HDL Always Construct warning at uart_seg.v(45): variable \"send\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 45 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "send uart_seg.v(46) " "Verilog HDL Always Construct warning at uart_seg.v(46): variable \"send\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 46 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "send uart_seg.v(47) " "Verilog HDL Always Construct warning at uart_seg.v(47): variable \"send\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 47 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 uart_seg.v(45) " "Verilog HDL assignment warning at uart_seg.v(45): truncated value with size 32 to match size of target (26)" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 45 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "send uart_seg.v(48) " "Verilog HDL Always Construct warning at uart_seg.v(48): variable \"send\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 48 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "send uart_seg.v(49) " "Verilog HDL Always Construct warning at uart_seg.v(49): variable \"send\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 49 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 uart_seg.v(48) " "Verilog HDL assignment warning at uart_seg.v(48): truncated value with size 32 to match size of target (26)" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 48 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 uart_seg.v(83) " "Verilog HDL assignment warning at uart_seg.v(83): truncated value with size 32 to match size of target (24)" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 83 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_L2_HDL_INDEX_EXPR_NOT_WIDE_ENOUGH" "uart_seg.v(99) " "Verilog HDL or VHDL warning at the uart_seg.v(99): index expression is not wide enough to address all of the elements in the array" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 99 0 0 } }  } 0 10027 "Verilog HDL or VHDL warning at the %1!s!: index expression is not wide enough to address all of the elements in the array" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 uart_seg.v(99) " "Verilog HDL assignment warning at uart_seg.v(99): truncated value with size 32 to match size of target (2)" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 99 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 uart_seg.v(99) " "Verilog HDL assignment warning at uart_seg.v(99): truncated value with size 32 to match size of target (7)" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 99 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_L2_HDL_INDEX_EXPR_NOT_WIDE_ENOUGH" "uart_seg.v(100) " "Verilog HDL or VHDL warning at the uart_seg.v(100): index expression is not wide enough to address all of the elements in the array" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 100 0 0 } }  } 0 10027 "Verilog HDL or VHDL warning at the %1!s!: index expression is not wide enough to address all of the elements in the array" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 uart_seg.v(100) " "Verilog HDL assignment warning at uart_seg.v(100): truncated value with size 32 to match size of target (2)" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 100 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 uart_seg.v(100) " "Verilog HDL assignment warning at uart_seg.v(100): truncated value with size 32 to match size of target (7)" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 100 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_L2_HDL_INDEX_EXPR_NOT_WIDE_ENOUGH" "uart_seg.v(101) " "Verilog HDL or VHDL warning at the uart_seg.v(101): index expression is not wide enough to address all of the elements in the array" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 101 0 0 } }  } 0 10027 "Verilog HDL or VHDL warning at the %1!s!: index expression is not wide enough to address all of the elements in the array" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 uart_seg.v(101) " "Verilog HDL assignment warning at uart_seg.v(101): truncated value with size 32 to match size of target (2)" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 101 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 uart_seg.v(101) " "Verilog HDL assignment warning at uart_seg.v(101): truncated value with size 32 to match size of target (7)" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 101 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_L2_HDL_INDEX_EXPR_NOT_WIDE_ENOUGH" "uart_seg.v(102) " "Verilog HDL or VHDL warning at the uart_seg.v(102): index expression is not wide enough to address all of the elements in the array" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 102 0 0 } }  } 0 10027 "Verilog HDL or VHDL warning at the %1!s!: index expression is not wide enough to address all of the elements in the array" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 uart_seg.v(102) " "Verilog HDL assignment warning at uart_seg.v(102): truncated value with size 32 to match size of target (2)" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 102 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 uart_seg.v(102) " "Verilog HDL assignment warning at uart_seg.v(102): truncated value with size 32 to match size of target (7)" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 102 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 uart_seg.v(107) " "Verilog HDL assignment warning at uart_seg.v(107): truncated value with size 32 to match size of target (24)" {  } { { "uart_seg.v" "" { Text "C:/FPGA/my_project/mission/uart_seg.v" 107 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090630970 "|mission|uart_seg:uart_seg1"}
{ "Warning" "WSGN_SEARCH_FILE" "uart_bus.v 1 1 " "Using design file uart_bus.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Uart_Bus " "Found entity 1: Uart_Bus" {  } { { "uart_bus.v" "" { Text "C:/FPGA/my_project/mission/uart_bus.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090630982 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1614090630982 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Uart_Bus uart_seg:uart_seg1\|Uart_Bus:u1 " "Elaborating entity \"Uart_Bus\" for hierarchy \"uart_seg:uart_seg1\|Uart_Bus:u1\"" {  } { { "uart_seg.v" "u1" { Text "C:/FPGA/my_project/mission/uart_seg.v" 134 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614090630983 ""}
{ "Warning" "WSGN_SEARCH_FILE" "baud.v 1 1 " "Using design file baud.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Baud " "Found entity 1: Baud" {  } { { "baud.v" "" { Text "C:/FPGA/my_project/mission/baud.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090630993 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1614090630993 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Baud uart_seg:uart_seg1\|Uart_Bus:u1\|Baud:Baud_rx " "Elaborating entity \"Baud\" for hierarchy \"uart_seg:uart_seg1\|Uart_Bus:u1\|Baud:Baud_rx\"" {  } { { "uart_bus.v" "Baud_rx" { Text "C:/FPGA/my_project/mission/uart_bus.v" 50 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614090630993 ""}
{ "Warning" "WSGN_SEARCH_FILE" "uart_rx.v 1 1 " "Using design file uart_rx.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Uart_Rx " "Found entity 1: Uart_Rx" {  } { { "uart_rx.v" "" { Text "C:/FPGA/my_project/mission/uart_rx.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090631004 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1614090631004 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Uart_Rx uart_seg:uart_seg1\|Uart_Bus:u1\|Uart_Rx:Uart_Rx_uut " "Elaborating entity \"Uart_Rx\" for hierarchy \"uart_seg:uart_seg1\|Uart_Bus:u1\|Uart_Rx:Uart_Rx_uut\"" {  } { { "uart_bus.v" "Uart_Rx_uut" { Text "C:/FPGA/my_project/mission/uart_bus.v" 64 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614090631005 ""}
{ "Warning" "WSGN_SEARCH_FILE" "uart_tx.v 1 1 " "Using design file uart_tx.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Uart_Tx " "Found entity 1: Uart_Tx" {  } { { "uart_tx.v" "" { Text "C:/FPGA/my_project/mission/uart_tx.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090631018 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1614090631018 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Uart_Tx uart_seg:uart_seg1\|Uart_Bus:u1\|Uart_Tx:Uart_Tx_uut " "Elaborating entity \"Uart_Tx\" for hierarchy \"uart_seg:uart_seg1\|Uart_Bus:u1\|Uart_Tx:Uart_Tx_uut\"" {  } { { "uart_bus.v" "Uart_Tx_uut" { Text "C:/FPGA/my_project/mission/uart_bus.v" 94 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614090631019 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "oled.v(176) " "Verilog HDL information at oled.v(176): always construct contains both blocking and non-blocking assignments" {  } { { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 176 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1614090631032 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CMD cmd oled.v(40) " "Verilog HDL Declaration information at oled.v(40): object \"CMD\" differs only in case from object \"cmd\" in the same scope" {  } { { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 40 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1614090631033 ""}
{ "Warning" "WSGN_SEARCH_FILE" "oled.v 1 1 " "Using design file oled.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 oled " "Found entity 1: oled" {  } { { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090631033 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1614090631033 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "oled oled:oled1 " "Elaborating entity \"oled\" for hierarchy \"oled:oled1\"" {  } { { "mission.v" "oled1" { Text "C:/FPGA/my_project/mission/mission.v" 88 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614090631039 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "sign oled.v(51) " "Verilog HDL or VHDL warning at oled.v(51): object \"sign\" assigned a value but never read" {  } { { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 51 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1614090631060 "|mission|oled:oled1"}
{ "Critical Warning" "WVRFX_VERI_NO_DFF_INFERRED" "oled.v(178) " "Verilog HDL warning at oled.v(178): can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead" {  } { { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 178 0 0 } }  } 1 10237 "Verilog HDL warning at %1!s!: can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead" 0 0 "Analysis & Synthesis" 0 -1 1614090631060 "|mission|oled:oled1"}
{ "Critical Warning" "WVRFX_VERI_NO_DFF_INFERRED" "oled.v(179) " "Verilog HDL warning at oled.v(179): can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead" {  } { { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 179 0 0 } }  } 1 10237 "Verilog HDL warning at %1!s!: can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead" 0 0 "Analysis & Synthesis" 0 -1 1614090631060 "|mission|oled:oled1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 oled.v(180) " "Verilog HDL assignment warning at oled.v(180): truncated value with size 32 to match size of target (4)" {  } { { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 180 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090631060 "|mission|oled:oled1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 oled.v(181) " "Verilog HDL assignment warning at oled.v(181): truncated value with size 32 to match size of target (4)" {  } { { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 181 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090631060 "|mission|oled:oled1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 oled.v(182) " "Verilog HDL assignment warning at oled.v(182): truncated value with size 32 to match size of target (4)" {  } { { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 182 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090631060 "|mission|oled:oled1"}
{ "Critical Warning" "WVRFX_VERI_NO_DFF_INFERRED" "oled.v(183) " "Verilog HDL warning at oled.v(183): can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead" {  } { { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 183 0 0 } }  } 1 10237 "Verilog HDL warning at %1!s!: can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead" 0 0 "Analysis & Synthesis" 0 -1 1614090631060 "|mission|oled:oled1"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem\[31..16\] 0 oled.v(43) " "Net \"mem\[31..16\]\" at oled.v(43) has no driver or initial value, using a default initial value '0'" {  } { { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 43 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1614090631060 "|mission|oled:oled1"}
{ "Warning" "WSGN_SEARCH_FILE" "beeper.v 1 1 " "Using design file beeper.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Beeper " "Found entity 1: Beeper" {  } { { "beeper.v" "" { Text "C:/FPGA/my_project/mission/beeper.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090631073 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1614090631073 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Beeper Beeper:beeper1 " "Elaborating entity \"Beeper\" for hierarchy \"Beeper:beeper1\"" {  } { { "mission.v" "beeper1" { Text "C:/FPGA/my_project/mission/mission.v" 99 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614090631075 ""}
{ "Warning" "WSGN_SEARCH_FILE" "tone.v 1 1 " "Using design file tone.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 tone " "Found entity 1: tone" {  } { { "tone.v" "" { Text "C:/FPGA/my_project/mission/tone.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090631087 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1614090631087 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tone Beeper:beeper1\|tone:u1 " "Elaborating entity \"tone\" for hierarchy \"Beeper:beeper1\|tone:u1\"" {  } { { "beeper.v" "u1" { Text "C:/FPGA/my_project/mission/beeper.v" 41 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614090631088 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 tone.v(84) " "Verilog HDL assignment warning at tone.v(84): truncated value with size 32 to match size of target (5)" {  } { { "tone.v" "" { Text "C:/FPGA/my_project/mission/tone.v" 84 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614090631094 "|mission|Beeper:beeper1|tone:u1"}
{ "Warning" "WSGN_SEARCH_FILE" "pwm.v 1 1 " "Using design file pwm.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 PWM " "Found entity 1: PWM" {  } { { "pwm.v" "" { Text "C:/FPGA/my_project/mission/pwm.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090631132 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1614090631132 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PWM Beeper:beeper1\|PWM:u2 " "Elaborating entity \"PWM\" for hierarchy \"Beeper:beeper1\|PWM:u2\"" {  } { { "beeper.v" "u2" { Text "C:/FPGA/my_project/mission/beeper.v" 55 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614090631133 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "temperature temperature:temperature1 " "Elaborating entity \"temperature\" for hierarchy \"temperature:temperature1\"" {  } { { "mission.v" "temperature1" { Text "C:/FPGA/my_project/mission/mission.v" 107 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614090631138 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "3 " "Inferred 3 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "oled:oled1\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"oled:oled1\|Mod0\"" {  } { { "oled.v" "Mod0" { Text "C:/FPGA/my_project/mission/oled.v" 180 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1614090633712 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "oled:oled1\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"oled:oled1\|Div0\"" {  } { { "oled.v" "Div0" { Text "C:/FPGA/my_project/mission/oled.v" 180 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1614090633712 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "oled:oled1\|Mod1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"oled:oled1\|Mod1\"" {  } { { "oled.v" "Mod1" { Text "C:/FPGA/my_project/mission/oled.v" 181 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1614090633712 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1614090633712 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "oled:oled1\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"oled:oled1\|lpm_divide:Mod0\"" {  } { { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 180 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614090633756 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "oled:oled1\|lpm_divide:Mod0 " "Instantiated megafunction \"oled:oled1\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 16 " "Parameter \"LPM_WIDTHN\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614090633756 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 7 " "Parameter \"LPM_WIDTHD\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614090633756 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614090633756 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614090633756 ""}  } { { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 180 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1614090633756 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ull.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_ull.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ull " "Found entity 1: lpm_divide_ull" {  } { { "db/lpm_divide_ull.tdf" "" { Text "C:/FPGA/my_project/mission/db/lpm_divide_ull.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090633802 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090633802 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_tlh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_tlh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_tlh " "Found entity 1: sign_div_unsign_tlh" {  } { { "db/sign_div_unsign_tlh.tdf" "" { Text "C:/FPGA/my_project/mission/db/sign_div_unsign_tlh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090633819 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090633819 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_4ie.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_4ie.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_4ie " "Found entity 1: alt_u_div_4ie" {  } { { "db/alt_u_div_4ie.tdf" "" { Text "C:/FPGA/my_project/mission/db/alt_u_div_4ie.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090633840 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090633840 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_t3c.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_t3c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_t3c " "Found entity 1: add_sub_t3c" {  } { { "db/add_sub_t3c.tdf" "" { Text "C:/FPGA/my_project/mission/db/add_sub_t3c.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090633889 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090633889 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_u3c.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_u3c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_u3c " "Found entity 1: add_sub_u3c" {  } { { "db/add_sub_u3c.tdf" "" { Text "C:/FPGA/my_project/mission/db/add_sub_u3c.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090633938 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090633938 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "oled:oled1\|lpm_divide:Div0 " "Elaborated megafunction instantiation \"oled:oled1\|lpm_divide:Div0\"" {  } { { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 180 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614090633949 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "oled:oled1\|lpm_divide:Div0 " "Instantiated megafunction \"oled:oled1\|lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 7 " "Parameter \"LPM_WIDTHN\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614090633949 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614090633949 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614090633949 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614090633949 ""}  } { { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 180 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1614090633949 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_8sl.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_8sl.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_8sl " "Found entity 1: lpm_divide_8sl" {  } { { "db/lpm_divide_8sl.tdf" "" { Text "C:/FPGA/my_project/mission/db/lpm_divide_8sl.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090633993 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090633993 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_akh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_akh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_akh " "Found entity 1: sign_div_unsign_akh" {  } { { "db/sign_div_unsign_akh.tdf" "" { Text "C:/FPGA/my_project/mission/db/sign_div_unsign_akh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090634009 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090634009 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_uee.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_uee.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_uee " "Found entity 1: alt_u_div_uee" {  } { { "db/alt_u_div_uee.tdf" "" { Text "C:/FPGA/my_project/mission/db/alt_u_div_uee.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090634026 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090634026 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "oled:oled1\|lpm_divide:Mod1 " "Elaborated megafunction instantiation \"oled:oled1\|lpm_divide:Mod1\"" {  } { { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 181 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614090634040 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "oled:oled1\|lpm_divide:Mod1 " "Instantiated megafunction \"oled:oled1\|lpm_divide:Mod1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 16 " "Parameter \"LPM_WIDTHN\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614090634041 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614090634041 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614090634041 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614090634041 ""}  } { { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 181 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1614090634041 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_rll.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_rll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_rll " "Found entity 1: lpm_divide_rll" {  } { { "db/lpm_divide_rll.tdf" "" { Text "C:/FPGA/my_project/mission/db/lpm_divide_rll.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090634083 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090634083 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_qlh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_qlh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_qlh " "Found entity 1: sign_div_unsign_qlh" {  } { { "db/sign_div_unsign_qlh.tdf" "" { Text "C:/FPGA/my_project/mission/db/sign_div_unsign_qlh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090634101 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090634101 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_uhe.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_uhe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_uhe " "Found entity 1: alt_u_div_uhe" {  } { { "db/alt_u_div_uhe.tdf" "" { Text "C:/FPGA/my_project/mission/db/alt_u_div_uhe.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614090634125 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090634125 ""}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1614090634456 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 30 -1 0 } } { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 31 -1 0 } } { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 33 -1 0 } } { "pwm.v" "" { Text "C:/FPGA/my_project/mission/pwm.v" 28 -1 0 } } { "uart_tx.v" "" { Text "C:/FPGA/my_project/mission/uart_tx.v" 29 -1 0 } } { "oled.v" "" { Text "C:/FPGA/my_project/mission/oled.v" 62 -1 0 } } { "debounce.v" "" { Text "C:/FPGA/my_project/mission/debounce.v" 52 -1 0 } } { "debounce.v" "" { Text "C:/FPGA/my_project/mission/debounce.v" 45 -1 0 } } { "tone.v" "" { Text "C:/FPGA/my_project/mission/tone.v" 53 -1 0 } } { "debounce.v" "" { Text "C:/FPGA/my_project/mission/debounce.v" 29 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1614090634489 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1614090634489 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1614090636066 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "7 " "7 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1614090639584 ""}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "oled:oled1\|lpm_divide:Mod0\|lpm_divide_ull:auto_generated\|sign_div_unsign_tlh:divider\|alt_u_div_4ie:divider\|add_sub_15_result_int\[1\]~14 " "Logic cell \"oled:oled1\|lpm_divide:Mod0\|lpm_divide_ull:auto_generated\|sign_div_unsign_tlh:divider\|alt_u_div_4ie:divider\|add_sub_15_result_int\[1\]~14\"" {  } { { "db/alt_u_div_4ie.tdf" "add_sub_15_result_int\[1\]~14" { Text "C:/FPGA/my_project/mission/db/alt_u_div_4ie.tdf" 61 23 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1614090639597 ""}  } {  } 0 17016 "Found the following redundant logic cells in design" 0 0 "Analysis & Synthesis" 0 -1 1614090639597 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/FPGA/my_project/mission/output_files/mission.map.smsg " "Generated suppressed messages file C:/FPGA/my_project/mission/output_files/mission.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090639689 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1614090639858 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614090639858 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "4 " "Design contains 4 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" {  } { { "mission.v" "" { Text "C:/FPGA/my_project/mission/mission.v" 5 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1614090640064 "|mission|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[1\] " "No output dependent on input pin \"SW\[1\]\"" {  } { { "mission.v" "" { Text "C:/FPGA/my_project/mission/mission.v" 5 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1614090640064 "|mission|SW[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[2\] " "No output dependent on input pin \"SW\[2\]\"" {  } { { "mission.v" "" { Text "C:/FPGA/my_project/mission/mission.v" 5 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1614090640064 "|mission|SW[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" {  } { { "mission.v" "" { Text "C:/FPGA/my_project/mission/mission.v" 5 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1614090640064 "|mission|SW[3]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1614090640064 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "2093 " "Implemented 2093 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1614090640065 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1614090640065 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "1 " "Implemented 1 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1614090640065 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2075 " "Implemented 2075 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1614090640065 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1614090640065 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 57 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 57 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4801 " "Peak virtual memory: 4801 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1614090640100 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 23 22:30:40 2021 " "Processing ended: Tue Feb 23 22:30:40 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1614090640100 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:20 " "Elapsed time: 00:00:20" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1614090640100 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:33 " "Total CPU time (on all processors): 00:00:33" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1614090640100 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1614090640100 ""}
