module clock
(
input  [2:0] BTN,  //button key
input clk_in,  //clk_in = 25mhz
output Time,
)

reg time1;

always@(posedge clk_in)
	begin
		if(time1>=1440)
			time1 = 0;
		else
			time1 = time1 + 1;
		Time <= time1;
	end
	
endmodule 

		