module clock
(
input  [2:0] BTN,  //button key
input clk,  //clk_in = 12mhz
input rst_n,
output reg [3:0] num1,
output reg [3:0] num2,
output reg [3:0] num3,
output reg [3:0] num4
);

reg [24:0] cnt1;
reg [24:0] cnt2;

always@(posedge clk or negedge rst_n)
	begin
		if(!rst_n) 
			begin
				cnt1<=0;
				cnt2<=0;
				num1<=0;
				num2<=0;
				num3<=0;
				num4<=0;
			end 
		else if(cnt1 >= 12000000-1)
			begin
				cnt1 <= 0;
				cnt2 <= cnt2 + 1;
				if(cnt2 >= 60-1)
					begin
						cnt2 <= 0;
						num1 = num1 + 1;
					end
			end
		else if(BTN[1])
			begin
				num1 <= num1 + 1;
			end
		else if (BTN[2])
			begin
				num3 = num3 + 1;
			end
		else if(num1 >= 10)
			begin
				num1 = 0;
				num2 = num2 + 1;
			end
		else if(num2 >= 6)
			begin
				num2 = 0;
				num3 = num3 + 1;
			end
		else if(num3 >= 10)
			begin
				num3 = 0;
				num4 = num4 + 1;
			end
		else if(num4 == 2 && num3 == 4)
			begin
				num3 = 0;
				num4 = 0;
			end
		else
			begin
				cnt1 <= cnt1 + 1;
			end
	end
	
		
endmodule 

		