module clk_1MHz(clk,clk_1MHz);
input clk;
output clk_1MHz;
reg clk_1MHz;
reg[2:0] num;
always @(posedge clk)
    begin
	 if(num < 6)
	     num = num+1;
	 else
	     begin
		  clk_1MHz = ~clk_1MHz;
		  num = 0;
		  end
	 end
endmodule