{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1614053587008 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1614053587036 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 23 12:13:06 2021 " "Processing started: Tue Feb 23 12:13:06 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1614053587036 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053587036 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off pro_1 -c pro_1 " "Command: quartus_map --read_settings_files=on --write_settings_files=off pro_1 -c pro_1" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053587037 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1614053587690 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1614053587690 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pro_1.bdf 1 1 " "Found 1 design units, including 1 entities, in source file pro_1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 pro_1 " "Found entity 1: pro_1" {  } { { "pro_1.bdf" "" { Schematic "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/pro_1.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053603610 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053603610 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "temperature.v(35) " "Verilog HDL information at temperature.v(35): always construct contains both blocking and non-blocking assignments" {  } { { "temperature.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/temperature.v" 35 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1614053603625 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "temperature.v 1 1 " "Found 1 design units, including 1 entities, in source file temperature.v" { { "Info" "ISGN_ENTITY_NAME" "1 temperature " "Found entity 1: temperature" {  } { { "temperature.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/temperature.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053603634 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053603634 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_1mhz.v 1 1 " "Found 1 design units, including 1 entities, in source file clk_1mhz.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_1MHz " "Found entity 1: clk_1MHz" {  } { { "clk_1MHz.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/clk_1MHz.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053603648 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053603648 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tem_trans.v 1 1 " "Found 1 design units, including 1 entities, in source file tem_trans.v" { { "Info" "ISGN_ENTITY_NAME" "1 tem_trans " "Found entity 1: tem_trans" {  } { { "tem_trans.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/tem_trans.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053603660 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053603660 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CMD cmd OLED.v(10) " "Verilog HDL Declaration information at OLED.v(10): object \"CMD\" differs only in case from object \"cmd\" in the same scope" {  } { { "OLED.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/OLED.v" 10 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1614053603680 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "oled.v 1 1 " "Found 1 design units, including 1 entities, in source file oled.v" { { "Info" "ISGN_ENTITY_NAME" "1 OLED " "Found entity 1: OLED" {  } { { "OLED.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/OLED.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053603685 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053603685 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reset.v 1 1 " "Found 1 design units, including 1 entities, in source file reset.v" { { "Info" "ISGN_ENTITY_NAME" "1 reset " "Found entity 1: reset" {  } { { "reset.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/reset.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053603700 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053603700 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_buzzer.v 1 1 " "Found 1 design units, including 1 entities, in source file clk_buzzer.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_buzzer " "Found entity 1: clk_buzzer" {  } { { "clk_buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/clk_buzzer.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053603720 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053603720 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "buzzer.v(36) " "Verilog HDL information at buzzer.v(36): always construct contains both blocking and non-blocking assignments" {  } { { "buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/buzzer.v" 36 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1614053603730 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "buzzer.v(79) " "Verilog HDL information at buzzer.v(79): always construct contains both blocking and non-blocking assignments" {  } { { "buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/buzzer.v" 79 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1614053603730 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "buzzer.v 1 1 " "Found 1 design units, including 1 entities, in source file buzzer.v" { { "Info" "ISGN_ENTITY_NAME" "1 buzzer " "Found entity 1: buzzer" {  } { { "buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/buzzer.v" 7 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053603730 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053603730 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "pro_1 " "Elaborating entity \"pro_1\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1614053603945 ""}
{ "Warning" "WSGN_SEARCH_FILE" "uart_tx.v 1 1 " "Using design file uart_tx.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 uart_tx " "Found entity 1: uart_tx" {  } { { "uart_tx.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/uart_tx.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053603980 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1614053603980 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_tx uart_tx:inst4 " "Elaborating entity \"uart_tx\" for hierarchy \"uart_tx:inst4\"" {  } { { "pro_1.bdf" "inst4" { Schematic "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/pro_1.bdf" { { -240 -8384 -8200 -128 "inst4" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614053603980 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_tx.v(29) " "Verilog HDL assignment warning at uart_tx.v(29): truncated value with size 2 to match size of target (1)" {  } { { "uart_tx.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/uart_tx.v" 29 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053603990 "|pro_1|uart_tx:inst4"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_tx.v(45) " "Verilog HDL assignment warning at uart_tx.v(45): truncated value with size 2 to match size of target (1)" {  } { { "uart_tx.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/uart_tx.v" 45 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053603990 "|pro_1|uart_tx:inst4"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 uart_tx.v(51) " "Verilog HDL assignment warning at uart_tx.v(51): truncated value with size 32 to match size of target (7)" {  } { { "uart_tx.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/uart_tx.v" 51 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053603990 "|pro_1|uart_tx:inst4"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_tx.v(56) " "Verilog HDL assignment warning at uart_tx.v(56): truncated value with size 2 to match size of target (1)" {  } { { "uart_tx.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/uart_tx.v" 56 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053603990 "|pro_1|uart_tx:inst4"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "tab.data_a 0 uart_tx.v(10) " "Net \"tab.data_a\" at uart_tx.v(10) has no driver or initial value, using a default initial value '0'" {  } { { "uart_tx.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/uart_tx.v" 10 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1614053603990 "|pro_1|uart_tx:inst4"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "tab.waddr_a 0 uart_tx.v(10) " "Net \"tab.waddr_a\" at uart_tx.v(10) has no driver or initial value, using a default initial value '0'" {  } { { "uart_tx.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/uart_tx.v" 10 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1614053603990 "|pro_1|uart_tx:inst4"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "tab.we_a 0 uart_tx.v(10) " "Net \"tab.we_a\" at uart_tx.v(10) has no driver or initial value, using a default initial value '0'" {  } { { "uart_tx.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/uart_tx.v" 10 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1614053603990 "|pro_1|uart_tx:inst4"}
{ "Warning" "WSGN_SEARCH_FILE" "clk_uart_tx.v 1 1 " "Using design file clk_uart_tx.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 clk_uart_tx " "Found entity 1: clk_uart_tx" {  } { { "clk_uart_tx.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/clk_uart_tx.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053604039 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1614053604039 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_uart_tx clk_uart_tx:inst2 " "Elaborating entity \"clk_uart_tx\" for hierarchy \"clk_uart_tx:inst2\"" {  } { { "pro_1.bdf" "inst2" { Schematic "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/pro_1.bdf" { { -208 -9528 -9376 -128 "inst2" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614053604042 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 clk_uart_tx.v(11) " "Verilog HDL assignment warning at clk_uart_tx.v(11): truncated value with size 32 to match size of target (10)" {  } { { "clk_uart_tx.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/clk_uart_tx.v" 11 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604044 "|pro_1|clk_uart_tx:inst2"}
{ "Warning" "WSGN_SEARCH_FILE" "clock.v 1 1 " "Using design file clock.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Found entity 1: clock" {  } { { "clock.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/clock.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053604081 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1614053604081 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock clock:inst1 " "Elaborating entity \"clock\" for hierarchy \"clock:inst1\"" {  } { { "pro_1.bdf" "inst1" { Schematic "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/pro_1.bdf" { { -368 -9160 -8960 -224 "inst1" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614053604085 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(34) " "Verilog HDL assignment warning at clock.v(34): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/clock.v" 34 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604088 "|pro_1|clock:inst1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(40) " "Verilog HDL assignment warning at clock.v(40): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/clock.v" 40 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604088 "|pro_1|clock:inst1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(46) " "Verilog HDL assignment warning at clock.v(46): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/clock.v" 46 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604088 "|pro_1|clock:inst1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(52) " "Verilog HDL assignment warning at clock.v(52): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/clock.v" 52 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604088 "|pro_1|clock:inst1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 clock.v(78) " "Verilog HDL assignment warning at clock.v(78): truncated value with size 32 to match size of target (16)" {  } { { "clock.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/clock.v" 78 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604088 "|pro_1|clock:inst1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(81) " "Verilog HDL assignment warning at clock.v(81): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/clock.v" 81 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604088 "|pro_1|clock:inst1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(85) " "Verilog HDL assignment warning at clock.v(85): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/clock.v" 85 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604088 "|pro_1|clock:inst1"}
{ "Warning" "WSGN_SEARCH_FILE" "clk_second.v 1 1 " "Using design file clk_second.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 clk_second " "Found entity 1: clk_second" {  } { { "clk_second.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/clk_second.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053604129 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1614053604129 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_second clk_second:inst " "Elaborating entity \"clk_second\" for hierarchy \"clk_second:inst\"" {  } { { "pro_1.bdf" "inst" { Schematic "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/pro_1.bdf" { { -304 -9528 -9360 -224 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614053604136 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 clk_second.v(19) " "Verilog HDL assignment warning at clk_second.v(19): truncated value with size 32 to match size of target (23)" {  } { { "clk_second.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/clk_second.v" 19 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604136 "|pro_1|clk_second:inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 clk_second.v(28) " "Verilog HDL assignment warning at clk_second.v(28): truncated value with size 32 to match size of target (23)" {  } { { "clk_second.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/clk_second.v" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604136 "|pro_1|clk_second:inst"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tem_trans tem_trans:inst9 " "Elaborating entity \"tem_trans\" for hierarchy \"tem_trans:inst9\"" {  } { { "pro_1.bdf" "inst9" { Schematic "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/pro_1.bdf" { { -24 -8656 -8440 88 "inst9" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614053604140 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 31 tem_trans.v(14) " "Verilog HDL assignment warning at tem_trans.v(14): truncated value with size 32 to match size of target (31)" {  } { { "tem_trans.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/tem_trans.v" 14 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604145 "|pro_1|tem_trans:inst9"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 tem_trans.v(17) " "Verilog HDL assignment warning at tem_trans.v(17): truncated value with size 32 to match size of target (8)" {  } { { "tem_trans.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/tem_trans.v" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604145 "|pro_1|tem_trans:inst9"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 tem_trans.v(18) " "Verilog HDL assignment warning at tem_trans.v(18): truncated value with size 32 to match size of target (8)" {  } { { "tem_trans.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/tem_trans.v" 18 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604145 "|pro_1|tem_trans:inst9"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "temperature temperature:inst8 " "Elaborating entity \"temperature\" for hierarchy \"temperature:inst8\"" {  } { { "pro_1.bdf" "inst8" { Schematic "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/pro_1.bdf" { { -40 -9008 -8840 40 "inst8" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614053604150 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 temperature.v(68) " "Verilog HDL assignment warning at temperature.v(68): truncated value with size 32 to match size of target (4)" {  } { { "temperature.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/temperature.v" 68 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604154 "|pro_1|temperature:inst8"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 temperature.v(134) " "Verilog HDL assignment warning at temperature.v(134): truncated value with size 32 to match size of target (3)" {  } { { "temperature.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/temperature.v" 134 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604154 "|pro_1|temperature:inst8"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_1MHz clk_1MHz:inst7 " "Elaborating entity \"clk_1MHz\" for hierarchy \"clk_1MHz:inst7\"" {  } { { "pro_1.bdf" "inst7" { Schematic "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/pro_1.bdf" { { -40 -9528 -9376 40 "inst7" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614053604154 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 clk_1MHz.v(9) " "Verilog HDL assignment warning at clk_1MHz.v(9): truncated value with size 32 to match size of target (3)" {  } { { "clk_1MHz.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/clk_1MHz.v" 9 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604160 "|pro_1|clk_1MHz:inst7"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reset reset:inst12 " "Elaborating entity \"reset\" for hierarchy \"reset:inst12\"" {  } { { "pro_1.bdf" "inst12" { Schematic "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/pro_1.bdf" { { -8 -9160 -9024 104 "inst12" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614053604165 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "OLED OLED:inst10 " "Elaborating entity \"OLED\" for hierarchy \"OLED:inst10\"" {  } { { "pro_1.bdf" "inst10" { Schematic "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/pro_1.bdf" { { -432 -8112 -7928 -224 "inst10" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614053604170 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 OLED.v(84) " "Verilog HDL assignment warning at OLED.v(84): truncated value with size 32 to match size of target (5)" {  } { { "OLED.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/OLED.v" 84 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604170 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "184 168 OLED.v(120) " "Verilog HDL assignment warning at OLED.v(120): truncated value with size 184 to match size of target (168)" {  } { { "OLED.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/OLED.v" 120 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604170 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "cmd.data_a 0 OLED.v(14) " "Net \"cmd.data_a\" at OLED.v(14) has no driver or initial value, using a default initial value '0'" {  } { { "OLED.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/OLED.v" 14 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1614053604170 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "cmd.waddr_a 0 OLED.v(14) " "Net \"cmd.waddr_a\" at OLED.v(14) has no driver or initial value, using a default initial value '0'" {  } { { "OLED.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/OLED.v" 14 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1614053604170 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 OLED.v(15) " "Net \"mem.data_a\" at OLED.v(15) has no driver or initial value, using a default initial value '0'" {  } { { "OLED.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/OLED.v" 15 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1614053604170 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 OLED.v(15) " "Net \"mem.waddr_a\" at OLED.v(15) has no driver or initial value, using a default initial value '0'" {  } { { "OLED.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/OLED.v" 15 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1614053604170 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "cmd.we_a 0 OLED.v(14) " "Net \"cmd.we_a\" at OLED.v(14) has no driver or initial value, using a default initial value '0'" {  } { { "OLED.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/OLED.v" 14 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1614053604170 "|pro_1|OLED:inst10"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 OLED.v(15) " "Net \"mem.we_a\" at OLED.v(15) has no driver or initial value, using a default initial value '0'" {  } { { "OLED.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/OLED.v" 15 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1614053604170 "|pro_1|OLED:inst10"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "buzzer buzzer:inst13 " "Elaborating entity \"buzzer\" for hierarchy \"buzzer:inst13\"" {  } { { "pro_1.bdf" "inst13" { Schematic "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/pro_1.bdf" { { -128 -8368 -8184 16 "inst13" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614053604180 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "flag_1 buzzer.v(23) " "Verilog HDL or VHDL warning at buzzer.v(23): object \"flag_1\" assigned a value but never read" {  } { { "buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/buzzer.v" 23 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1614053604180 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "flag_2 buzzer.v(23) " "Verilog HDL or VHDL warning at buzzer.v(23): object \"flag_2\" assigned a value but never read" {  } { { "buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/buzzer.v" 23 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1614053604180 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 buzzer.v(32) " "Verilog HDL assignment warning at buzzer.v(32): truncated value with size 32 to match size of target (6)" {  } { { "buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/buzzer.v" 32 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604180 "|pro_1|buzzer:inst13"}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "buzzer.v(42) " "Verilog HDL Case Statement information at buzzer.v(42): all case item expressions in this case statement are onehot" {  } { { "buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/buzzer.v" 42 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1614053604180 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 buzzer.v(72) " "Verilog HDL assignment warning at buzzer.v(72): truncated value with size 8 to match size of target (4)" {  } { { "buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/buzzer.v" 72 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604180 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 buzzer.v(73) " "Verilog HDL assignment warning at buzzer.v(73): truncated value with size 32 to match size of target (6)" {  } { { "buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/buzzer.v" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604180 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "buzzer.v(97) " "Verilog HDL Case Statement warning at buzzer.v(97): case item expression never matches the case expression" {  } { { "buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/buzzer.v" 97 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "Analysis & Synthesis" 0 -1 1614053604180 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "buzzer.v(98) " "Verilog HDL Case Statement warning at buzzer.v(98): case item expression never matches the case expression" {  } { { "buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/buzzer.v" 98 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "Analysis & Synthesis" 0 -1 1614053604180 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "buzzer.v(99) " "Verilog HDL Case Statement warning at buzzer.v(99): case item expression never matches the case expression" {  } { { "buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/buzzer.v" 99 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "Analysis & Synthesis" 0 -1 1614053604180 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "buzzer.v(100) " "Verilog HDL Case Statement warning at buzzer.v(100): case item expression never matches the case expression" {  } { { "buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/buzzer.v" 100 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "Analysis & Synthesis" 0 -1 1614053604180 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "buzzer.v(101) " "Verilog HDL Case Statement warning at buzzer.v(101): case item expression never matches the case expression" {  } { { "buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/buzzer.v" 101 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "Analysis & Synthesis" 0 -1 1614053604180 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "buzzer.v(102) " "Verilog HDL Case Statement warning at buzzer.v(102): case item expression never matches the case expression" {  } { { "buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/buzzer.v" 102 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "Analysis & Synthesis" 0 -1 1614053604180 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 buzzer.v(113) " "Verilog HDL assignment warning at buzzer.v(113): truncated value with size 32 to match size of target (18)" {  } { { "buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/buzzer.v" 113 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604180 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 buzzer.v(119) " "Verilog HDL assignment warning at buzzer.v(119): truncated value with size 32 to match size of target (24)" {  } { { "buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/buzzer.v" 119 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604180 "|pro_1|buzzer:inst13"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "judge\[2\] 0 buzzer.v(24) " "Net \"judge\[2\]\" at buzzer.v(24) has no driver or initial value, using a default initial value '0'" {  } { { "buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/buzzer.v" 24 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1614053604190 "|pro_1|buzzer:inst13"}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "TIMES times uart_rx.v(6) " "Verilog HDL Declaration information at uart_rx.v(6): object \"TIMES\" differs only in case from object \"times\" in the same scope" {  } { { "uart_rx.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/uart_rx.v" 6 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1614053604280 ""}
{ "Warning" "WSGN_SEARCH_FILE" "uart_rx.v 1 1 " "Using design file uart_rx.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 uart_rx " "Found entity 1: uart_rx" {  } { { "uart_rx.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/uart_rx.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053604290 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1614053604290 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_rx uart_rx:inst3 " "Elaborating entity \"uart_rx\" for hierarchy \"uart_rx:inst3\"" {  } { { "pro_1.bdf" "inst3" { Schematic "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/pro_1.bdf" { { -128 -8952 -8768 -48 "inst3" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614053604290 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 uart_rx.v(38) " "Verilog HDL assignment warning at uart_rx.v(38): truncated value with size 32 to match size of target (11)" {  } { { "uart_rx.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/uart_rx.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604290 "|pro_1|uart_rx:inst3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 uart_rx.v(39) " "Verilog HDL assignment warning at uart_rx.v(39): truncated value with size 32 to match size of target (11)" {  } { { "uart_rx.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/uart_rx.v" 39 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604290 "|pro_1|uart_rx:inst3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 uart_rx.v(58) " "Verilog HDL assignment warning at uart_rx.v(58): truncated value with size 32 to match size of target (11)" {  } { { "uart_rx.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/uart_rx.v" 58 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604290 "|pro_1|uart_rx:inst3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 uart_rx.v(61) " "Verilog HDL assignment warning at uart_rx.v(61): truncated value with size 32 to match size of target (11)" {  } { { "uart_rx.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/uart_rx.v" 61 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604290 "|pro_1|uart_rx:inst3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 uart_rx.v(73) " "Verilog HDL assignment warning at uart_rx.v(73): truncated value with size 32 to match size of target (4)" {  } { { "uart_rx.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/uart_rx.v" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604290 "|pro_1|uart_rx:inst3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 uart_rx.v(89) " "Verilog HDL assignment warning at uart_rx.v(89): truncated value with size 32 to match size of target (6)" {  } { { "uart_rx.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/uart_rx.v" 89 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604290 "|pro_1|uart_rx:inst3"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_buzzer clk_buzzer:inst11 " "Elaborating entity \"clk_buzzer\" for hierarchy \"clk_buzzer:inst11\"" {  } { { "pro_1.bdf" "inst11" { Schematic "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/pro_1.bdf" { { 136 -9528 -9376 216 "inst11" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614053604300 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 clk_buzzer.v(16) " "Verilog HDL assignment warning at clk_buzzer.v(16): truncated value with size 32 to match size of target (23)" {  } { { "clk_buzzer.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/clk_buzzer.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604300 "|pro_1|clk_buzzer:inst11"}
{ "Warning" "WSGN_SEARCH_FILE" "trans.v 1 1 " "Using design file trans.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 trans " "Found entity 1: trans" {  } { { "trans.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/trans.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053604360 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1614053604360 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "trans trans:inst5 " "Elaborating entity \"trans\" for hierarchy \"trans:inst5\"" {  } { { "pro_1.bdf" "inst5" { Schematic "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/pro_1.bdf" { { -400 -8856 -8640 -320 "inst5" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614053604370 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 trans.v(8) " "Verilog HDL assignment warning at trans.v(8): truncated value with size 32 to match size of target (8)" {  } { { "trans.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/trans.v" 8 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604370 "|pro_1|trans:inst5"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 trans.v(9) " "Verilog HDL assignment warning at trans.v(9): truncated value with size 32 to match size of target (8)" {  } { { "trans.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/trans.v" 9 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1614053604370 "|pro_1|trans:inst5"}
{ "Critical Warning" "WCDB_CDB_LESS_INI_CONTENT" "16 10 C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/pro_1.ram0_uart_tx_5cd61368.hdl.mif " "Memory depth (16) in the design file differs from memory depth (10) in the Memory Initialization File \"C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/pro_1.ram0_uart_tx_5cd61368.hdl.mif\" -- setting initial value for remaining addresses to 0" {  } {  } 1 127005 "Memory depth (%1!d!) in the design file differs from memory depth (%2!d!) in the Memory Initialization File \"%3!s!\" -- setting initial value for remaining addresses to 0" 0 0 "Analysis & Synthesis" 0 -1 1614053605665 ""}
{ "Critical Warning" "WCDB_CDB_LESS_INI_CONTENT" "32 25 C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/pro_1.ram0_OLED_2af399.hdl.mif " "Memory depth (32) in the design file differs from memory depth (25) in the Memory Initialization File \"C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/pro_1.ram0_OLED_2af399.hdl.mif\" -- setting initial value for remaining addresses to 0" {  } {  } 1 127005 "Memory depth (%1!d!) in the design file differs from memory depth (%2!d!) in the Memory Initialization File \"%3!s!\" -- setting initial value for remaining addresses to 0" 0 0 "Analysis & Synthesis" 0 -1 1614053605671 ""}
{ "Critical Warning" "WCDB_CDB_LESS_INI_CONTENT" "128 124 C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/pro_1.ram1_OLED_2af399.hdl.mif " "Memory depth (128) in the design file differs from memory depth (124) in the Memory Initialization File \"C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/pro_1.ram1_OLED_2af399.hdl.mif\" -- setting initial value for remaining addresses to 0" {  } {  } 1 127005 "Memory depth (%1!d!) in the design file differs from memory depth (%2!d!) in the Memory Initialization File \"%3!s!\" -- setting initial value for remaining addresses to 0" 0 0 "Analysis & Synthesis" 0 -1 1614053605676 ""}
{ "Warning" "WCDB_CDB_RAM_MIF_CONTAIN_DONT_CARE" "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/pro_1.ram1_OLED_2af399.hdl.mif " "Memory Initialization File or Hexadecimal (Intel-Format) File \"C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/pro_1.ram1_OLED_2af399.hdl.mif\" contains \"don't care\" values -- overwriting them with 0s" {  } {  } 0 127007 "Memory Initialization File or Hexadecimal (Intel-Format) File \"%1!s!\" contains \"don't care\" values -- overwriting them with 0s" 0 0 "Analysis & Synthesis" 0 -1 1614053605680 ""}
{ "Info" "IINFER_UNINFERRED_RAM_SUMMARY" "3 " "Found 3 instances of uninferred RAM logic" { { "Info" "IINFER_MIF_NOT_SUPPORTED_FOR_HARDCOPY" "uart_tx:inst4\|tab " "RAM logic \"uart_tx:inst4\|tab\" is uninferred because MIF is not supported for the selected family" {  } { { "uart_tx.v" "tab" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/uart_tx.v" 10 -1 0 } }  } 0 276013 "RAM logic \"%1!s!\" is uninferred because MIF is not supported for the selected family" 0 0 "Design Software" 0 -1 1614053605715 ""} { "Info" "IINFER_MIF_NOT_SUPPORTED_FOR_HARDCOPY" "OLED:inst10\|cmd " "RAM logic \"OLED:inst10\|cmd\" is uninferred because MIF is not supported for the selected family" {  } { { "OLED.v" "cmd" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/OLED.v" 14 -1 0 } }  } 0 276013 "RAM logic \"%1!s!\" is uninferred because MIF is not supported for the selected family" 0 0 "Design Software" 0 -1 1614053605715 ""} { "Info" "IINFER_MIF_NOT_SUPPORTED_FOR_HARDCOPY" "OLED:inst10\|mem " "RAM logic \"OLED:inst10\|mem\" is uninferred because MIF is not supported for the selected family" {  } { { "OLED.v" "mem" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/OLED.v" 15 -1 0 } }  } 0 276013 "RAM logic \"%1!s!\" is uninferred because MIF is not supported for the selected family" 0 0 "Design Software" 0 -1 1614053605715 ""}  } {  } 0 276014 "Found %1!d! instances of uninferred RAM logic" 0 0 "Analysis & Synthesis" 0 -1 1614053605715 ""}
{ "Warning" "WCDB_CDB_RAM_MIF_CONTAIN_DONT_CARE" "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/pro_1.ram1_OLED_2af399.hdl.mif " "Memory Initialization File or Hexadecimal (Intel-Format) File \"C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/pro_1.ram1_OLED_2af399.hdl.mif\" contains \"don't care\" values -- overwriting them with 0s" {  } {  } 0 127007 "Memory Initialization File or Hexadecimal (Intel-Format) File \"%1!s!\" contains \"don't care\" values -- overwriting them with 0s" 0 0 "Analysis & Synthesis" 0 -1 1614053605725 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "6 " "Inferred 6 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "tem_trans:inst9\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"tem_trans:inst9\|Mod0\"" {  } { { "tem_trans.v" "Mod0" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/tem_trans.v" 18 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1614053608005 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "tem_trans:inst9\|Div1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"tem_trans:inst9\|Div1\"" {  } { { "tem_trans.v" "Div1" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/tem_trans.v" 17 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1614053608005 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "trans:inst6\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"trans:inst6\|Mod0\"" {  } { { "trans.v" "Mod0" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/trans.v" 9 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1614053608005 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "trans:inst6\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"trans:inst6\|Div0\"" {  } { { "trans.v" "Div0" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/trans.v" 8 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1614053608005 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "trans:inst5\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"trans:inst5\|Mod0\"" {  } { { "trans.v" "Mod0" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/trans.v" 9 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1614053608005 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "trans:inst5\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"trans:inst5\|Div0\"" {  } { { "trans.v" "Div0" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/trans.v" 8 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1614053608005 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1614053608005 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "tem_trans:inst9\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"tem_trans:inst9\|lpm_divide:Mod0\"" {  } { { "tem_trans.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/tem_trans.v" 18 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614053608145 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tem_trans:inst9\|lpm_divide:Mod0 " "Instantiated megafunction \"tem_trans:inst9\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 31 " "Parameter \"LPM_WIDTHN\" = \"31\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614053608145 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614053608145 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614053608145 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614053608145 ""}  } { { "tem_trans.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/tem_trans.v" 18 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1614053608145 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_oll.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_oll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_oll " "Found entity 1: lpm_divide_oll" {  } { { "db/lpm_divide_oll.tdf" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/lpm_divide_oll.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053608251 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053608251 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_nlh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_nlh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_nlh " "Found entity 1: sign_div_unsign_nlh" {  } { { "db/sign_div_unsign_nlh.tdf" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/sign_div_unsign_nlh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053608320 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053608320 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_ohe.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_ohe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_ohe " "Found entity 1: alt_u_div_ohe" {  } { { "db/alt_u_div_ohe.tdf" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/alt_u_div_ohe.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053608420 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053608420 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_t3c.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_t3c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_t3c " "Found entity 1: add_sub_t3c" {  } { { "db/add_sub_t3c.tdf" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/add_sub_t3c.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053608515 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053608515 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_u3c.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_u3c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_u3c " "Found entity 1: add_sub_u3c" {  } { { "db/add_sub_u3c.tdf" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/add_sub_u3c.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053608590 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053608590 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "tem_trans:inst9\|lpm_divide:Div1 " "Elaborated megafunction instantiation \"tem_trans:inst9\|lpm_divide:Div1\"" {  } { { "tem_trans.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/tem_trans.v" 17 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614053608630 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tem_trans:inst9\|lpm_divide:Div1 " "Instantiated megafunction \"tem_trans:inst9\|lpm_divide:Div1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 31 " "Parameter \"LPM_WIDTHN\" = \"31\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614053608630 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614053608630 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614053608630 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614053608630 ""}  } { { "tem_trans.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/tem_trans.v" 17 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1614053608630 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ltl.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_ltl.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ltl " "Found entity 1: lpm_divide_ltl" {  } { { "db/lpm_divide_ltl.tdf" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/lpm_divide_ltl.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053608705 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053608705 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "trans:inst6\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"trans:inst6\|lpm_divide:Mod0\"" {  } { { "trans.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/trans.v" 9 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614053608781 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "trans:inst6\|lpm_divide:Mod0 " "Instantiated megafunction \"trans:inst6\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 7 " "Parameter \"LPM_WIDTHN\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614053608781 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614053608781 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614053608781 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614053608781 ""}  } { { "trans.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/trans.v" 9 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1614053608781 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_bkl.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_bkl.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_bkl " "Found entity 1: lpm_divide_bkl" {  } { { "db/lpm_divide_bkl.tdf" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/lpm_divide_bkl.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053608870 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053608870 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_akh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_akh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_akh " "Found entity 1: sign_div_unsign_akh" {  } { { "db/sign_div_unsign_akh.tdf" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/sign_div_unsign_akh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053608915 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053608915 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_uee.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_uee.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_uee " "Found entity 1: alt_u_div_uee" {  } { { "db/alt_u_div_uee.tdf" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/alt_u_div_uee.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053608990 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053608990 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "trans:inst6\|lpm_divide:Div0 " "Elaborated megafunction instantiation \"trans:inst6\|lpm_divide:Div0\"" {  } { { "trans.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/trans.v" 8 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614053609076 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "trans:inst6\|lpm_divide:Div0 " "Instantiated megafunction \"trans:inst6\|lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 7 " "Parameter \"LPM_WIDTHN\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614053609076 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614053609076 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614053609076 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1614053609076 ""}  } { { "trans.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/trans.v" 8 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1614053609076 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_8sl.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_8sl.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_8sl " "Found entity 1: lpm_divide_8sl" {  } { { "db/lpm_divide_8sl.tdf" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/db/lpm_divide_8sl.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614053609148 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053609148 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "OLED.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/OLED.v" 4 -1 0 } } { "OLED.v" "" { Text "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/OLED.v" 55 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1614053609982 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1614053609982 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1614053611973 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "9 " "9 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1614053617210 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/output_files/pro_1.map.smsg " "Generated suppressed messages file C:/Users/Lenovo/Desktop/project_2021winter/pro_1_19.1/output_files/pro_1.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053617310 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1614053617650 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614053617650 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "2273 " "Implemented 2273 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1614053617965 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1614053617965 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "1 " "Implemented 1 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1614053617965 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2259 " "Implemented 2259 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1614053617965 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1614053617965 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 66 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 66 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4788 " "Peak virtual memory: 4788 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1614053618000 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 23 12:13:38 2021 " "Processing ended: Tue Feb 23 12:13:38 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1614053618000 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:32 " "Elapsed time: 00:00:32" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1614053618000 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:47 " "Total CPU time (on all processors): 00:00:47" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1614053618000 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1614053618000 ""}
