module clock(hour_a,hour_d,min_a,min_d,clk_1ms,clk_500ms,hour_out,min_out,t_i_u);
input hour_a,hour_d,min_a,min_d,clk_1ms,clk_500ms;
output[6:0] hour_out,min_out;
output t_i_u;
reg t_i_u;
reg[6:0] hour_out,min_out;
reg[6:0] hour_mem,min_mem,hour_set,min_set,second;
initial
    begin
	 hour_mem = 0;
	 hour_set = 0;
	 hour_out = 0;
	 min_mem = 0;
	 min_set = 0;
	 min_out = 0;
	 second = 0;
	 t_i_u = 0;
	 end

always @(posedge clk_500ms)
    begin
	 if(hour_a == 0&&hour_d == 0&&min_a == 0&&min_d == 0)
	     begin
		  hour_set = 0;
		  min_set = 0;
		  end
	 else if(hour_a == 0)
	     hour_set = hour_set+1;
	 else if(hour_d == 0)
	     hour_set = hour_set-1;
	 else if(min_a == 0)
	     min_set = min_set+1;
	 else if(min_d == 0)
	     min_set = min_set-1;
	 if(hour_set == 24)
	     hour_set = 0;
	 if(hour_set > 24)
	     hour_set = 23;
	 if(min_set == 60)
	     min_set = 0;
	 if(min_set > 60)
	     min_set = 59;
	 end
	 
always @(posedge clk_1ms)
    begin
	 if(hour_set != hour_mem || min_set != min_mem)
		  begin
        hour_mem = hour_set;
        min_mem = min_set;
        hour_out = hour_set;
        min_out = min_set;
        end
    else
        begin
		  if(second < 60000)
		      second = second+1;
		  else
		      begin
				min_out = min_out+1;
				second = 0;
				if(min_out == 60)
				    begin
					 hour_out = hour_out+1;
					 min_out = 0;
					 t_i_u = ~t_i_u;
					 if(hour_out == 24)
					     begin
						  hour_out = 0;
						  end
					 end
				end
		  end  
	 end
endmodule