/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2019  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and any partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 16 16 168 96)
	(text "clk_1MHz" (rect 5 0 43 12)(font "Arial" ))
	(text "inst" (rect 8 64 20 76)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "clk" (rect 0 0 10 12)(font "Arial" ))
		(text "clk" (rect 21 27 31 39)(font "Arial" ))
		(line (pt 0 32)(pt 16 32)(line_width 1))
	)
	(port
		(pt 152 32)
		(output)
		(text "clk_1MHz" (rect 0 0 38 12)(font "Arial" ))
		(text "clk_1MHz" (rect 93 27 131 39)(font "Arial" ))
		(line (pt 152 32)(pt 136 32)(line_width 1))
	)
	(drawing
		(rectangle (rect 16 16 136 64)(line_width 1))
	)
)
